Technical Program

Session	Opening Session: Plenary, Awards Ceremony & Keynote Addresses
Session Code / Room	1.1 / Großer Saal
Date / Time	Tuesday, March 20, 2018 / 08:30 – 10:30
Chair	Jan Madsen, DATE 2018 General Chair, DTU, DK,
Co-Chair	Ayse Coskun, DATE 2018 Programme Chair, Boston University, US

08:30 – 08:45	WELCOME ADDRESSES Jan Madsen and Ayse Coskun
08:45 – 09:15	Presentation of Distinguished Awards
1.1.1 09:15 – 10:00	Keynote Address 1: The Responsibility Sensitive Safety (Rss) Formal Model Toward Safety Guarantees for Autonomous Vehicles Amnon Shashua
1.1.2 09:15 – 10:00	Keynote Address 2: Programming Living Cells: Design Automation to Map Circuits to Dann Christopher Voigt

Session Title	Executive Panel: How Electronics May Change Our Lives, and the World
Session Code / Room	2. 1 / Saal 2
Date / Time	Tuesday, March 20, 2018 / 11:30 – 13:30
Chair	Domic Antun, Synopsys, US

11:30 – 13:00

Executive Panel: How Electronics May Change Our Lives, and the World

Session Title	Energy Efficient Neural Networks
Session Code / Room	2.2 / Konf. 6
Date / Time	Tuesday, March 20, 2018 / 11:30 – 13:30
Chair	Hai (Helen) Li, Duke University, US
Co-Chair	Muhammad Shafique, Vienna University of Technology (TU Wien), AT

2.2.1 11:30–12:00	MATIC: Learning Around Errors for Efficient Low‐Voltage Neural Network Accelerators Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze and Visvesh Sathe
2.2.2 12:00–12:30	Maximizing System Performance by Balancing Computation Loads in LSTM Accelerators Junki Park, Jaeha Kung, Wooseok Yi c and Jae-Joon Kim
2.2.3 12:30–12:45	moDNN: Memory Optimal DNN Training on GPUs Xiaoming Chen, Danny Z. Chen and Xiaobo Sharon Hu
2.2.4 12:45–13:00	HyperPower: Power‐ and Memory‐Constrained Hyper‐Parameter Optimization for Neural Networks Dimitrios Stamoulis, Ermao Cai, Da‐Cheng Juan and Diana Marculescu

Session Title	High-Level Synthesis
Session Code / Room	2.3 / Konf. 1
Date / Time	Tuesday, March 20, 2018 / 11:30 – 13:00
Chair	Selma Saidi, Hamburg University of Technology, DE
Co-Chair	Daniel Ziener, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

2.3.1 11:30–12:00	Sensei: An Area-Reduction Advisor for FPGA High‐Level Synthesis Hsuan Hsiao and Jason H. Anderson
2.3.2 12:00–12:30	A Fast and Effective Lookahead and Fractional Search Based Scheduling Algorithm for High‐Level Synthesis Shantanu Dutt and Ouwen Shi
2.3.3 12:30–13:00	High‐Level Synthesis of Software‐Customizable Floating‐Point Cores Samridhi Bansal, Hsuan Hsiao, Tomasz Czajkowski and Jason H. Anderson

Session Title	Model Checking
Session Code / Room	2.4 / Konf. 2
Date / Time	Tuesday, March 20, 2018 / 11:30 – 13:00
chair	Armin Biere, JKU Linz, AT
co-chair	Daniel Große, University Bremen, DE

2.4.1 11:30–12:00	Efficient Verification of Multi‐Property Designs (The Benefit of Wrong Assumptions) Eugene Goldberg, Matthias Güdemann, Daniel Kroening and Rajdeep Mukherjee
2.4.2 12:00–12:30	Combining PDR and Reverse PDR for Hardware Model Checking Tobias Seufert and Christoph Scholl
2.4.3 12:30–12:45	Symbolic Quick Error Detection Using Symbolic Initial State for Pre-Silicon Verification Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivas Shashank Nuthakki, Subhasish Mitra, Clark Barrett, Dominik Stoffel and Wolfgang Kunz
2.4.4 12:45–13:00	Verification of Tree-Based Hierarchical Read-Copy Update in the Linux Kernel Lihao Liang, Paul E. McKenney, Daniel Kroening and Tom Melham

Session Title	GPU and GPU-based heterogeneous system management
Session Code / Room	2.5 /Konf. 3
Date / Time	Tuesday, March 20, 2018 / 11:30 – 13:00
Chair	Andrea Marongiu, Università di Bologna, IT
Co-Chair	Carles Hernandez, BSC, ES

2.5.1 11:30–12:00	HVSM: Hardware‐Variability Aware Streaming Processors’ Management Policy in GPUs Jingweijia Tan and Kaige Yan
2.5.2 12:00–12:30	Throughput Optimization and Resource Allocation on GPUs under Multi‐Application Execution Srinivasa Reddy Punyala, Theodoros Marinakis, Arash Komaee and Iraklis Anagnostopoulos
2.5.3 12:30–13:00	Set Variation-aware Shared LLC Management for CPU-GPU Heterogeneous Architecture Zhaoying Li, Lei Ju, Hongjun Dai, Xin Li, Mengying Zhao and Zhiping Jia

Session Title	Circuit Locking and Camouflaging
Session Code / Room	2.6 /Konf. 4
Date / Time	Tuesday, March 22, 2018/ 11:30 – 13:00
Chair	Debdeep Debdeep Mukhophyadhyay, IIT Kharagpur, IN
Co-Chair	Yiorgos Yiorgos Makris, UT Dallas, US

2.6.1 11:30–12:00	Cyclic Locking and Memristor‐based Obfuscation Against CycSAT and Inside Foundry Attacks Amin Rezaei,Yuanqi Shen, Shuyu Kong, Jie Gu and Hai Zhou
2.6.2 12:00–12:30	TimingCamouflage: Improving Circuit Security against Counterfeiting by Unconventional Timing Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan and Ulf Schlichtmann
2.6.3 12:30–13:00	Advancing Hardware Security Using Polymorphic and Stochastic Spin‐Hall Effect Devices Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu and Shaloo Rakheja

Session Title	Special Session: Spintronics based New Computing Paradigms and Applications
Session Code / Room	2.7 / Konf. 5
Date / Time	Tuesday, March 22, 2018 / 11:30 – 13:00
Chair	Zhao Weisheng, Beihang University, CN
Co-Chair	Tahoori Mehdi, Karlsruhe Institute of Technology, DE

2.7.1 11:30–11:45	Main memory organization trade‐offs with DRAM and STT-MRAM options based on gem5‐NVMain simulation frameworks Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenlladoy, José Ignacio Gómezy, Gouri Sankar Kar, Arnaud Furnemont, Francky Catthoor, Sophiane Sennix, David Novox, Abdoulaye Gamatiex and Lionel Torres
2.7.2 11:45–12:00	Exploring the Opportunity of Implementing Neuromorphic Computing Systems with Spintronic Devices Bonan Yan, Fan Chen, Yaojun Zhangy, Chang Song, Hai Li and Yiran Chen
2.7.3 12:00–12:15	Spintronic Normally-off Heterogeneous System-on-Chip Design Anteneh Gebregiorgis, Rajendra Bishnoiand Mehdi B. Tahoori
2.7.4 12:15–12:30	Magnetic Skyrmions for Future Potential Memory and Logic Applications: Alternative Information Carriers Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang and Weisheng Zhao
2.7.5 12:30–12:45	Novel Application of Spintronics in Computing, Sensing, Storage and Cybersecurity Seyedhamidreza Motaman, Mohammad Nasim Imtiaz Khan and Swaroop Ghosh
2.7.6 12:45–13:00	Large scale, high d ensity integration of All Spin Logic Qi AN, Sébastien Le Beux, Ian O’Connor and Jacques‐Olivier Klein

Session Title	Enabling ICT Innovations for European SMEs
Session Code / Room	2.8 /Exhibition Theatre
Date / Time	Tuesday, March 22, 2018 / 14:30 - 16:00
Organisers	Rainer Leupers, RWTH Aachen, DE Bernd Janson, ZENIT GmbH, DE
Co-Chair	Giovanni De Micheli, EPFL, CH,

2.8.1 11:30–11:45	Presentation of Tetramax Rainer Leupers
2.8.2 11:45–12:00	The Fed4Sae Project, Accelerating European CPS Solutions to Market Isabelle Dor
2.8.3 12:00–12:15	Open Innovation Business Based on Efficient Networking Bernd Janson
2.8.4 12:15–12:30	The Silexica Multicore Solution Juan Eusse
2.8.5 12:30–12:40	Transferring Research Results to Safety-Relevant Products: Case Study on Automated Driving Software Robert Schubert
2.8.6 12:40–13:00	Intenta GMBH Bernd Janson

Session Title	Executive Session: Design Automation for Quantum Computing
Session Code / Room	3.1 / Saal 2
Date / Time	Tuesday, March 20, 2018 / 14:30 – 16:00
Chair	Charbon Edoardo, TU Delft / EPFL, NL
Co-Chair	Große Daniel, University of Bremen, DE

3.1.0

Programming Quantum Computers Using Design Automation
Mathias Soeken, Thomas Haener and Martin Roetteler

Session Title	Approximate and Near-Threshold Computing
Session Code / Room	3.2 / Konf. 6
Date / Time	Tuesday, March 20, 2018 / 14:30 – 16:00
Chair	Semeen Rehman, Vienna University of Technology (TU Wien), AT
Co-Chair	Saibal Mukhopadhyay, Univ. Pierre et Marie Curie, FR

3.2.1 14:30–15:00	Energy Proportionality in Near-Threshold Computing Servers and Cloud Data Centers: Consolidating or Not? Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini and David Atienza
3.2.2 15:00–15:30	Lookup Table Allocation for Approximate Computing with Memory under Quality Constraints Ye Tian, Qian Zhang, Ting Wang and Qiang Xu
3.2.3 15:30–16:00	Accelerating Biophysical Neural Network Simulation with Region of Interest based Approximation Yun Long, Xueyuan Sheand Saibal Mukhopadhyay

Session Title	Optimization Techniques for MPSoCs
Session Code / Room	3.3 / Konf. 1
Date / Time	Tuesday, March 20, 2018 / 14:30 - 16:00
chair	Stefan Wildermann, FAU Erlangen-Nuremberg, DE
Co-chair	Michael Glass, Ulm University, DE

3.3.1 14:30–15:00	DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications Jinghan Zhang, Hamed Tabkhi and Gunar Schirner
3.3.2 15:00–15:30	Variation-Aware Task Allocation and Scheduling for Improving Reliability of Real-Time MPSoCs Junlong Zhou, Tongquan Wei, Mingsong Chen, X. Sharon Hu, Yue Ma, Gongxuan Zhang and Jianming Yan
3.3.3 15:30–16:00	Topology‐aware Virtual Resource Management for Heterogeneous Multicore Systems Jianmin Qian, Jian Liand Ruhui Ma

Session Title	Optimizing Computing with Neuromorphic Architectures and Accelerators
Session Code / Room	3.4 / Konf. 2
Date / Time	Tuesday, March 20, 2018/ 14:30 – 16:00
Chair	Dimitrios Soudris, UNTUA, GR
Co-Chair	Ioana Vatajelu, TIMA, FR

3.4.1 14:30–15:00	Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Network Heechun Park and Taewhan Kim
3.4.2 15:00–15:30	CCR: A Concise Convolution Rule for Sparse Neural Network Accelerators Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu f and Xiaowei Li

Session Title	Memory Reliability
Session Code / Room	3.5 /Konf. 3
Date / Time	Tuesday, March 20, 2018 / 14:30 – 16:00
Chair	Jose Pineda, NXP, NL
Co-Chair	Mehdi Tahoori, Karlsruhe Institute of Technology, DE

3.5.1 14:30–15:00	Gradient Importance Sampling: an Efficient Statistical Extraction Methodology of High‐Sigma SRAM Dynamic Characteristics Thomas Haine, Johan Segers, Denis Flandre and David Bol
3.5.2 15:00–15:30	Degradation Analysis of High Performance 14nm FinFET SRAM Daniël Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans and Francky Catthoor
3.5.3 15:30–16:00	Investigating Power Outage Effects on Reliability of Solid‐State Drives Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi and Hossein Asadi

Session Title	Real-time Multiprocessing
Session Code / Room	3.6 / Konf. 4
Date / Time	Tuesday, March 22, 2018 / 14:30 – 16:00
Chair	Jian-Jia Chen, TU Dortmund, DE
Co-Chair	Rolf Ernst, TU Braunschweig, DE

3.6.1 14:30–15:00	Workload-Aware Harmonic Partitioned Scheduling for Probabilistic Real‐Time Systems Jiankang Ren, Ran Bi, Xiaoyan Su, Qian Liu, Guowei Wu and Guozhen Tan
3.6.2 15:00–15:30	Buffer‐aware bounds to multi‐point progressive blocking in priority‐preemptive NoCs Leandro Soares Indrusiak, Alan Burns and Borislav Nikolić
3.6.3 15:30–15:45	A Design‐Space Exploration for Allocating Security Tasks in Multicore Real‐Time Systems Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni and Rakesh B. Bobba
3.6.4 15:45–16:00	Design and Analysis of Semaphore Precedence Constraints: a Model‐based Approach for Deterministic Communications Thanh‐Dat Nguyen, Yassine Ouhammou, Emmanuel Grolleau, Julien Forget, Claire Pagetti and Pascal Richard

Session Title	Innovative Products for Autonomous Driving (part 1)
Session Code / Room	3.8 / Exhibition Theatre
Date / Time	Tuesday, March 20, 2018 / 14:30 – 16:00
Organiser	Hans-Jürgen Brand, IDT/ZMDI, DE

3.8.1 14:30–15:00	Design of Functional Safety Products for Autonomous Driving Christian Wolf
3.8.2 15:00–15:30	5G Connected Cars Stanislav Mudriievskyi
3.8.3 15:30–16:00	Foundry Solutions for Autonomous Driving Alexander Muffler

Session Title	Interactive Presentations
Session Code / Room	IP1 /Conference Floor
Date / Time	Tuesday, March 20, 2018 / 16:00 – 16:30
Chair	Gianluca Palermo, politecnico di Milano, IT
Co-Chair	Ingo Sander, KTH Royal Institute of Technology

IP1-1	RECOM: An Efficient Resistive Accelerator for Compressed Deep Neural Networks Houxiang Ji, Linghao Song,Li Jiang, Hai(Halen) Li and Yiran Chen
IP1-2	SparseNN: An Energy‐Efficient Neural Network Accelerator Exploiting Input and Output Sparsity Jingyang Zhu, Jingbo Jiang, Xizi Chen and Chi‐Ying Tsui
IP1-3	ACCLIB: Accelerators as Libraries Jacob R. Stevens, Yue Du, Vivek Kozhikkottu and Anand Raghunathan
IP1-4	HPXA: A Highly Parallel XML Parser Isaar Ahmad, Sanjog Patiland Smruti R. Sarangi
IP1-5	QoR-Aware Power Capping for Approximate Big Data Processing Seyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi and Sherief Reda
IP1-6	Exact Multi-Objective Design Space Exploration using ASPmT Kai Neubauer, Philipp Wanko, Torsten Schaub and Christian Haubelt
IP1-7	HIPE: HMC Instruction Predication Extension Applied on Database Processing Diego G. Tomé, Paulo C. Santos, Luigi Carro, Eduardo C. Almeida and Marco A. Z. Alves
IP1-8	Parametric Failure Modeling and Yield Analysis for STT‐MRAM Sarath Mohanachandran Nair, Rajendra Bishnoiand Mehdi B. Tahoori
IP1-9	One‐Way Shared Memory Martin Schoeberl
IP1-10	An Efficient Resource-Optimized Learning Prefetcher for Solid State Drives Rui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang and Teng Tian
IP1-11	Bridging Discrete and Continuous Time Models with Atoms George Ungureanu, José E. G. de Medeiros and Ingo Sander
IP1-12	OHEX: OS-Aware Hybridization Techniques for Accelerating MPSoC Full-System Simulation Róbert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies and Andreas Hoffmann
IP1-13	A Highly Efficient Full‐System Virtual Prototype Based on Virtualization‐Assisted Approach Hsin‐I Wu, Chi-Kang Chen, Tsung‐Ying Lu and Ren‐Song Tsay
IP1-14	Industrial Evaluation of Transition Fault Testing for Cost Effective Offline Adaptive Voltage Scaling Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, and Zaid Al‐Ars
IP1-15	An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs Deepak M. Mathew, Martin Schultheis, Carl C. Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn and Matthias Jung
IP1-16	A Boolean Model for Delay Fault Testing of Emerging Digital Technologies based on Ambipolar Devices Marcello Dalpasso, Davide Bertozzi and Michele Favalli
IP1-17	ATPG Power Guards: On Limiting the Test Power below Threshold Rohini Gulve and Virendra Singh

Session Title	Executive Session: Exact Synthesis and SAT
Session Code / Room	4.1 / Saal 2
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Amaru Luca, Synopsys, US
Co-Chair:	Patrick Vuillod, Synopsys, FR

4.1.1 17:00–17:30	Improving Circuit Size Upper Bounds Using SAT‐Solvers Alexander S. Kulikov
4.1.2 17:30–18:00	Practical Exact Synthesis (Executive Session Paper) Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca G. Amarù, Robert K. Brayton and Giovanni De Micheli
4.1.3 18:00–18:30	SAT‐based Redundancy Removal Krishanu Debnath, Rajeev Murgai, Mayank Jain and Janet Olson

Session Title	Domain Specific Design Methodologies
Session Code / Room	4.2 / Konf. 6
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Frédéric Pétrot, Grenoble Institute of Technology, FR
Co-Chair:	David Novo, French National Centre for Scientific Research, FR

4.2.1 17:00–17:30	Approximate Computing for Biometric Security Systems: A Case Study on Iris Scanning Soheil Hashemi, Hokchhay Tann, Francesco Buttafuoco and Sherief Reda
4.2.2 17:30–18:00	Flash Read Disturb Management Using Adaptive Cell Bit-Density with In-Place Reprogramming Tai-Chou Wu, Yu-Ping Maand Li-Pin Chang
4.2.3 18:00–18:30	HTF‐MPR: A Heterogeneous TensorFlow Mapper Targeting Performance using Genetic Algorithms and Gradient Boosting Regressors Ahmad Albaqsami, Maryam S. Hosseiniand Nader Bagherzadeh

Session Title	System Modelling for Simulation and Optimisation
Session Code / Room	4.3 / Konf. 1
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Frederic Mallet, Universite Nice Cote d'Azur, FR
Co-Chair:	Gianluca Palermo, Politecnico di Milano, IT

4.3.1 17:00–17:30	CAMP: Accurate Modeling of Core and Memory Locality for Proxy Generation of Big-data Applications Reena Panda, Xinnian Zheng, Andreas Gerstlauer and Lizy Kurian John
4.3.2 17:30–18:00	SmartShuttle: Optimizing Off‐Chip Memory Accesses for Deep Learning Accelerators Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong Jingya Wu and Xiaowei Li
4.3.3 18:00–18:30	Port Call Path Sensitive Conflict Analysis for Instance-Aware Parallel SystemC Simulation Tim Schmidt, Zhongqi Cheng and Rainer Dömer

Session Title	Overcoming the Limitations of Worst-Case IC Design
Session Code / Room	4.4 / Konf. 2
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Vasilis Pavlidis, University of Manchester, GB
Co-Chair:	Giorgios Karakonstantis, Queen's University Belfast, GB

4.4.1 17:00–17:30	Trident: A Comprehensive Timing Error Resilient Technique against Choke Points at NTC Aatreyi Bal, Sanghamitra Royand Koushik Chakraborty
4.4.2 17:30–18:00	Bayesian Theory based Switching Probability Calculation Method of Critical Timing Path for On‐Chip Timing Slack Monitoring Byung Su Kim and Joon‐Sung Yang
4.4.3 18:00–18:30	Performance Based Tuning of an Inductive Integrated Voltage Regulator Driving a Digital Core against Process and Passive Variations Venakata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh and Saibal Mukhopadhyay

Session Title	Test: innovative infrastructures and ATPG techniques
Session Code / Room	4.5 / Konf. 3
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Danilo Pau, STMicroelectronics, IT
Co-Chair:	Lukasz Rybak, Mentor Graphics Poland, PL

4.5.1 17:00–17:30	Pre-Assembly Testing of Interconnects in Embedded Multi-Die Interconnect Bridge (EMIB) Dies Sudipta Mondal and Krishnendu Chakrabarty
4.5.3 18:00–18:15	On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths Felipe A. Kuentzer, Leonardo R. Juracyand Alexandre M. Amory
4.5.4 18:15–18:30	Characterization of Possibly Detected Faults by Accurately Computing their Detection Probability Jan Burchard, Dominik Erb and Bernd Becker

Session Title	Special Session: Securing Power-constrained System-on-Chips: Challenges and Opportunities
Session Code / Room	4.6 / Konf. 4
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Mukhopadhyay Saibal, School of ECE, Georgia Institute of Technology, US

4.6.1 17:00–17:15	Ultra‐low Energy Circuit Building Blocks for Security Technologies Sanu Mathew, Sudhir Satpathy, Vikram Suresh and Ram Krishnamurthy
4.6.2 17:15–17:40	Embedded Randomness and Data Dependencies Design Paradigm: Advantages and Challenges Itamar Levi, Yehuda Rudin, Alexander Fish and Osnat Keren
4.6.3 17:40–18:05	Exploiting On‐chip Power Management for Side‐Channel Security Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan,e, Vivek De and Saibal Mukhopadhyay

Session Title	Adaptive Reliable Computing Using Memristive and Reconfigurable Hardware
Session Code / Room	4.7 / Konf. 5
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Chair:	Walter Weber Walter Weber, NAMLAB, DE
Co-Chair:	Alessandro Cilardo, University of Naples Federico II, IT

4.7.1 17:00–17:30	Rescuing Memristor‐based Computing with Non‐linear Resistance Levels Jilan Lin, Lixue Xia, Zhenhua Zhu, Hanbo Sun, Yi Cai, Hui Gao, Ming Cheng, Xiaoming Chen, Yu Wang and Huazhong Yang
4.7.2 17:30–18:00	PX‐CGRA: Polymorphic Approximate Coarse‐Grained Reconfigurable Architecture Omid Akbari, Mehdi Kamal, Ali Afzali‐Kusha, Massoud Pedram and Muhammad Shafique
4.7.3 18:00–18:15	Multi‐Precision Convolutional Neural Networks on Heterogeneous Hardware Moslem Amiri, Mohammad Hosseinabady, Simon McIntosh‐Smith and Jose Nunez‐Yanez
4.7.4 18:15–18:30	Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays Onur Tunali and Mustafa Altun

Session Title	Components for Secure IoT Systems
Session Code / Room	4.8 / Exhibition Theatre
Date / Time	Tuesday, March 20, 2018 / 17:00 – 18:30
Organiser:	Jürgen Haase, edacentrum, DE

4.8.1 17:00–17:30	Securing the Internet of Things With Ti Simplelink Platform Roger Monk
4.8.2 17:30–18:30	Development of A Near-Threshold Digital Cell Library and a Design Flow for IoT Sensor Systems Jörg Doblaski

Session Title	Special Day Session on Future and Emerging Technologies: Challenges for the Design of Microfluidic Devices: EDA for your Lab-on-a-Chip
Session Code / Room	5.1 / Saal 2
Date / Time	Tuesday, March 22, 2018 / 17:00 – 18:30
Chair	Chakrabarty Krishnendu, Duke University, US

5.1.1 08:30–09:00	Point-of-Care Diagnostics 2.0: Standards, Design Automation, and Consumer Electronics for the Next Generation of Diagnostic Devices Emmanuel Delamarche
5.1.2 09:00–09:30	Design Automation in Microfluidics: An Experimentalist's Perspective William H. Grover
5.1.3 09:30–10:00	Chemofluidics: Prospects and Challenges Andreas Richter

Session Title	Smart Energy and Automotive Systems
Session Code / Room	5.2 / Konf. 6
Date / Time	Wednesday, March 21, 2018 / 08:30 – 10:00
Chair	Bart Vermeulen, NXP, NL
Co-Chair	Massimo Poncino, Politecnico di Torino, IT

5.2.1 08:30–09:00	SOH-Aware Active Cell Balancing Strategy For High Power Battery Packs Alma Pröbstl, Sangyoung Park, Swaminathan Narayanaswamy, Sebastian Steinhorst and Samarjit Chakraborty
5.2.2 09:00–09:30	GIS-Based Optimal Photovoltaic Panel Floorplanning for Residential Installations Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii and Massimo Poncino
5.2.3 09:30–10:00	Cell‐based Update Algorithm for Occupancy Grid Maps and Hybrid Map for ADAS on Embedded GPUs Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich and Mohamed Essayed Bouzouraa

Session Title	Heterogeneous multi-level caching
Session Code / Room	5.3 / Konf. 1
Date / Time	Wednesday, March 21, 2018 / 08:30 – 10:00
Chair	Jeronimo Castrillon, Technische Universität Dresden, DE
Co-Chair	Lei Ju, Shandong University, CN

5.3.1 08:30–09:00	WALL: A Writeback‐Aware LLC Management for PCM‐based Main Memory Systems Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu and Gokhan Memik
5.3.2 09:00–09:30	Design and Integration of Hierarchical‐Placement Multi‐level Caches for Real‐Time Systems Pedro Benedicte, Carles Hernandez, Jaume Abella and Francisco J. Cazorla
5.3.3 09:30–10:00	LARS: Logically Adaptable Retention Time STT‐RAM Cache for Embedded Systems Kyle Kuan and Tosiron Adegbija

Session Title	Special Session: Lightweight Security for Resources-Constrained Internet-of-Things Applications
Session Code / Room	5.4 /Konf. 2
Date / Time	Wednesday, March 21, 2018 / 08:30 – 10:00
Chair	Halak Basel, Southampton University, GB
Co-Chair	Jin Yier, University of Florida, US

5.4.1 08:30–08:45	Cost‐Efficient Design for Modeling Attacks Resistant PUFs Mohd Syafiq Mispan, Haibo Su, Mark Zwolinski and Basel Halak
5.4.2 08:45–09:10	Device Attestation: Past, Present, and Future Orlando Arias, Fahim Rahman, Mark Tehranipoor and Yier Jin
5.4.3 09:10–09:35	A Reconfigurable Scan Network based IC Identification for Embedded Devices Omid Aramoon, Xi Chenand and Gang Qu
5.4.4 09:35–10:00	Early Detection of System‐Level Anomalous Behaviour using Hardware Performance Counters Lai Leng Woo, Mark Zwolinski and Basel Halak

Session Title	Emerging Technologies for Future Computing
Session Code / Room	5.5 / Konf. 3
Date / Time	Wednesday, March 21, 2018 / 08:30 – 10:00
Chair	Aida Todri-Sanial Aida Todri-Sanial, CNRS, FR
Co-Chair	Mariagrazia Graziano Mariagrazia Graziano, Politecnico di Torino, IT

5.5.1 08:30–09:00	Compact Modeling of Carbon Nanotube Thin Film Transistors for Flexible Circuit Design Leilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond Beausoleil and Kwang-Ting Cheng
5.5.2 09:00–09:30	A High‐Speed Design Methodology for Inductive Coupling Links in 3D‐ICs Benjamin J. Fletcher, Shidhartha Das and Terrence Mak
5.5.3 09:30–09:45	An Exact Method for Design Exploration of Quantum‐dot Cellular Automata Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres and Rolf Drechsler
5.5.4 09:45–10:00	Accurate Margin Calculation for Single Flux Quantum Logic Cells Soheil Nazar Shahsavani, Bo Zhangand Massoud Pedram

Session Title	Reliability improvement and evaluation techniques
Session Code / Room	5.6 /Konf. 4
Date / Time	Tuesday, March 22, 2018 / 08:30 – 10:00
Chair	Stefano Di Carlo, Politecnico di Torino, IT
Chair	Vasileios Tenentes, University of Southampton, GB

5.6.1 08:30–09:00	Improving Reliability for Real‐Time Systems through Dynamic Recovery Yue Ma, Thidapat Chantem, Robert P. Dick and X. Sharon Hu
5.6.2 09:00–09:30	Optimal Metastability‐Containing Sorting Networks Johannes Bund, Christoph Lenzen and Moti Medina
5.6.3 09:30–09:45	MAUI: Making Aging Useful, Intentionally Kai‐Chiang Wu, Tien‐Hung Tseng and Shou‐Chun Li
5.6.4 09:45–10:00	EXPERT: Effective and Flexible Error Protection by Redundant Multi Threading Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, and Kyoungwoo Lee

Session Title	Software-centric techniques for embedded systems
Session Code / Room	5.7 / Konf. 5
Date / Time	Wednesday, March 29, 2018/ 08:30 – 10:00
Chair	Marc Geilen, Eindhoven University of Technology, NL
Co-Chair	Daniel Ziener, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

5.7.1 08:30–09:00	HePREM: Enabling Predictable GPU Execution on Heterogeneous SoC Björn Forsberg, Luca Benini and Andrea Marongiu
5.7.2 09:00–09:15	Circuit Carving: A Methodology for the Design of Approximate Hardware Ilaria Scarabottolo, Giovanni Ansaloni and Laura Pozzi
5.7.3 09:15–09:30	ICNN: An Iterative Implementation of Convolutional Neural Networks to Enable Energy and Computational Complexity Aware Dynamic Approximation Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun c and Avesta Sasan
5.7.4 09:30–09:45	Task Scheduling for Many‐Cores with S‐NUCA Caches Anuj Pathania and Jörg Henkel
5.7.5 09:45–10:00	KVSSD: Close Integration of LSM Trees and Flash Translation Layer for Write-Efficient KV Store Sung-Ming Wu, Kai-Hsiang Linand Li-Pin Chang

Session Title	Interactive Presentations
Session Code / Room	IP2 /Conference Floor
Date / Time	Wednesday, March 21, 2018 / 10:00 – 10:30

IP2-1	In‐growth Test for Monolithic 3D Integrated SRAM Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang and Li Jiang
IP2-2	A Co‐design Methodology for Scalable Quantum Processors and their Classical Electronic Interface Jeroen van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon and Fabio Sebastiano
IP2-3	Approximate Quaternary Addition with the Fast Carry Chains of FPGAs Sina Boroumand, Hadi P. Afshar and Philip Brisk
IP2-4	NN Compactor: Minimizing Memory and Logic Resources for Small Neural Networks Seongmin Hong,Inho Lee and Yongjun Park
IP2-5	Improving Fast Charging Efficiency of Reconfigurable Battery Packs Alexander Lamprecht, Swaminathan Narayanaswamy and Sebastian Steinhorst
IP2-6	Cloud‐assisted Control of Ground Vehicles using Adaptive Computation Offloading Techniques Arun Adiththan, Ramesh S and Soheil Samii
IP2-7	FusionCache: using LLC Tags for DRAM Cache Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso and Ioannis Sourdis
IP2-8	Improved Synthesis of Clifford+T Quantum Functionality Philipp Niemann, Robert Wille and Rolf Drechsler
IP2-9	Energy-Efficient Channel Alignment of DWDM Silicon Photonic Transceivers Yuyang Wang, M. Ashkan Seyedi, Rui Wu, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil and Kwang-Ting Cheng
IP2-10	A Physical Synthesis Flow for Early Technology Evaluation of Silicon Nanowire based Reconfigurable FETs Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andrè Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber and Akash Kumar
IP2-11	ETISS-ML: A Multi-Level Instruction Set Simulator with RTL-level Fault Injection Support for the Evaluation of Cross-Layer Resiliency Techniques Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra and Ulf Schlichtmann
IP2-12	Precise Evaluation of the Fault Sensitivity of OOO Superscalar Processors Rafael Billig Tonetto, Gabriel L. Nazarand Antonio Carlos Schneider Beck
IP2-13	StreamFTL: Stream‐level Address Translation Scheme for Memory Constrained Flash Storage Hyukjoong Kim, Kyuhwa Hanand Dongkun Shin
IP2-14	Online Concurrent Workload Classification for Multi-core Energy Management Basireddy Karunakar Reddy, Geoff V. Merrett, Bashir M. Al-Hashimi and Amit Kumar Singh
IP2-15	AIM: Fast and Energy‐Efficient AES In‐Memory Implementation for Emerging Non‐volatile Main Memory Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuangang Wang and Yuan Xie
IP2-16	SAT‐based Bit‐flipping Attack on Logic Encryptions Yuanqi Shen, Amin Rezaeiand Hai Zhou
IP2-17	AMS Verification Methodology regarding Supply Modulation in RF SoCs induced by Digital Standard Cells Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich and Stefan Heinen

Session Title	Special Day Session on Future and Emerging Technologies: Transistors for Digital NanoSystems: The Road Ahead
Session Code / Room	6.1 / Saal 2
Date / Time	Wednesday, March 21, 2018 / 11:00 – 12:30
Chair	Aitken Rob, ARM, US

6.1.3
12:00–12:30

Towards High‐Performance Polarity‐Controllable FETs with 2D Materials
Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthor, Iuliana P. Radu, Giovanni De Micheli and Pierre‐Emmanuel Gaillardon

Session Title	Memory Security
Session Code / Room	6.2 / Konf. 6
Date / Time	Wednesday, March 21, 2018 / 11:00 – 12:30
Chair	Francesco Regazzoni, ALaRI USI, CH
Co-Chair	Todd Austin, University of Michigan, US

6.2.1 11:00–11:30	Dynamic Skewed Tree for Fast Memory Integrity Verification Saru Vig, Guiyuan Jiang and Siew‐Kei Lam
6.2.2 11:30–12:00	Earthquake ‐ A NoC‐based Optimized Differential Cache‐Collision Attack for MPSoCs Cezar Reinbrecht, Bruno Forlin, Andreas Zankl and Johanna Sepúlveda
6.2.3 12:00–12:30	A Fast and Resource Efficient FPGA Implementation of Secret Sharing for Storage Applications Jakob Stangl, Thomas Lorünser and Sai Manoj Pudukotai Dinakarrao

Session Title	Advances in AMS/RF Design & Test Automation and Beyond
Session Code / Room	6.3 /Konf. 1
Date / Time	Wednesday, March 21, 2018/ 11:00 – 12:30
Chair	Marie-Minerve Louerat, LIP6, FR

6.3.1 11:00–11:30	Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA‐II Optimization Kernel Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Póvoa and Nuno Horta
6.3.2 11:30–12:00	A SystemC‐based Simulator for Design Space Exploration of Smart Wireless Systems Gabriele Miorandi, Francesco Stefanni, Federico Fraccaroli and Davide Quaglia
6.3.3 12:00–12:15	A Circuit-Design-Driven Tool with a Hybrid Automation Approach for SAR ADCs in IoT Ming Ding, Guibin Chen, Pieter Harpe, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips and Arthur van Roermund

Session Title	Modeling, Control and Scheduling for Cyber-Physical Systems
Session Code / Room	6.4 / Konf. 2
Date / Time	Wednesday, March 21, 2018 / 11:00 – 12:30
Chair	Shiyan Hu, Michigan Tech., US
Co-Chair	Franco Fummi, University of Verona, IT

6.4.1 11:00–11:30	Automatic Integration of Cycle-accurate Descriptions with Continuous‐time Models for Cyber‐Physical Virtual Platforms Michele Lora, Stefano Centomo, Davide Quaglia and Franco Fummi
6.4.2 11:30–12:00	Stability‐Aware Integrated Routing and Scheduling for Control Applications in Ethernet Networks Rouhollah Mahfouzi, Amir Aminifar, Soheil Samii, Ahmed Rezine, Petru Eles and Zebo Peng
6.4.3 12:00–12:15	Feedback Control of Real-Time EtherCAT Networks for Reliability Enhancement in CPS Liying Li, Peijin Cong, Kun Cao, Junlong Zhou, Tongquan Wei, Mingsong Chen and Xiaobo Sharon Hu
6.4.4 12:15–12:30	Cache-Aware Task Scheduling for Maximizing Control Performance Wanli Chang, Debayan Roy, Xiaobo Sharon Hu and Samarjit Chakraborty

Session Title	Special Session: Three Years of Low-Power Image Recognition Challenge
Session Code / Room	6.5 / Konf. 3
Date / Time	Wednesday, March 21, 2018 / 11:00 – 12:30
Chair	Yung-Hsiang Lu, Purdue University, US

6.5.1 11:00–11:15	Three Years of Low‐Power Image Recognition Challenge: Introduction to Special Session Kent Gauen, Ryan Dailey, Yung-Hsiang Lu, Eunbyung Park, Wei Liu, Alexander C. Berg and Yiran Chen
6.5.2 11:15–11:40	Real‐time object detection towards high power efficiency Jincheng Yu, Kaiyuan Guo, Yiming Hu, Xuefei Ning, Jiantao Qiu, Huizi Mao, Song Yao, Tianqi Tang, Boxun Li, Yu Wang and Huazhong Yang
6.5.3 11:40–12:05	A Retrospective Evaluation of Energy‐Efficient Object Detection Solutions on Embedded Devices Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li and Xiaowei Li
6.5.4 12:05–12:30	Joint Optimization of Speed, Accuracy, and Energy for Embedded Image Recognition Systems Duseok Kang, DongHyun Kang, Jintaek Kang, Sungjoo Yoo and Soonhoi Ha

Session Title	Innovative Products for Autonomous Driving (part 2)
Session Code / Room	6.8 / Exhibition Theatre
Date / Time	Wednesday, March 21, 2018 / 11:00 – 12:30
Organiser	Hans-Jürgen Brand , IDT/ZMDI, DE

6.8.1 11:00–11:30	22Fdx Ultra-Low-Voltage Design Based on Adaptive Body Bias Holger Eisenreich
6.8.2 11:30–12:00	A New Adas Chip Design in 22 NM Fdsoi Technology for Automotive Computer Vision Applications Jens Benndorf
6.8.3 12:00–12:30	Accelerating Physical Signoff for Leading Edge Chip Designs David DeMarcos

Session Title	LUNCH TIME KEYNOTE SESSION: From inverse design to implementation of robust and efficient photonics for computing
Session Code / Room	7.0 / Saal 2
Date / Time	Wednesday, March 21, 2018 / 13:35 – 14:20
Chair	Ayse Coskun, Boston University, US

7.0.1 13:45 – 13:50	Presentation of the IEEE TCCPS Technical Achievement Award to Prof. Alberto Sangiovanni-Vincentelli Christopher Voigt
7.0.2 13:50 – 14:20	Keynote Address 3: From inverse design to implementation of robust and efficient photonics for computing Jelena Vuckovic

Session Title	Special Day Session on Future and Emerging Technologies: Theoretical and practical aspects of verification of quantum computers
Session Code / Room	7.1 / Saal 2
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Naveh Yehuda, IBM Research, Is

7.1.0

Theoretical and Practical Aspects of Verification of Quantum Computers
Yehuda Naveh, Elham Kashefi, James R. Wootton and Koen Bertels

Session Title	Special Day Session on Future and Emerging Technologies: Theoretical and practical aspects of verification of quantum computers
Session Code / Room	7.2 / Konf. 6
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Pascal Vivet, CEA-Leti, FR
Co-Chair	Donghwa Shin, Yeungnam Univ. Daegu, KR

7.2.1 14:30–15:00	Airavat: Improving Energy Efficiency of Heterogeneous Applications Trinayan Baruah, Yifan Sun, Shi Dong, David Kaeli and Norm Rubin
7.2.2 15:00–15:30	All‐Digital Embedded Meters for On‐line Power Estimation Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii and Massimo Poncino
7.2.3 15:30–15:45	PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation Davide Zoni, Luca Cremona and William Fornaciari
7.2.4 15:45–16:00	Design Optimization of Photovoltaic Arrays on Curved Surfaces Sangyoung Park and Samarjit Chakraborty

Session Title	Advances in Logic Synthesis and Technology Mapping
Session Code / Room	7.3 / Konf. 1
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Mathias Soeken, EPFL, CH
Co-Chair	Luciano Lavagno, Politecnico di Torino, ITz

7.3.1 14:30–15:00	Improvements to Boolean Resynthesis Luca Amarú, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert Brayton and Giovanni De Micheli
7.3.2 15:00–15:30	Logic Optimization with Considering Boolean Relations Tung‐Yuan Lee, Chia‐Cheng Wu, Chia‐Chun Lin, Yung‐Chih Chen and Chun‐Yao Wang
7.3.3 15:30–15:45	Technology Mapping Flow for Emerging Reconfigurable Silicon Nanowire Transistors Shubham Rai, Michael Raitza and Akash Kumar
7.3.4 15:45–16:00	Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee Yung‐An Lai, Chia‐Chun Lin, Chia‐Cheng Wu, Yung‐Chih Chen and Chun-Yao Wang

Session Title	DRAM and NVMs
Session Code / Room	7.4 / Konf. 2
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Francisco Cazorla, BSC, ES
Co-Chair	Olivier Sentieys, IRISA, FR

7.4.1 14:30–15:00	Row-Buffer Hit Harvesting in Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems Yang Song, Olivier Alavoine and Bill Lin
7.4.2 15:00–15:30	AdAM: Adaptive Approximation Management for the Non‐Volatile Memory Hierarchies Mohammad Taghi Teimoori, Muhammad Abdullah Hanif, Alireza Ejlali and Muhammad Shafique
7.4.3 15:30–16:00	A Cross‐layer Adaptive Approach for Performance and Power Optimization in STT-MRAM Nour Sayed, Rajendra Bishnoi, Fabian Oboril c and Mehdi B. Tahoori

Session Title	Reliability Modeling and Mitigation
Session Code / Room	7.5 / Konf. 3
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Said Hamdioui, TU Delft, NL
Co-Chair	Bram Kruseman, NXP, NL

7.5.1 14:30–15:00	Low‐Cost High‐Accuracy Variation Characterization for Nanoscale IC Technologies via Novel Learningbased Techniques Zhijian Pan, Miao Li, Jian Yao, Hong Lu, Zuochang Ye, Yanfeng Li and Yan Wang
7.5.2 15:00–15:30	Mitigation of NBTI Induced Performance Degradation in On‐Chip Digital LDOs Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu and Selçuk Köse
7.5.3 15:30–16:00	Evaluating the Impact of Execution Parameters on Program Vulnerability in GPU Applications Fritz G. Previlon, Charu Kalra, David R. Kaeli and Paolo Rech

Session Title	Special Session: Next Generation Processors and Architectures for Deep Learning
Session Code / Room	7.6 / Konf. 4
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Theocharides Theocharis, University of Cyprus, CY
Co-Chair	Shafique Muhammad, TU Wien, AT

7.6.1 14:30–14:45	ReRAM‐based Accelerator for Deep Learning Bing Li, Linghao Song, Fan Chen, Xuehai Qian, Yiran Chen and Hai (Helen) Li
7.6.2 14:45–15:10	Exploiting Approximate Computing for Deep Learning Acceleration Chia‐Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Viji Srinivasan and Swagath Venkataramani
7.6.3 15:10–15:35	An Overview of Next-Generation Architectures for Machine Learning: Roadmap, Opportunities and Challenges in the IoT Era Muhammad Shafique, Theocharis Theocharides, Christos-Savvas Bouganis, Muhammad Abdullah Hanif, Faiq Khalid, Rehan Hafiz and Semeen Rehman
7.6.4 15:35–16:00	Inference of Quantized Neural Networks on Heterogeneous All‐Programmable Devices Thomas B. Preußer, Giulio Gambardella, Nicholas Fraser and Michaela Blott

Session Title	Rigorous design, analysis, and monitoring of dependable embedded systems
Session Code / Room	7.7 / Konf. 5
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Chair	Petru Eles, Linköping University, SE
Co-Chair	Akash Kumar, Technische Universität Dresden, DE

7.7.1 14:30–15:00	CHASE: Contract‐Based Requirement Engineering for Cyber‐Physical System Design Pierluigi Nuzzo, Michele Lora, Yishai A. Feldman and Alberto L. Sangiovanni-Vincentelli
7.7.2 15:00–15:30	Resilience Evaluation via Symbolic Fault Injection on Intermediate Code Hoang M. Le, Vladimir Herdt, Daniel Große and Rolf Drechsler
7.7.3 15:30–16:00	Online Analysis of Debug Trace Data for Embedded Systems Normann Decker, Boris Dreyer, Philip Gottschling, Christian Hochberger, Alexander Lange, Martin Leucker, Torben Scheffel, Simon Wegener and Alexander Weiss

Session Title	22FDX - the superior technology for IoT, RF, Automotive and Mobility: Advanced Design Methodologies for Ultra-low Power Solutions
Session Code / Room	7.8 / Exhibition Theatre
Date / Time	Wednesday, March 21, 2018 / 14:30 – 16:00
Organiser	Claudia Kretzschmar, GLOBALFOUNDRIES, DE

7.8.1 14:30–14:50	22FDX: A Technology Alternative to the Mainstream Optimized for IoT Applications Jürgen Faul
7.8.2 14:50–15:10	22FDX Design Methodology Enabling Optimized Power Performance and Area for IoT and Mobile AP Designs Ulrich Hensel
7.8.3 15:10–15:30	Adaptive Body Bias for A 0.4V Operable Mpsoc in 22Fdx as an Example for Big Data Handling Christian Mayr
7.8.4 15:30–16:00	QUENTIN: A Near-Threshold Soc for Energy-Efficient IoT End-Nodes in 22Nm FDX Technology Davide Rossi, Pasquale Davide Schiavone, Davide Rossi, Antonio Pullini, Francesco Conti, Frank K. Gurkaynak and Luca Benini

Session Title	Interactive Presentations
Session Code / Room	IP3 / Conference Floor
Date / Time	Wednesday, March 21, 2018 / 16:00 – 16:30

IP3-1	Testbench Qualification for SystemC‐AMS Timed Data Flow Models Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
IP3-2	An Algebra for Modeling Continuous Time Systems José E. G. de Medeiros, George Ungureanu and Ingo Sander
IP3-3	TTW: A Time‐Triggered Wireless Design for CPS Romain Jacob, Licong Zhang, Marco Zimmerling, Jan Beutel, Samarjit Chakraborty, and Lothar Thiele
IP3-4	PHYLAX: Snapshot-based Profiling of Real-Time Embedded Devices via JTAG Interface Charalambos Konstantinou, Eduardo Chielle and Michail Maniatakos
IP3-5	Characterizing Display QoS Based on Frame Dropping for Power Management of Interactive Applications on Smartphones Kuan-Ting Ho, Chung-Ta King, Bhaskar Das and Yung-Ju Chang
IP3-6	Prediction-Based Fast Thermoelectric Generator Reconfiguration for Energy Harvesting from Vehicle Radiators Hanchen Yang, Feiyang Kang, Caiwen Ding, Ji Li, Jaemin Kim, Donkyu Baek, Shahin Nazarian, Xue Lin, Paul Bogdan and Naehyuck Chang
IP3-7	A Parameterized Timing‐aware Flip‐flop Merging Algorithm for Clock Power Reduction Chaochao Feng, Daheng Yue, Zhenyu Zhao and Zhuofan Liao
IP3-8	Fast Chip‐Package‐PCB Coanalysis Methodology for Power Integrity of Multi‐Domain High‐Speed Memory: A Case Study Seungwon Kim, Ki Jin Han, Youngmin Kim and Seokhyeong Kang
IP3-9	Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis Saman Froehlich, Daniel Großeand Rolf Drechsler
IP3-10	Reconfigurable implementation of GF(2 m ) bit‐parallel multipliers José L. Imaña
IP3-11	Processing in 3D memories to speed up operations on complex data structures Paulo C. Santos, Geraldo F. Oliveira, João P. Lima, Marco A. Z. Alves, Luigi Carro and Antonio C. S. Beck
IP3-12	An Efficient NBTI‐Aware Wake‐Up Strategy for Power‐Gated Designs Kun‐Wei Chiu, Yu-Guang Chen and Ing‐Chao Lin
IP3-13	Designing Reliable Processor Cores in Ultimate CMOS and Beyond: a Double Sampling Solution Thierry Bonnoit, Fraidy Bouesse, Nacer‐Eddine Zergainoh and Michael Nicolaidis
IP3-14	Design of a Time‐predictable Multicore Processor: The T‐CREST Project Martin Schoeberl
IP3-15	Error Resilience Analysis for Systematically Employing Approximate Computing in Convolutional Neural Networks Muhammad Abdullah Hanif, Rehan Hafiz and Muhammad Shafique
IP3-16	DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA‐Based Systems Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar and Muhammad Shafique
IP3-17	Gain Scheduled Control for Nonlinear Power Management in CMPs Bryan Donyanavard, Amir M. Rahmani, Tiago Mück, Kasra Moazemmi and Nikil Dutt

Session Title	Special Day Session on Future and Emerging Technologies: NanoSystems: Connecting Devices, Architectures, and Applications
Session Code / Room	8.1 / Saal 2
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Sabry Aly Mohamed M., Nanyang Technological University, SG

8.1.1 17:00–17:30	3D Nanosystems: The Path To 1,000X Energy Efficiency Max Shulaker
8.1.2 17:30–18:00	Resistive Ram for New Computing Systems: From Deep Learning to Biomimicry Elisa Vianello
8.1.3 18:00–18:15	How Might New Technologies for Sensing Shape the Future of Computing Naveen Verma

Session Title	EU Projects: novel technologies, predictable architectures and worst-case execution times
Session Code / Room	8.2 / Konf. 6
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Paul Pop, Technical University of Denmark, De
Co-Chair	Petru Eles, Linköping University, SE

8.2.1 17:00–17:30	Using Polyhedral Techniques to Tighten WCET Estimates of Optimized Code: A Case Study with Array Contraction Thomas Lefeuvre, Imen Fassi, Christoph Cullmann, A. Gernot Gebhard, Emin Koray Kasnakli, Isabelle Puaut and Steven Derrien
8.2.2 17:30–18:00	Using Multifunctional Standardized Stack as Universal Spintronic Technology for IoT M. Tahoori, S.M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, A. Gamatie, P. Nouet, F. Ouattara, G. Sassatelli, K. Jabeur, P. Vanhauwaert 3, A. Atitoaie, I.Firastrau, G. Di Pendina and G. Prenat
8.2.3 18:00–18:15	Progress on Carbon Nanotube BEOL Interconnects B. Uhlig, J. Liang 8, J. Lee, R. Ramos, A. Dhavamani, N. Nagy, J. Dijon, H. Okuno, D. Kalita, V. Georgiev, A. Asenov, S. Amoroso, L. Wang, C. Millar, F. Konemann, B. Gotsmann, G. Goncalves, B. Chen, R. R. Pandey, R. Chen and A. Todri‐Sanial
8.2.4 18:15–18:30	A WCET‐Aware Parallel Programming Model for Predictability Enhanced Multi‐core Architectures Simon Reder, Leonard Masing, Harald Bucher, Timon ter Braak, Timo Stripf and Jürgen Becker

Session Title	Real time intelligent methods for energy-efficient approaches in CNN and biomedical applications
Session Code / Room	8.3 / Konf. 1
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Theo Theocharis Theocharides, University of Cyprus, CY
Co-Chair	Jose L. Ayala, Dpto Arquitectura de Computadores - UCM, ES

8.3.1 17:00–17:30	Online Efficient Bio‐Medical Video Transcoding on MPSoCs Through Content‐Aware Workload Allocation Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Žagar, Mario Kovač and David Atienza
8.3.2 17:30–18:00	Highly Efficient and Accurate Seizure Prediction on Constrained IoT Devices Farzad Samie, Sebastian Paul, Lars Bauer and Jörg Henkel
8.3.3 18:00–18:15	A Wearable Long‐Term Single‐Lead ECG Processor for Early Detection of Cardiac Arrhythmia Syed Muhammad Abubakar, Wala Saadeh and Muhammad Awais Bin Altaf
8.3.4 18:15–18:30	DroNet: Efficient Convolutional Neural Network Detector for Real‐Time UAV Applications Christos Kyrkou, George Plastiras, Theocharis Theocharides, Stylianos I. Venieris and Christos-Savvas Bouganis

Session Title	Efficient and reliable memory and computing architectures
Session Code / Room	8.4 / Konf. 2
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Göhringer Diana, Technische Universität Dresden, DE
Co-Chair	Jie Han, University of Alberta, CA

8.4.1 17:00–17:30	HyVE: Hybrid Vertex‐Edge Memory Hierarchy for Energy‐Efficient Graph Processing Tianhao Huang, Guohao Dai, Yu Wang c and Huazhong Yang
8.4.2 17:30–18:00	Accurate Neuron Resilience Prediction for a Flexible Reliability Management in Neural Network Accelerators Christoph Schorn, Andre Guntoro and Gerd Ascheid
8.4.3 18:00–18:15	Rapid In-Memory Matrix Multiplication Using Associative Processor Mohamed Ayoub Neggaz, Hasan Erdem Yantir, Smail Niar, Ahmed Eltawil and Fadi Kurdahi
8.4.4 18:15–18:30	HiMap: A Hierarchical Mapping Approach for Enhancing Lifetime Reliability of Dark Silicon Manycore Systems Vijeta Rathore, Vivek Chaturvedi, Amit K. Singh, Thambipillai Srikanthan, Rohith R, Siew-Kei Lam and Muhammad Shafique

Session Title	From NBTI to IoT security: industrial experiences
Session Code / Room	8.5 / Konf. 3
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Doris Keitel-Schulz, Infineon Technologies, DE
Co-Chair	Norbert Wehn, University of Kaiserslautern, DE

8.5.1 17:00–17:15	NBTI Aged Cell Rejuvenation with Back Biasing And Resulting Critical Path Reordering for Digital Circuits in 28nm FDSOI Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho and Lorena Anghel
8.5.2 17:15–17:30	An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo and Zaid Al‐Ars
8.5.3 17:30–17:45	A Case Study for Using Dynamic Partitioning Based Solution in Volume Diagnosis Tao Wang, Zhangchun Shi, Junlin Huang, Huaxing Tang, Wu Yang and Junna Zhong
8.5.4 17:45–18:00	On‐line RF Built‐In Self‐Test using Noise Injection and Transmitter Signal Modulation by Phase Shifter Jan Schat
8.5.5 18:00–18:15	Neural Networks for Safety‐Critical Applications ‐ Challenges, Experiments and Perspectives Chih‐Hong Cheng, Frederik Diehl, Gereon Hinz, Yassine Hamza, Georg Nuehrenberg, Markus Rickert, Harald Ruess and Michael Truong‐Le
8.5.6 18:15–18:30	IoT Security Assessment through the Interfaces P‐SCAN Test Bench Platform Thomas Maurin, Laurent‐Frédéric Ducreux, George Caraiman and Philippe SISSOKO

Session Title	Designing reliable embedded architectures under uncertainty
Session Code / Room	8.6 / Konf. 4
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Chair	Oliver Bringmann, Universität Tübingen, DE
Co-Chair	Amit Singh, University of Essex, GB

8.6.1 17:00–17:30	Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation Simon Rokicki, Erven Rohouand and Steven Derrien
8.6.2 17:30–18:00	uSFI: Ultra‐Lightweight Software Fault Isolation for IoT‐Class Devices Zelalem Birhanu Aweke and Todd Austin
8.6.3 18:00–18:15	Converging Safety and High‐performance Domains: Integrating OpenMP into Ada Sara Royuela, Luis Miguel Pinho and Eduardo Quiñones
8.6.4 18:15–18:30	Compiler‐Driven Error Analysis for Designing Approximate Accelerators Jorge Castro‐Godínez, Sven Esser, Muhammad Shafique, Santiago Pagani and Jörg Henkel

Session Title	22FDX - the superior technology for IoT, RF, Automotive and Mobility: Best-in Class RF, 5G and mmWave designs
Session Code / Room	8.8 / Exhibition Theatre
Date / Time	Wednesday, March 21, 2018 / 17:00 – 18:30
Organiser	Claudia Kretzschmar, GLOBALFOUNDRIES, DE

8.8.1 17:00–17:20	Best-In Class RF Integrated Circuits for Multi-Gbps Communication in 22Fdx Corrado Carta
8.8.2 17:20–17:40	Smart Data Converters for Wireline and Wireless Systems Using 22Fdx Friedel Gerfers
8.8.3 17:40–18:00	N-Path Filters and Mixers Controllable by a Digital Multi-Phase Clock Eric Klumperink
8.8.4 18:00–18:30	MM-Wave Circuit Design Using Globalfoundries 22Fdx Aarno Pärssinen, Janne P. Aikio, Mikko Hietanen, Henri Hurskainen and Timo Rahkonen

Session Title	Special Day Session on Designing Autonomous Systems: Embedded Machine Learning
Session Code / Room	9.1 / Saal 2
Date / Time	Thursday, March 22, 2018 / 08:30 – 10:00
Chair	Jerraya Ahmed, CEA, FR

9.1.2 09:00–09:30	Overview of the State of the Art in Embedded Machine Learning Liliana Andrade, Adrien Prost‐Boucle and Frédéric Pétrot
9.1.3 09:30–10:00	PNeuro: a scalable energy‐efficient programmable hardware accelerator for neural networks A. Carbon, J.‐M. Philippe, O. Bichler, R. Schmit, B. Tain, D. Briand, N. Ventroux, M. Paindavoine and O. Brousse

Session Title	Emerging architectures and technologies for ultra low power and efficient embedded systems
Session Code / Room	9.2 / Konf. 6
Date / Time	Thursday, March 22, 2018 / 08:30 – 10:00
Chair	Johanna Sepulveda, Technical University of Munich, DE
Co-Chair	Amato Paolo, Micron Technology, IT

9.2.1 08:30–09:00	FFT‐Based Deep Learning Deployment in Embedded Systems Sheng Lin, Ning Liu, Mahdi Nazemi, Hongjia Li, Caiwen Ding, Yanzhi Wang and Massoud Pedram
9.2.2 09:00–09:30	A Transprecision Floating‐Point Platform for Ultra‐Low Power Computing Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu and Luca Benini
9.2.3 09:30–09:45	A Peripheral Circuit Reuse Structure Integrated with a Retimed Data Flow for Low Power RRAM Crossbar‐based CNN Keni Qiu, Weiwen Chen, Yuanchao Xu, Lixue Xia, Yu Wang and Zili Shao
9.2.4 09:45–10:00	Optimal DC/AC Data Bus Inversion Coding Jan Lucas, Sohan Laland Ben Juurlink

Session Title	Advances in Reconfigurable Computing
Session Code / Room	9.3 /Konf. 1
Date / Time	Thursday, March 22, 2018 / 08:30 – 10:00
Chair	Jürgen Teich, Friedrich-Alexander Universität, DE
Co-Chair	Florent de Dinechin, INSA-Lyon, FR

9.3.1 08:30–09:00	LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava and Reiley Jeyapaul
9.3.2 09:00–09:30	A Time‐Multiplexed FPGA Overlay with Linear Interconnect Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell and Suhaib A. Fahmy
9.3.3 09:30–09:45	URECA: A Compiler Solution to Manage Unified Register File for CGRAs Shail Dave, Mahesh Balasubramanianand Aviral Shrivastava
9.3.4 09:45–10:00	Optimizing the data placement and transformation for multi‐bank CGRA computing system Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang and Zhigang Mao

Session Title	EU and transatlantic projects: novel platforms--from self-aware MPSoCs to server ecosystems
Session Code / Room	9.4 /Konf. 2
Date / Time	Thursday, March 22, 2018 / 08:30 – 10:00
Chair	Flavius Gruian, Lund University, SE
Co-Chair	Martin Schoeberl, Technical University of Denmark, De

9.4.1 08:30–09:00	dReDBox: Materializing a Full‐stack Rack‐scale System Prototype of a Next‐Generation Disaggregated Datacenter M. Bielski, I. Syrigos, K. Katrinis, D. Syrivelis, A. Reale, D. Theodoropoulos, N. Alachiotis, D. Pnevmatikatos, E.H. Pap, G. Zervas, V. Mishra, A. Saljoghei,A. Rigo, J. Fernando Zazo, S. Lopez‐Buedo, M. Torrents, F. Zyulkyarov, M. Enrico and O. Gonzalez de Dios
9.4.2 09:00–09:30	An Energy‐Efficient and Error‐Resilient Server Ecosystem Exceeding Conservative Scaling Limits Georgios Karakonstantis, Panos Koutsovasilis, Srikumar Venugopal, Andreas Diavastos and George Papadimitriou
9.4.3 09:30–10:00	The Transprecision Computing Paradigm: Concept, Design, and Applications A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni,Giuseppe Tagliavini, Andrew Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand and Norbert Wehn

Session	Physical Attacks
Session Code / Room	9.5/ Konf. 3
Date / Time	Thursday, March 22, 2018 / 08:30 - 10:00
Chair	Bilge Kavun Elif, Infineon Technologies, DE
Co-Chair	Batina Lejla, Radboud University, NL

9.5.1 08:30–09:00	An Inside Job: Remote Power Analysis Attacks on FPGAs Falk Schellenberg, Dennis R.E. Gnad, Amir Moradi and Mehdi B. Tahoori
9.5.2 09:00–09:30	Confident Leakage Assessment ‐ A Side‐Channel Evaluation Framework based on Confidence Intervals Florian Bache, Christina Plump and Tim Güneysu
9.5.3 09:30–09:45	Øzone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures Zelalem Birhanu Aweke and Todd Austin
9.5.4 09:45–10:00	SCADPA: Side‐Channel Assisted Differential‐Plaintext Attack on Bit Permutation Based Ciphers Jakub Breier, Dirmanto Jap and Shivam Bhasin

Session Title	Interactive Presentations
Session Code / Room	IP4 /Conference Floor
Date / Time	Thursday, March 22, 2018 / 10:00 – 10:30

IP4-1	Efficient Mapping of Quantum Circuits to the IBM QX Architectures Alwin Zulehner, Alexandru Paler and Robert Wille
IP4-2	Parallel Code Generation of Synchronous Programs for a Many‐core Architecture Amaury Graillat, Matthieu Moy, Pascal Raymond and Benoît Dupont de Dinechin
IP4-3	SOCRATES ‐ A Seamless Online Compiler and System Runtime AutoTuning Framework for Energy-Aware Applications Davide Gadioli, Ricardo Nobre, Pedro Pinto, Emanuele Vitali, Amir H. Ashouri, Gianluca Palermo, Joao Cardoso and Cristina Silvano
IP4-4	Non-Intrusive Program Tracing of Non-Preemptive Multitasking Systems Using Power Consumption Kamal Lamichhane, Carlos Moreno and Sebastian Fischmeister
IP4-5	Energy‐Performance Design Exploration of a Low‐Power Microprogrammed Deep‐Learning Accelerator Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera and Massimo Alioto
IP4-6	GenPIM: Generalized Processing In‐Memory to Accelerate Data Intensive Applications Mohsen Imani, Saransh Gupta and Tajana Rosing
IP4-7	Universal Number Posit Arithmetic Generator on FPGA Manish Kumar Jaiswal and Hayden K.-H So
IP4-8	Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA Gang Li, Fanrong Li, Tianli Zhao and Jian Cheng
IP4-9	Examining the Consequences of High‐Level Synthesis Optimizations on Power Side‐Channel Lu Zhang, Wei Hu, Armaiti Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu and Ryan Kastner
IP4-10	DFARPA: Differential Fault Attack Resistant Physical Design Automation Mustafa Khairallah, Rajat Sadhukhan, Radhamanjari Samanta, Jakub Breier, Shivam Bhasin, Rajat Subhra Chakraborty, Anupam Chattopadhyay and Debdeep Mukhopadhyay
IP4-11	An Energy-Efficient Stochastic Computational Deep Belief Network Yidong Liu,Yanzhi Wang, Fabrizio Lombardi and Jie Han
IP4-12	Pushing the Number of Qubits Below the "Minimum": Realizing Compact Boolean Components for Quantum Logic Alwin Zulehner and Robert Wille
IP4-13	Power Optimization Through Peripheral Circuit Reusing Integrated with Loop Tiling for RRAM Crossbar‐based CNN Yuanhui Ni, Weiwen Chen, Wenjuan Cui, Yuanchun Zhou and Keni Qiu
IP4-14	ORIENT: Organized Interleaved ECCs for New STT‐MRAM Caches Zahra Azad, Hamed Farbeh and Amir Mahdi Hosseini Monazzah
IP4-15	ERASMUS: Efficient Remote Attestation via Self‐Measurement for Unattended Settings Xavier Carpent, Norrathep Rattanavipanon and Gene Tsudik
IP4-16	End‐to‐end Latency Analysis of Cause-effect Chains in an Engine Management System Junchul Choi, Donghyun Kang and Soonhoi Ha
IP4-17	General Floorplanning Methodology for 3D ICs with An Arbitrary Bonding Style Jai-Ming Lin and Chien-Yu Huang

Session Title	Special Day Session on Designing Autonomous Systems: Digitalization in automotive and industrial systems
Session Code / Room	10.1 / Saal 2
Date / Time	Thursday, March 22, 2018 / 11:00 – 12:30
Chair	Traub Matthias, BMW, Ge

10.1.0

Digitalization in automotive and industrial systems
Matthias Traub, Hans‐Jörg Vögel, Eric Sax, Thilo Streichert and Jérôme Härri

Session Title	Neural Networks and Neurotechnology
Session Code / Room	10.2 / Konf. 6
Date / Time	Thursday, March 22, 2018 / 11:00 – 12:30
Chair	Jim Harkin, University of Ulster, GB
Co-Chair	Robert Wille, University of Linz, AT

10.2.1 11:00–11:30	Design and Optimization of FeFET‐based Crossbars for Binary Convolution Neural Networks Xiaoming Chen, Xunzhao Yin, Michael Niemier and Xiaobo Sharon Hu
10.2.2 11:30–12:00	Low‐Power 3D Integration using Inductive Coupling Links for Neurotechnology Applications Benjamin J. Fletcher, Shidhartha Das, Chi‐Sang Poon and Terrence Mak
10.2.3 12:00–12:15	Mapping of Local and Global Synapses on Spiking Neuromorphic Hardware Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Francky Catthoor and Siebren Schaafsma
10.2.4 12:15–12:30	Energy-Efficient Neural Networks using Approximate Computation Reuse Xun Jiao, Vahideh Akhlaghi, Yu Jiang and Rajesh K. Gupta

Session Title	From Non-Volatile Flip-Flops to Storage Systems
Session Code / Room	10.3 / Konf. 1
Date / Time	Thursday, March 22, 2018 / 11:00 – 12:30
Chair	Stefan Slesazeck, NaMLab gGmbH, DE
Co-Chair	Weisheng Zhao, Beihang University, CN

10.3.1 11:00–11:30	Multi‐Bit Non‐Volatile Spintronic Flip‐Flop Christopher Münch, Rajendra Bishnoi and Mehdi B. Tahoori
10.3.2 11:30–12:00	ADAM: Architecture for Write DisturbAnce Mitigation in Scaled Phase Change Memory Shivam Swami and Kartik Mohanram
10.3.3 12:00–12:15	Program Error Rate-based Wear Leveling for NAND Flash Memory Xin Shi, Fei Wu, Shunzhuo Wang, Changsheng Xie and Zhonghai Lu
10.3.4 12:15–12:30	ShadowGC: Cooperative Garbage Collection with Multi-level Buffer for Performance Improvement in NAND flash-based SSDs Jinhua Cui, Youtao Zhang, Jianhang Huang, Weiguo Wu and Jun Yang

Session Title	Cryptographic Hardware
Session Code / Room	10.4 / Konf. 2
Date / Time	Thursday, March 22, 2018 / 11:00 – 12:30
Chair	Nele Mentens, Katholieke Universiteit Leuven, BE
Co-Chair	Tim Güneysu, Ruhr-Universität Bochum, DE

10.4.1 11:00–11:30	Binary Ring-LWE Hardware with Power Side-Channel Countermeasures Aydin Aysu, Michael Orshansky and Mohit Tiwari
10.4.2 11:30–12:00	High Speed ASIC Implementations of Leakage‐Resilient Cryptography Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gurkaynak, Michael Muehlberghuber and Luca Benini
10.4.3 12:00–12:30	Optimization of the PLL Configuration in a PLL‐based TRNG Design Elie Noumon Allini, Oto Petura, Viktor Fischer and Florent Bernard

Session Title	Mixed-Criticality and Fault-Tolerant Real-Time Embedded Systems
Session Code / Room	10.5 /Konf. 3
Date / Time	Thursday, March 22, 2018/ 11:00 – 12:30
Chair	Leandro Indrusiak, Univ. of York, GB
Co-Chair	Andy Pimentel, University of Amsterdam, DE

10.5.1 11:00–11:30	Availability Enhancement and Analysis for Mixed-Criticality Systems on Multi-core Roberto Medina, Etienne Borde and Laurent Pautet
10.5.2 11:30–12:00	Mixed‐criticality Scheduling with Memory Bandwidth Regulation Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson and Eduardo Tovar
10.5.3 12:00–12:30	Design and Validation of Fault‐tolerant Embedded Controllers Saurav Kumar Ghosh, Soumyajjit Dey, Dip Goswami, Daniel Mueller‐Gritschneder and Samarjit Chakraborty

Session Title	Special Session: Computing with Ferroelectric FETs - Devices, Models, Systems, and Applications
Session Code / Room	10.6 / Konf. 4
Date / Time	Thursday, March 22, 2018 / 11:00 – 12:30
Chair	Niemier Michael, University of Notre Dame, US
Co-Chair	O'Connor Ian, Ecole Centrale de Lyon, FR

10.6.0

Computing with Ferroelectric FETs: Devices, Models, Systems, and Applications
Ahmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni, Michael Niemier, Ian O’Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala and Xunzhao Yin

Session Title	Lunch Time Keynote Session: Autonomous driving : ready to market? Which are the remaining top challenges?
Session Code / Room	11.0 / Saal 2
Date / Time	Thursday, March 22, 2018 / 13:20 – 13:50
Chair	Ayse Coskun, Boston University, US

11.0.1
13:20 – 13:50

Keynote Address 4: Autonomous driving : ready to market? Which are the remaining top challenges?
Thomas Form

Session Title	Special Day Session on Designing Autonomous Systems: Smart Vision Systems
Session Code / Room	11.1 / Saal 2
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Rinner Bernhard, Alpen-Adria-Universität Klagenfurt, Au

11.1.1 14:00–14:18	The CAMEL Approach to Stacked Sensor Smart Cameras Saibal Mukhopodhyay, Marilyn Wolf, Mohammed F. Amir, Evan Gebahrdt, Jong Hwan Ko, Jae Ha Kung and Burhan A. Musassar
11.1.2 14:18–14:36	A Design Tool for High Performance Image Processing on Multicore Platforms Jiahao Wu, Timothy Blattner, Walid Keyrouz and Shuvra S. Bhattacharyya
11.1.3 14:36–14:54	Quasar, a High‐level Programming Language and Development Environment for Designing Smart Vision Systems on Embedded Platforms Bart Goossens, Hiêp Luong, Jan Aelterman and Wilfried Philips
11.1.4 14:54–16:12	Concurrent focal‐plane generation of compressed samples from time‐encoded pixel values M. Trevisi, H. C. Bandala, J. Fernández‐Berni, R. Carmona‐Galán and Á. Rodríguez‐Vázquez
11.1.5 16:12–15:30	Contactless Finger and Face Capturing on a Secure Handheld Embedded Device Axel Weissenfeld, Bernhard Strobland Franz Daubner

Session Title	Timing and Power Driven Physical Design
Session Code / Room	11.2 / Konf. 6
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Miguel Silveira, INESC-ID/IST, PT
Co-Chair	Patrick Groeneveld, Cadence Design Systems, US

11.2.1 14:00–14:30	A Faithful Binary Circuit Model with Adversarial Noise Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak and Ulrich Schmid
11.2.2 14:30–15:00	EVT‐based Worst Case Delay Estimation Under Process Variation Charalampos Antoniadis, Dimitrios Garyfallou, Nestor Evmorfopoulos and Georgios Stamoulis
11.2.3 15:00–15:15	Co‐Synthesis of Floorplanning and Powerplanning in 3D ICs for Multiple Supply Voltage Designs Jai‐Ming Lin, Chien‐Yu Huang and Jhih‐Ying Yang
11.2.4 15:15–15:30	Accelerate Analytical Placement with GPU: A Generic Approach Chun‐Xun Lin and Martin D. F. Wong

Session Title	More than Moore Interconnects
Session Code / Room	11.3 / Konf. 1
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Sébastien Le Beux, Ecole Centrale de Lyon - University of Lyon, FR
Co-Chair	Davide Zoni, Politecnico di Milano, IT

11.3.1 14:00–14:30	High Performance Collective Communication‐Aware 3D Network‐on‐Chip Architectures Biresh Kumar Joardar, Karthi Duraisamy and Partha Pratim Pande
11.3.2 14:30–15:00	A Soft‐Error Resilient Route Computation Unit for 3D Networks‐on‐Chips Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan Fraire and Raoul Velazco
11.3.3 15:00–15:15	SPA: Simple Pool Architecture for application resource allocation in many‐core systems Jayasimha Sai Koduri and Iraklis Anagnostopoulos
11.3.4 15:15–15:30	RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-Scale Computing Systems Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong and Jiang Xu

Session Title	Evaluating and optimizing memory and timing across HW and SW boundaries
Session Code / Room	11.4 / Konf. 2
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Sara Vinco, Politecnico di Torino, IT
Co-Chair	Todd Austin, University of Michigan, US

11.4.1 14:00–14:30	HME: A Lightweight Emulator for Hybrid Memory Zhuohui Duan, Haikun Liu, Xiaofei Liao and Hai J
11.4.2 14:30–15:00	VerC3: A Library for Explicit State Synthesis of Concurrent Systems Marco Elver, Christopher J. Banks, Paul Jackson and Vijay Nagarajan
11.4.3 15:00–15:15	Prometheus: Processing‐in‐memory Heterogeneous Architecture Design From a Multi‐layer Network Theoretic Strategy Yao Xiao, Shahin Nazarian and Paul Bogdan
11.4.4 15:15–15:30	Advancing Source‐Level Timing Simulation using Loop Acceleration Joscha Benz, Christoph Gerumand and Oliver Bringmann

Session Title	Microfluidic Devices and Inexact Computing
Session Code / Room	11.5 / Konf. 3
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Trefzer Martin, University of York, GB
Co-Chair	Lukas Sekanina, University of Brno, CZ

11.5.1 14:00–14:30	Storage-Aware Sample Preparation Using Flow-Based Microfluidic Labs-on-Chip Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang and Bhargab B. Bhattacharya
11.5.2 14:30–15:00	Pump‐Aware Flow Routing Algorithm for Programmable Microfluidic Devices Guan‐Ru Lai, Chun‐Yu Lin and Tsung‐Yi Ho
11.5.3 15:00–15:15	Adaptive Approximation in Arithmetic Circuits: A Low‐Power Unsigned Divider Design Honglan Jiang, Leibo Liu, Fabrizio Lombardi and Jie Han
11.5.4 15:15–15:30	Correlation Manipulating Circuits for Stochastic Computing Vincent T. Lee, Armin Alaghi and Luis Ceze

Session Title	Memory: new technologies and reliability-related issues
Session Code / Room	11.6 / Konf. 4
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Carles Hernandez, Barcelona Supercomputing Center (BSC), ES
Co-Chair	Shahar Kvatinsky, Technion, IL

11.6.1 14:00–14:30	XNOR‐RRAM: A Scalable and Parallel Resistive Synaptic Architecture for Binary Neural Networks Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo and Shimeng Yu
11.6.2 14:30–15:00	A Novel Fault Tolerant Cache Architecture Based on Orthogonal Latin Squares Theory Filippos Filippou, Georgios Keramidas, Michail Mavropoulos and Dimitris Nikolos
11.6.3 15:00–15:15	Technology-Aware Logic Synthesis for ReRAM based In-Memory Computing Debjyoti Bhattacharjee, Luca Amaŕu and Anupam Chattopadhyay
11.6.4 15:15–15:30	SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality Seyedeh Golsana Ghaemi, Iman Ahmadpour, Mehdi Ardebili and Hamed Farbeh

Session Title	Building Resistant Systems: From Temperature Awareness to Attack Resistance
Session Code / Room	11.7 / Konf. 5
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Chair	Marina Zapater, EPFL, CH
Co-Chair	Georg Georg Becker, ESMT Berlin, DE

11.7.1 14:00–14:30	Leveraging Thermally-Aware Chiplet Organization in 2.5D Systems to Reclaim Dark Silicon Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful Mojumder and Tiansheng Zhang
11.7.2 14:30–15:00	Ising‐PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter‐PUFs Hiromitsu Awano and Takashi Sato
11.7.3 15:00–15:15	Efficient Helper Data Reduction in SRAM PUFs via Lossy Compression Ye Wang and Michael Orshansky
11.7.4 15:15–15:30	Improving the Efficiency of Thermal Covert Channels in Multi-/many-core Systems Zijun Long, Xiaohang Wang, Yingtao Jiang, Guofeng Cui, Li Zhang and Terrence Mak

Session Title	A Powerful Framework for Functional Safety
Session Code / Room	11.8 / Exhibition Theatre
Date / Time	Thursday, March 22, 2018 / 14:00 – 15:30
Organiser	Astrid Ernst, Mentor, DE

11.8.1 14:00–14:10	Introduction Astrid Ernst
11.8.2 14:10–14:50	IC Verification: How Formal Reduces Fault Analysis for ISO 26262 Dirk Hansen
11.8.3 14:50–15:30	DFT Part: Tessent Mission Mode: New, On-Line Self-Testing Technology Paves Way for Self-Correcting Automotive Electronic Architectures Ralph Sommer

Session Title	Interactive Presentations
Session Code / Room	IP5 /Conference Floor
Date / Time	Thursday, March 22, 2018 / 15:30 – 16:00

IP5-1	A Placement Algorithm for Superconducting Logic Circuits Based on Cell Grouping and Super‐Cell Placement Soheil Nazar Shahsavani, Alireza Shafaei and Massoud Pedram
IP5-2	Abax: 2D/3D Legaliser Supporting Look‐Ahead Legalisation and Blockage Strategies Nikolaos Sketopoulos, Christos Sotiriou and Stavros Simoglou
IP5-3	LESAR: A Dynamic Line‐End Spacing Aware Detailed Router Ying‐Chi Wei, Radhamanjari Samanta and Yih‐Lang Li
IP5-4	Understanding Turn Models for Adaptive Routing: the Modular Approach Edoardo Fusella and Alessandro Cilardo
IP5-5	Quater‐Imaginary Base for Complex Number Arithmetic Circuits Souradip Sarkar and Manil Dev Gomony
IP5-6	Fault‐Tolerant Valve‐Based Microfluidic Routing Fabric for Droplet Barcoding in Single‐Cell Analysis Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty and Ulf Schlichtmann
IP5-7	Optimizing Power-Accuracy trade-off in Approximate Adders Celia D, Vinita Vasudevan and Nitin Chandrachoodan
IP5-8	Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn and Matthias Jung
IP5-9	Architecture and Optimization of Associative Memories used for the Implementation of Logic Functions based on Nanoelectronic 1S1R Cells Arne Heittmann and Tobias G. Noll
IP5-10	Accurate Prediction of Smartphones’ Skin Temperature by Considering Exothermic Components Jihoon Park, Seokjun Lee and Hojung Cha
IP5-11	Trustworthy Proofs for Sensor Data using FPGA based Physically Unclonable Functions Urbi Chatterjee, Durga Prasad Sahoo, Debdeep Mukhopadhyay and Rajat Subhra Chakraborty
IP5-12	Towards Fully Automated TLM‐to‐RTL Property Refinement⋆ Vladimir Herdt, Hoang M. Le, Daniel Große and Rolf Drechsler
IP5-13	In‐Memory Computing Using Paths‐Based Logic and Heterogeneous Components Alvaro Velasquez and Sumit Kumar Jha
IP5-14	Non‐Intrusive Testing Technique for Detection of Trojans in Asynchronous Circuits Leonel Acunha Guimarães, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos and Laurent Fesquet
IP5-15	Towards Inter‐Vendor Compatibility of True Random Number Generators for FPGAs Miloš Grujić, Bohan Yang, Vladimir Rožić and Ingrid Verbauwhede
IP5-16	Efficient Wear Leveling for Inodes of File Systems on Persistent Memories Xianzhang Chen, Edwin H.-M. Sha, Yuansong Zeng, Chaoshu Yang, Weiwen Jiang and Qingfeng Zhuge
IP5-17	Exploring Non‐Volatile Main Memory Architectures for Handheld Devices Sneha Ved and Manu Awasthi

Session Title	Special Day Session on Designing Autonomous Systems: Self-awareness for Autonomous Systems
Session Code / Room	12.1 / Saal 2
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Dutt Nikil, University of California at Irving, US

12.1.3
17:00–17:30

Design Methodologies for Enabling Self‐awareness in Autonomous Systems
Armin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mück, Ahmed Nas, Amir M. Rahmani, Thomas Wild, Nikil Dutt, Rolf Ernst, Andreas Herkersdorf and Fadi Kurdahi

Session Title	Searching for corner cases, bugs and security vulnerabilities
Session Code / Room	12.2 / Konf. 6
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Daniel Grosse, University of Bremen / DFKI, DE
Co-Chair	Jaan Raik, Tallinn University of Technology, Es

12.2.1 16:00–16:30	Directed Test Generation using Concolic Testing on RTL models Alif Ahmed, Farimah Farahmandi and Prabhat Mishra
12.2.2 16:30–17:00	Suspect Set Prediction in RTL Bug Hunting Neil Veira, Zissis Poulos and Andreas Veneris
12.2.3 17:00–17:30	Symbolic assertion mining for security validation Alessandro Danese, Valeria Bertacco and Graziano Pravadelli

Session Title	Verification and Formal Synthesis
Session Code / Room	12.3 / Konf. 1
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Christoph Scholl, Albert-Ludwigs-Universität Freiburg, DE
Co-Chair	Gianpiero Cabodi, Politecnico di Torino, IT

12.3.1 16:00–16:30	Improving and Extending the Algebraic Approach for Verifying Gate‐Level Multipliers Daniela Ritirc, Armin Biere and Manuel Kauers
12.3.2 16:30–17:00	Reconfigurable Asynchronous Pipelines: from Formal Models to Silicon Danil Sokolov, Alessandro de Gennaro and Andrey Mokhov
12.3.3 17:00–17:15	Automatic Generation of Hardware Checkers from Formal Micro‐architectural Specifications Alexander Fedotov and Julien Schmaltz
12.3.4 17:15–17:30	Specification Decomposition for Synthesis from Libraries of LTL Assume/Guarantee Contracts Antonio Iannopollo, Stavros Tripakis and Alberto Sangiovanni-Vincentelli

Session Title	Hardware-assisted Security
Session Code / Room	12.4 / Konf. 2
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Ilia Polian, University of Stuttgart, DE
Co-Chair	Nele Mentens, Katholieke Universiteit Leuven, Be

12.4.1 16:00–16:30	Hardware-Assisted Rootkit Detection via On-line Statistical Fingerprinting of Process Execution Liwei Zhou and Yiorgos Makris
12.4.2 16:30–17:00	Securing Conditional Branches in the Presence of Fault Attacks Robert Schilling, Mario Werner and Stefan Mangard
12.4.3 17:00–17:15	Towards Provably‐Secure Performance Locking Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris and Jeyavijayan (JV) Rajendran
12.4.4 17:15–17:30	An Automated Configurable Trojan Insertion Framework for Dynamic Trust Benchmarks Jonathan Cruz, Yuanwen Huang, Prabhat Mishra and Swarup Bhunia

Session Title	Lifetime Improvement for Persistent Memory
Session Code / Room	12.5 / Konf. 3
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Arne Heittman, RWTH, DE
Co-Chair	Chengmo Yang, University of Delaware, US

12.5.1 16:00–16:30	Extending the Lifetime of NVMs with Compression Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu and Chunyan Li
12.5.2 16:30–17:00	Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement Taehyun Kwon, Muhammad Imran, Jung Min You and Joon-Sung Yang
12.5.3 17:00–17:15	An Efficient PCM‐based Main Memory System via Exploiting Fine‐grained Dirtiness of Cachelines Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li and Zheng Li
12.5.4 17:15–17:30	DFPC: A Dynamic Frequent Pattern Compression Scheme in NVM-based Main Memory Yuncheng Guo, Yu Hua and Pengfei Zuo

Session Title	Special Session: Computing with Emerging Memories; How good can it be?
Session Code / Room	12.6 / Konf. 4
Date / Time	Thursday, March 22, 2018 / 16:00 – 17:30
Chair	Gaillardon Pierre-Emmanuel, University of Utah, US
Co-Chair	O'Connor Ian, Ecole Centrale de Lyon, FR

12.6.1 16:00–16:15	Practical Challenges in Delivering the Promises of Real Processing‐in‐Memory Machines Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre‐Emmanuel Gaillardon and Shahar Kvatinsky
12.6.2 16:15–16:40	Smart Instruction Codes for In‐Memory Computing Architectures Compatible with Standard SRAM Interfaces Maha Kooli, Henri‐Pierre Charles, Clement Touzet, Bastien Giraud and Jean‐Philippe Noel
12.6.3 16:40–17:05	Computing‐in‐Memory with Spintronics Shubham Jain, Sachin Sapatnekar, Jian‐Ping Wang, Kaushik Roy and Anand Raghunathan
12.6.4 17:05–17:30	Memristive Devices for Computation‐In‐Memory Jintao Yu, Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil and Said Hamdioui