Design of a Time‐predictable Multicore Processor: The T‐CREST Project
Martin Schoeberl
Department of Applied Mathematics and Computer Science Technical University of Denmark
masca@dtu.dk
ABSTRACT
Real‐time systems need to deliver results in time and often this timely production of a result needs to be guaranteed. Static timing analysis can be used to bound the worst‐case execution time of tasks. However, this timing analysis is only possible if the processor architecture is analysis friendly. This paper presents the T‐CREST processor, a real‐time multicore processor developed to be time‐predictable and an easy target for static worst‐case execution time analysis. We present how to achieve time‐predictability at all levels of the architecture, from the processor pipeline, via a network‐on‐chip, up to the memory controller. The main architectural feature to provide time predictability is to use static arbitration of shared resources in a time‐division multiplexing way.
