Fast Chip‐Package‐PCB Coanalysis Methodology for Power Integrity of Multi‐Domain High‐Speed Memory: A Case Study
Seungwon Kim1, Ki Jin Han2, Youngmin Kim3 and Seokhyeong Kang1,a
1Department of Electrical Engineering, Ulsan National Institute of Science and Technology
ashkang@unist.ac.kr
2Division of Electronics and Electrical Engineering, Dongguk University
3School of Computer and Information Engineering, Kwangwoon University
ABSTRACT
The power integrity of high‐speed interfaces is an increasingly important issue in mobile memory systems. However, because of complicated design variations such as adjacent VDD domain coupling, conventional case‐specific modeling is limited in analyzing trends in results from parametric variations. Moreover, conventional industrial methods can be simulated only after the design layout is completed and it requires a lot of back‐annotation processes, which result in delayed delays time to market. In this paper, we propose a chip‐package‐PCB coanalysis methodology applied to our multi‐domain high‐speed memory system model with a current generation method. Our proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPPDR4 environment.
