An Efficient PCM‐based Main Memory System via Exploiting Fine‐grained Dirtiness of Cachelines
Jie Xua, Dan Fengb, Yu Huac, Wei Tongd, Jingning Liue, Chunyan Lif and Zheng Lig
Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System
(School of Computer Science and Technology, Huazhong University of Science and Technology)
Ministry of Education of China
axujie_dsal@hust.edu.cn
bdfeng@hust.edu.cn
ccsyhua@hust.edu.cn
dTongwei@hust.edu.cn
ejnliu@hust.edu.cn
flichunyan@hust.edu.cn
glizheng@hust.edu.cn
ABSTRACT
Phase Change Memory (PCM) has the potential to replace traditional DRAM memory due to its better scalability and non‐volatility. However, PCM also suffers from high write latency and energy consumption. To mitigate the write overhead of PCM‐based main memory, we propose a Fine-grained Dirtiness Aware (FDA) last-level cache (LLC) victimization scheme. The key idea of FDA is to preferentially evict cachelines with fewer dirty words when victimizing dirty cachelines. The modified word is defined to be dirty. FDA exploits two key observations. First, the write service time of a cacheline is proportional to the number of dirty words. Second, a cacheline with fewer dirty words has the same or lower reference frequency compared with other dirty cachelines. Therefore, evicting cachelines with fewer dirty words can reduce the write service time of cachelines and will not increase the miss rate. To reduce the write service time of cachelines, FDA evicts the cacheline with the fewest dirty words when victimizing dirty cachelines. We also present FDARP to decrease the miss rate by further synergizing the number of dirty words with Re‐reference Prediction Value. Experimental results show that FDA (FDARP) can improve the IPC performance by 8.3% (14.8%), decrease the write service time of cachelines by 37.0% (36.3%) and reduce write energy consumption of PCM by 27.0% (32.5%) under the mixed benchmarks.
