Energy‐Performance Design Exploration of a Low‐Power Microprogrammed Deep‐Learning Accelerator

Giulia Santoro1, Mario R. Casu1, Valentino Peluso1, Andrea Calimera1 and Massimo Alioto2
1Politecnico di Torino, 10129 Turin, IT
2National University of Singapore, 119077 Singapore, SG

ABSTRACT


This paper presents the design space exploration of a novel microprogrammable accelerator in which PEs are connected with a Network‐on‐Chip and benefit from low‐power features enabled through a practical implementation of a Dual‐ Vdd assignment scheme. An analytical model, fitted with postlayout data obtained with a 28nm FDSOI design kit, returns implementations with optimal energy‐performance tradeoff by taking into consideration all the key design‐space variables. The obtained Pareto analysis helps us infer optimization rules aimed at improving quality of design.



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