SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality
Seyedeh Golsana Ghaemi1,a, Iman Ahmadpour1,b, Mehdi Ardebili2 and Hamed Farbeh3
1Department of Computer Engineering, Sharif University of Technology, Tehran 11155‐11365, Iran
agghaemi@ce.sharif.edu
bahmadpour@ce.sharif.edu
2College of Engineering, Tehran University, Tehran 14174‐66191, Iran
m.ardebili@ut.ac.ir
3School of Computer Science, Institute for Research in Fundamental Sciences (IPM) Tehran 19538‐33511, Iran
farbeh@ipm.ir
ABSTRACT
Soft errors in on‐chip caches are the major cause of processors failure. Partitioning the cache into data and tag arrays, recent reports show that the vulnerability of the latter is as high as or even higher than that of the former. Although Error‐Correcting Codes (ECCs) are widely used to protect the data array, their overheads are not affordable in the tag array and its protection is conventionally limited to parity code. In this paper, we propose Similarity‐Managed Robust Tag (SMARTag) technique to provide the error correction capability in parity‐protected tags. SMARTag exploits the inherent similarity between the upper parts of the tags in a cache set to share these parts between addresses and ECCs. Using SMARTag, the cache access time is intact since the ECC part is bypassed in normal cache operation and no extra memory is required since ECCs are stored in available tag space. The simulation results show that SMARTag is capable of correcting more than 98% of errors in the tag array, on average, and its energy consumption, area, and performance overhead is less than 0.2%.
Keywords: Address locality, Error‐correcting code, On‐chip caches, Soft errors, Tag array.
