High Performance Collective Communication‐Aware 3D Network‐on‐Chip Architectures
Biresh Kumar Joardara, Karthi Duraisamyb and Partha Pratim Pandec
School of EECS Washington State University Pullman, USA
abjoardar@eecs.wsu.edu
bkduraisa@eecs.wsu.edu
cpande@eecs.wsu.edu
ABSTRACT
3D Network‐on‐Chip (NoC) architectures are capable of achieving better performance and lower energy consumption compared to their planar counterparts. However, conventional 3D NoCs are not efficient in handling collective communication. Existing works mainly explore Path and Tree multicast distribution schemes for 3D NoCs. However, both these mechanisms involve high network latency and lack scalability. In this work, we propose a SMART (Single‐cycle Multi‐hop Asynchronous Repeated Traversal) 3D NoC architecture that is capable of achieving high‐performance collective communication. The proposed High‐Performance SMART (HP-SMART) 3D NoC achieves 65% and 31% latency improvements compared to the existing Path and Tree multicast‐based 3D NoCs respectively. HP‐SMART 3D NoC also achieves significant improvement in message latency compared to its 2D counterpart.
