Embedded Randomness and Data Dependencies Design Paradigm: Advantages and Challenges

Itamar Levia, Yehuda Rudinb, Alexander Fishc and Osnat Kerend
Faculty of Engineering, Bar‐Ilan University, Ramat-Gan, Israel
aitamar.levi@biu.ac.il
byehuda.rudin@biu.ac.il
calexander.fish@biu.ac.il
dosnat.keren@biu.ac.il

ABSTRACT


Information leakage through physical channels is a major hurdle in embedded hardware security. This paper overviews the three key factors in the embedded hardware security space, focusing on gray‐box (bounded resources) power analysis attacks: the adversary's knowledge and abilities, the security metrics used by adversaries' and security evaluators and gate‐level countermeasures. A new design paradigm, dubbed pAsynch, that utilizes internal signals and random signals to uniformly spread the information‐carrying energy within the clock period in a specific way with a resolution below the band‐width and noise‐filtering abilities of advanced measurement equipment is introduced. The advantages and design challenges introduced by the pAsynch paradigm are discussed.

Keywords: Hardware security, Information leakage, pAsynch, Pseudo asynchronous, Side channel.


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