Examining the Consequences of High‐Level Synthesis Optimizations on Power Side‐Channel

Lu Zhang1,a, Wei Hu1,b, Armaiti Ardeshiricham2,e, Yu Tai1,c, Jeremy Blackstone2,f, Dejun Mu1,d and Ryan Kastner2,g
1Northwestern Polytechnical University, Xi'an, Shaanxi, China
awillvsnick@mail.nwpu.edu.cn
btaiyu@mail.nwpu.edu.cn
cweihu@nwpu.edu.cn
dmudejun@nwpu.edu.cn
2University of California, San Diego, La Jolla, CA
eaardeshi@ucsd.edu
fjblackst@ucsd.edu
gkastner@ucsd.edu

ABSTRACT


High‐level synthesis (HLS) allows hardware designers to think algorithmically and not have to worry about low level, cycle‐by‐cycle details. This provides the ability to quickly explore the architectural design space and trade off between resource utilization and performance. Unfortunately, evaluating the security is not a standard part of the HLS design flow. In this work, we aim to understand the effects of HLS optimizations with respect to power side‐channel leakage. We use Vivado HLS to develop different cryptographic cores, implement them on a Xilinx Spartan 6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and side-channel leakage through power consumption. Furthermore, we analyze the first‐order leakage of the HLS‐based designs alongside well‐known register transfer level (RTL) cryptographic cores. We describe an evaluation procedure for hardware designers and use it to make insightful recommendations on how to design the best architecture in cryptographic domain.



Full Text (PDF)