Ultra‐low Energy Circuit Building Blocks for Security Technologies

Sanu Mathewa, Sudhir Satpathy, Vikram Suresh and Ram Krishnamurthy
Circuits Research Lab, Intel Corporation, Hillsboro, USA
asanu.k.mathew@intel.com

ABSTRACT


Low‐area energy‐efficient security primitives are key building blocks for enabling end‐to‐end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy‐efficient circuit techniques with optimal hardware‐friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040‐gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All‐digital TRNG to achieve >0.99 min‐entropy with 3pJ/bit energy‐efficiency.



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