Precise Evaluation of the Fault Sensitivity of OOO Superscalar Processors
Rafael Billig Tonettoa, Gabriel L. Nazarb and Antonio Carlos Schneider Beckc
Instituto de Informática ‐ Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
arafael.tonetto@inf.ufrgs.br
bglnazar@inf.ufrgs.br
ccaco@inf.ufrgs.br
ABSTRACT
Since superscalar processors lead the market, their resiliency evaluation by means of fault injection grows in importance. Fault injection strategies usually trade‐off their levels of accuracy: low‐level HW‐based methods are accurate, but very expensive, need special equipment and the actual hardware, and lack controllability; while high‐level simulation‐based strategies are flexible, fast, easily accessible and have high controllability, but are not accurate since they are based on models that do not always reflect the low‐level implementation, mainly when it comes to complex designs like out‐of‐order multiple‐issue processors. In this work, we propose a cycle‐accurate fault injection platform for superscalar processors, which has a smart checkpointing mechanism to accelerate injection time, attenuating the shortcomings imposed by the aforementioned fault injection methods while providing the same level of abstraction as detailed RTL models. Leveraging from this new platform, we evaluate a complex and parameterizable Out‐of‐Order processor (BOOM) by experimenting with different issue widths and analyzing the sensitivity of several hardware structures of the processor.
Keywords: Fault injection, superscalar processor, registertransfer level.
