AMS Verification Methodology regarding Supply Modulation in RF SoCs induced by Digital Standard Cells
Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich and Stefan Heinen
Chair of Integrated Analog Circuits and RF Systems RWTH Aachen University Kopernikusstrasse 16, D‐52074 Aachen
mailbox@ias.rwth-aachen.de
ABSTRACT
Nanoscale CMOS enables and forces the use of digital‐centric RF architectures, where timing resolution is traded for analog resolution. Simultaneously, digital circuits act as aggressors endangering the performance of the time continuous digital and analog parts. The switching activities of logic cells result in power supply variations which lead to jitter in the digital signal paths and causes interferers coupling to the analog paths, appearing as e.g. phase noise, crosstalk, unwanted frequency conversion, etc. Since todays commonly used AMS simulation methods are limited to register‐transfer level (RTL) models for the digital domain, the electrical behavior caused by digital switching is not considered. Here, a method for modeling logic cells with regard to power supply noise is presented using the available characterization data of a standard cell library. It covers the influence of switching on the supply voltage as well as influences of supply variations on the digital path delay and their feedthrough to blocks of the RF domain. A fast event-driven simulation of an entire AMS system regarding the mentioned aspects is enabled. The method is demonstrated on a digitalcentric transmitter to detect the effects on system level.
