SAT‐based Redundancy Removal
Krishanu Debnath1, Rajeev Murgai2, Mayank Jain3 and Janet Olson3
1Synopsys India Private Ltd., Bengaluru, India
2Synopsys India Private Ltd., Noida, India
3Synopsys Mountain View, California, USA
ABSTRACT
Logic optimization is an integral part of digital circuit design. It reduces design area and power consumption, and quite often improves circuit delay as well. Redundancy removal is a key step in logic optimization, in which redundant connections in the circuit are determined and replaced by constant values 0 or 1. The resulting circuit is simplified, resulting in area and power savings. In this paper, we describe a redundancy removal approach for combinational circuits based on a combination of logic simulation and SAT. We show that this approach can handle large industrial‐strength designs in a reasonable amount of CPU time.
