Row-Buffer Hit Harvesting in Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
Yang Song1,a, Olivier Alavoine2 and Bill Lin1
1Electrical and Computer Engineering Department, University of California San Diego, La Jolla, CA, USA
ay6song@eng.ucsd.edu
2Qualcomm Inc., San Diego, CA, USA
ABSTRACT
In heterogeneous multicore systems, the memory subsystem, including the last‐level cache and DRAM, is widely shared among the CPU, the GPU, and the real‐time cores. Due to their distinct memory traffic patterns, heterogeneous cores result in more frequent cache misses at the last‐level cache. As cache misses travel through the memory subsystem, two schedulers are involved for the last‐level cache and DRAM respectively. Prior studies treated the scheduling of the last‐level cache and DRAM as independent stages. However, with no orchestration and limited visibility of memory traffic, neither scheduling stage is able to ensure optimal scheduling decisions for memory efficiency. Unnecessary precharges and row activations happen in DRAM when the memory scheduler is ignorant of incoming cache misses and DRAM row‐buffer states are invisible to the last‐level cache. In this paper, we propose a unified memory controller for the the last‐level cache and DRAM with orchestrated schedulers. The memory scheduler harvests row‐buffer hit opportunities in cache request buffers during spare time without inducing significant implementation cost. Extensive evaluations show that the proposed controller improves the total memory bandwidth of DRAM by 16.8% on average and saves DRAM energy by up to 29.7% while achieving comparable CPU IPC. In addition, we explore the impact of last‐level cache bypassing techniques on the proposed memory controller.
Keywords: Memory subsystem, Row‐buffer hit, Memory efficiency, Heterogeneous MPSoCs.
