One‐Way Shared Memory
Martin Schoeberl
Technical University of Denmark
masca@dtu.dk
ABSTRACT
Standard multicore processors use the shared main memory via the on‐chip caches for communication between cores. However, this form of communication has two limitations: (1) it is hardly time‐predictable and therefore not a good solution for real‐time systems and (2) this single shared memory is a bottleneck in the system. This paper presents a communication architecture for time predictable multi core systems where core‐local memories are distributed on the chip. A network‐on‐chip constantly copies data from a sender core‐local memory to a receiver core‐local memory. As this copying is performed in one direction we call this architecture a one‐way shared memory. With the use of time‐division multiplexing for the memory accesses and the network‐on‐chip routers we achieve a time predictable solution where the communication latency and bandwidth can be bounded. An example architecture for a 3x3 core processor and 32‐bit wide links and memory ports provides a cumulative bandwidth of 29 bytes per clock cycle. Furthermore, the evaluation shows that this architecture, due to its simplicity, is small compared to other network‐on‐chip solutions.
