Optimization of the PLL Configuration in a PLL‐based TRNG Design
Elie Noumon Allinia, Oto Peturab, Viktor Fischerc and Florent Bernardd
Univ Lyon, UJM Saint‐Etienne, Laboratoire Hubert Curien, UMR CNRS 5516 42000 Saint-Etienne
aelie.noumon.allini@univ-st-etienne.fr
boto.petura@univ-st-etienne.fr
cfischer@univ-st-etienne.fr
dflorent.bernard@univ-st-etienne.fr
ABSTRACT
Several recent designs show that the phase lockedloops (PLLs) are well suited for building true random number generators (TRNG) in logic devices and especially in FPGAs, in which PLLs are physically isolated from the rest of the device. However, the setup of the PLL configuration for the PLL-based TRNG is a challenging task. Indeed, the designer has to take into account physical constraints of the hardwired block, when trying to achieve required performance (bit rate) and security (entropy rate per bit). In this paper, we introduce a method aimed at choosing PLL parameters (e.g. input frequency, multiplication and division factors of the PLL) that satisfy hardware constraints, while achieving the highest possible bit rate or entropy rate according to application requirements. The proposed method is fast enough to produce all possible configurations in a short time. Comparing to the previous method based on a genetic algorithm, which was able to find only a locally optimized solution and only for one PLL in tens of seconds, the new method finds exhaustive set of feasible configurations of one‐ or two‐PLL TRNG in few seconds, while the found configurations can be ordered depending on their performance or sensitivity to jitter.
