Automatic Generation of Hardware Checkers from Formal Micro‐architectural Specifications

Alexander Fedotova and Julien Schmaltzb
Eindhoven University of Technology
aa.fedotov@tue.nl
bj.schmaltz@tue.nl

ABSTRACT


To manage design complexity, high‐level models are used to evaluate the functionality and performance of design solutions. There is a significant gap between these high‐level models and the Register Transfer Level (RTL) implementations actually produced by designers. We address the challenge of bridging this gap, namely, relating abstract specifications to RTL implementations. An important feature of our proposed approach is to support non‐deterministic specifications. From such a non‐deterministic model, we automatically compute a representation of its observable behaviour. We then turn this representation into a System Verilog checker. The checker is connected to the input and output interfaces of the RTL implementation. The resulting combination is given to a commercial EDA tool to prove inclusion of the traces of the implementation into the traces of the specification. Our method is implemented for the formal micro‐architectural description language (MaDL) ‐ an extension of the xMAS formalism originally proposed by Intel ‐ and exemplified on several examples.


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