On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths
Felipe A. Kuentzera, Leonardo R. Juracyb and Alexandre M. Amoryc
Faculty of Informatics, PUCRS University, Av. Ipiranga, Porto Alegre, Brazil
afelipe.kuentzer@acad.pucrs.br
bleonardo.juracy@acad.pucrs.br
calexandre.amory@pucrs.br
ABSTRACT
Energy efficiency has become one of the most common and important demands for contemporary applications, increasing the desire for chips that operate near the threshold voltage levels, which unfortunately worsens the effects of process, voltage, and temperature (PVT) variability. An alternative solution to cope with PVT variations are the timing resilient architectures, such as the synchronous Razor family and the asynchronous Blade template, that rely on error detection logic (EDL) to detect and recover from timing violations. On one hand, the use of timing resilient architectures makes the path delay testing more challenging because it is not a matter of simple pass or fails the test. On the other hand, we show that timing resilient architectures, such as Blade, present opportunities to design lowcost online delay testing of the critical paths. Results show the area overhead and fault coverage using functional testing on a 32‐bit MIPS CPU and a crypto core.
