MAUI: Making Aging Useful, Intentionally
Kai‐Chiang Wua, Tien‐Hung Tsengb and Shou‐Chun Lic
National Chiao Tung University, Hsinchu, Taiwan
akcw@cs.nctu.edu.tw
beric830303@gmail.com
cscli.cs02g@nctu.edu.tw
ABSTRACT
Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nano scale designs. In this paper, we propose to take advantage of aging induced clock skews (i.e., make them useful for aging tolerance) by manipulating these time‐varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging‐induced clock skews in a circuit, such that its overall performance degradation due to aging can be minimized, that is, the lifespan can be maximized. On average, 25% aging tolerance can be achieved with insignificant design overhead.
