Architecture and Optimization of Associative Memories used for the Implementation of Logic Functions based on Nanoelectronic 1S1R Cells
Arne Heittmanna and Tobias G. Nollb
Chair of Integrated Digital Systems and Circuit Design, RWTH‐Aachen University, Germany
aheittmann@ids.rwth-aachen.de
btgnoll@ids.rwth-aachen.de
ABSTRACT
A neuromorphic architecture based on Binary Associative memories and nanoelectronic resistive switches is proposed for the realization of arbitrary logic/arithmetic functions. Subsets of non‐trivial code sets based on error detecting 2‐out‐of‐n‐codes are thoroughly used to encode operands, results, and intermediate states in order to enhance the circuit reliability by mitigating the impact of device variability. 2‐ary functions can be implemented by cascading a mixer memory, a correlator memory, and a response memory. By introduction of a new cost function based on class‐specific wordline‐ coverage, stochastic optimization is applied with the aim to minimize the overall number of active amplifiers. For various exemplary functions optimized architectures are compared against solutions obtained using a standard‐cost function. It is especially shown that the consideration of word‐line‐coverage results in a significant circuit compaction.
Keywords: Resistive Switches, Selector Device, Associative Memory, Clipped Hebbian Synaptic Rule, Reliability, logic functions, arithmetic function, nanoelectronics, BiNAM.
