DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

IP5_5 Interactive Presentations

Date: Wednesday, 03 February 2021
Time: 10:30 - 11:00

Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session

Label Presentation Title
Authors
IP5_5.1 RUNTIME FAULT INJECTION DETECTION FOR FPGA-BASED DNN EXECUTION USING SIAMESE PATH VERIFICATION
Speaker:
Xianglong Feng, Rutgers University, US
Authors:
Xianglong Feng, Mengmei Ye, Ke Xia and Sheng Wei, Rutgers University, US
Abstract
Deep neural networks (DNNs) have been deployed on FPGAs to achieve improved performance, power efficiency, and design flexibility. However, the FPGA-based DNNs are vulnerable to fault injection attacks that aim to compromise the original functionality. The existing defense methods either duplicate the models and check the consistency of the results at runtime, or strengthen the robustness of the models by adding additional neurons. However, these existing methods could introduce huge overhead or require retraining the models. In this paper, we develop a runtime verification method, namely Siamese path verification (SPV), to detect fault injection attacks for FPGA-based DNN execution. By leveraging the computing features of the DNN and designing the weight parameters, SPV adds neurons to check the integrity of the model without impacting the original functionality and, therefore, model retraining is not required. We evaluate the proposed SPV approach on Xilinx Virtex-7 FPGA using the MNIST dataset. The evaluation results show that SPV achieves the security goal with low overhead.
IP5_5.2 TRULOOK: A FRAMEWORK FOR CONFIGURABLE GPU APPROXIMATION
Speaker:
Mohsen Imani, University of California Irvine, US
Authors:
Ricardo Garcia1, Fatemeh Asgarinejad1, Behnam Khaleghi1, Tajana Rosing1 and Mohsen Imani2
1University of California San Diego, US; 2University of California Irvine, US
Abstract
In this paper, we propose TruLook, a framework that employs approximate computing techniques for GPU acceleration through computation reuse as well as approximate arithmetic operations to eliminate redundant and unnecessary exact computations. To enable computational reuse, GPU is enhanced with small lookup tables which are placed close to the stream cores that return already computed values for exact and potential inexact matches. Inexact matching is subject to a threshold that is controlled by the number of mantissa bits involved in the search. Approximate arithmetic is provided by a configurable approximate multiplier that dynamically detects and approximates operations which are not significantly affected by approximation. TruLook guarantees the accuracy bound required for an application by configuring the hardware at runtime. We have evaluated TruLook efficiency on a wide range of multimedia and deep learning applications. Our evaluation shows that with 0% and less than 1% quality loss budget, TruLook yields on average 2.1× and 5.6× energy-delay product improvement over four popular networks on ImageNet dataset.