DATE 2026 Technical Programme Committee

Track D: Design Methods and Tools

addresses design automation, design tools, and Hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete and complex systems. The track’s focus includes significant improvements on existing design methods and tools, as well as forward-looking approaches to model and design future system architectures and design flows.

Topics
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Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance,real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which shall provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale Systems.

Topics
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Track T: Test and Dependability

covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon Validation challenges, and test and fault injection methods addressing system security.

Topics
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Track E: Embedded Systems Design

is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems, and dependable systems. Emphasis is also on model-based design and verification, embedded software platforms, software compilation and integration for these systems.

Topics
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Topics per Track

Track D: Design Methods and Tools

D1 System-level design methodologies and high-level synthesis

This topic focuses on methodologies and tools for system-level design and high-level synthesis (HLS), enabling the efficient development of complex hardware and hardware/software systems. It encompasses advanced techniques for translating high-level and behavioural descriptions into optimized hardware architectures, supporting both productivity and performance.
Areas of interest include high-level and system-level synthesis approaches, high-level programming languages and models for system specification and optimization, and methods for hardware/software co-design and partitioning. Contributions related to the synthesis of communication protocols and hardware/software interfaces, interface-based design, and correct-by-construction methodologies are highly encouraged. We also welcome works on control and data flow analysis, high-level scheduling, resource allocation, and binding techniques. The topic covers design space exploration strategies and systematic optimization techniques targeting both HLS and system-level design. Platform-based design approaches, IP reuse strategies, and the development of accelerator-rich architectures are particularly relevant, as are hardware/software design patterns for multi-processor systems-on-chip (MPSoCs) and heterogeneous computing platforms. Finally, we encourage to demonstrate how these system-level design and high-level synthesis methodologies apply to emerging domains, with a particular emphasis on machine learning and other compute-intensive applications.

Chair: Benjamin Carrion Schaefer, The University of Texas at Dallas, US

Co-Chair: John Wickerson, Imperial College London, GB

Topic Members

D2 System simulation and validation

This topic addresses simulation-based and semi-formal methods for the validation and verification of complex digital systems, including systems-on-chip (SoCs), cyber-physical systems, and emerging computing architectures. Contributions are invited at all levels of abstraction—from system-level down to the circuit level—with a focus on methodologies that enhance correctness, reliability, and security. Key areas include the generation and qualification of testbenches and assertions, the development and application of functional coverage metrics, and techniques for checker synthesis and optimization. We welcome submissions exploring acceleration-driven and emulation-based approaches for efficient verification, as well as simulation-based methods for pre- and post-silicon validation and debugging.
The topic also encompasses verification and validation strategies tailored to modern application domains such as the Internet of Things (IoT) and cloud infrastructures. We also invite contributions to verify non-functional requirements, such as validation of security and reliability, including the detection of vulnerabilities, with or without the integration of artificial intelligence and machine learning techniques. Note that submissions focused on the simulation of analogue circuits should be directed to topic DT4.

Chair: Prabhat Mishra, University of Florida, US

Co-Chair: Samuele Germiniani, University of Guglielmo Marconi, IT

Topic Members

D3 Formal methods and verification

This topic focuses on the use of formal methods for the modelling, specification, and verification of hardware, software, and integrated hardware/software systems. It covers rigorous techniques that ensure functional correctness, safety, and reliability across a wide range of platforms, from IP blocks and SoCs to complete systems and emerging computing paradigms. Relevant areas include the development and application of formal models, as well as verification techniques such as equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, and compositional reasoning. The topic also emphasizes advances in core algorithmic technologies supporting formal verification, particularly those based on SAT and SMT solving.
We welcome contributions on the formal verification of hardware components (including IPs, cores, and systems-on-chip), embedded software, and cyber-physical or hybrid systems with timing constraints. Additional points of interest include formal synthesis, the integration of formal techniques into mainstream design flows, and the specific challenges posed by multi-core systems, both as verification targets and as platforms for executing formal verification tools.
This topic also encourages work on the application of formal methods to emerging technologies, where correctness and trustworthiness are critical.

Chair: Stefano Quer, Politecnico di Torino, IT

Co-Chair: Farimah Farahmandi, University of Florida, US

Topic Members

DT4 Design and test for analogue and mixed-signal circuits and systems, and MEMS

Analogue, radio-frequency, mixed-signal, MEMS, circuit and system synthesis and optimization; layout and parasitic-aware synthesis; design for manufacturability, yield, reliability; analysis of variability effects; performance modelling; formal, numerical and symbolic simulation methods; topology generation; HW description languages and models of computation; self-healing and self-calibration; test generation, built-in self-test and design for testability; fault modelling, diagnosis and simulation; defect characterization and failure analysis; on-line test and fault tolerance; test metrics.

Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

Co-Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

Topic Members

DT5 Design and test of hardware security primitives

Hardware security primitives, including classical and post-quantum cryptographic circuits, multiparty computation (MPC), zero-knowledge proof systems, homomorphic encryption; side-channel countermeasure primitives and analysis (including modelling, verification, and simulation); fault injection countermeasures and attacks; physically unclonable functions (PUF) and true random number generators (TRNG); hardware trojan primitives; AI methods in hardware security; AI accelerators and their relevant physical attacks and countermeasures; nano security primitives.

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

DT6 Design and test of secure systems

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

Chair: Elif Bilge Kavun, Barkhausen Institut & TU Dresden, DE

Co-Chair: Tobias Schneider, NXP Semiconductors, AT

Topic Members

D7 Network on chip and on-chip communication

This topic covers the architecture, design methodologies, and modelling and simulation techniques for intra- and inter-chip interconnects, with a focus on network-on-chip (NoC) and general on-chip communication infrastructures. Contributions are encouraged in all aspects of NoC and interconnect design, including topology exploration, router microarchitecture, interface design, flow control mechanisms, quality of service (QoS), security, reliability, and performance optimization.
The topic welcomes work on design space exploration frameworks, communication-centric design approaches, and programming models or specifications tailored to on-chip communication. Submissions that address challenges posed by emerging technology constraints—such as designs targeting FPGAs, chiplet-based or interposer-based 2.5D and 3D integration, photonic interconnects, wireless NoCs, or non-volatile memory technologies—are particularly relevant.
We also invite contributions from application-driven perspectives, especially those focusing on interconnect solutions for high-performance computing, in-memory or near-memory computing architectures, and communication support for machine learning and artificial intelligence accelerators.

Chair: Amlan Ganguly, Rochester Institute of Technology, US

Co-Chair: Davide Bertozzi, University of Manchester, GB

Topic Members

D8 Architectural and microarchitectural design

This topic seeks innovative contributions in architectural and microarchitectural design for modern computing systems, with a particular focus on addressing key challenges related to performance, energy efficiency, scalability, and predictability. Within the architectural domain, we welcome work on the design and extension of instruction set architectures (ISA), memory system organization, and architectural mechanisms supporting concurrency and parallelism. The topic also covers multi-core and many-core architectures, application-specific architectures and domain-specific accelerators, as well as system-level architectures and architectural support for real-time and time-predictable execution. In the microarchitectural domain, we invite submissions addressing core microarchitecture design, including techniques for instruction fetch, branch prediction, and decoding, as well as register file and execution unit design. Contributions focusing on memory-related microarchitectural optimizations—such as cache hierarchy design and load/store management—are particularly relevant. Additionally, we encourage work that explores microarchitectural strategies for timing predictability and real-time constraints.
Overall, this topic places strong emphasis on innovative hardware design techniques tailored to the demands of emerging and compute-intensive workloads, including artificial intelligence, machine learning, edge and cloud computing, and autonomous systems.

Chair: Diana Goehringer, TU Dresden, DE

Co-Chair: Cristina Silvano, Politecnico di Milano, IT

Topic Members

D9 Low-power, energy-efficient and thermal-aware design

This topic focuses on theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behaviour. These can be applied to a full range of scales, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centres and cloud computing).
Topics of interest include: low-power digital circuits and systems, energy-aware system design, battery-aware system design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems; hardware/software cross-layer optimizations, with emphasis on power modelling and optimization; thermal/power monitors and knobs at circuit level; temperature modelling and prediction; thermal-power-aware optimization; thermal management for chiplets, multi-chiplet, and heterogeneous packaging; power and thermal modelling for 2.5D/3D architectures; advanced thermal simulation methodology for large-scale HPC systems; thermal-aware design for AI chips.

Chair: Massimo Poncino, Politecnico di Torino, IT

Co-Chair: Grace Li Zhang, TU Darmstadt, DE

Topic Members

D10 Approximate computing

This topic focuses on design techniques and methodologies for approximate computing across all levels of the computing stack, from circuits to software.
We invite contributions on circuit-level and architectural-level approximation, as well as techniques applied at the memory, operating system, and software layers. Both top-down and bottom-up approaches are of interest, including the design and use of finite precision arithmetic, inexact or approximate operators, and stochastic computing architectures.
The topic also encompasses cross-layer approximation strategies, where trade-offs are coordinated across multiple abstraction levels. Relevant areas include dynamic approximation techniques, quality assessment and metrics for approximate systems, and design automation tools that support the modelling, synthesis, and benchmarking of approximate computing systems.
We particularly encourage submissions that demonstrate systematic and principled methods for approximation, and that address real-world use cases or integrate approximation into broader system-level design flows.

Chair: Jie Han, University of Alberta, CA

Co-Chair: Alexandra Kourfali, EuroHPC Joint Undertaking, LU

Topic Members

D11 Reconfigurable systems

This topic focuses on reconfigurable computing systems and architectures, covering both statically and dynamically reconfigurable platforms. It includes the design, implementation, and optimization of systems that leverage reconfigurability to achieve flexibility, performance, and energy efficiency across a wide range of application domains.
We welcome contributions on heterogeneous platforms with run-time reconfiguration capabilities, reconfigurable processors, and component-level reconfiguration strategies. Particular attention is given to the use of reconfigurable computing in machine learning, data center infrastructures, and high-performance computing, where adaptability and hardware specialization are key.
The topic also encompasses research on FPGA architectures, including partial reconfiguration techniques, and advances in design methodologies and toolchains that facilitate the development of efficient reconfigurable systems. Submissions addressing design automation, resource management, and compilation flows for reconfigurable hardware are especially encouraged.
Overall, the topic invites innovations that exploit reconfigurability to meet the growing demands of performance, scalability, and adaptability in modern computing.

Chair: Dionisios Pnevmatikatos, National Technical University of Athens & ICCS, GR

Co-Chair: Stefania Perri, University of Calabria - DIMEG, IT

Topic Members

D12 Logical analysis and design

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; FPGA synthesis; arithmetic circuits; logic ECO (engineering change order); logic synthesis utilizing AI/ML techniques; interaction between logic synthesis and physical design.

Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE

Co-Chair: Jie-Hong Roland Jiang, National Taiwan University, TW

Topic Members

D13 Physical analysis and design

Statistical timing analysis and closure; asynchronous and mixed synchronous/asynchronous circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modelling, behavioural and reduced order modelling; modelling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

Chair: Matthias Fuegger, CNRS & LMF, ENS Paris-Saclay, FR

Co-Chair: Patrick Groeneveld, DAC, US

Topic Members

D14 Emerging design technologies for future computing

Modelling, circuit design, HW/SW co-design, and design automation flows for future computing, including but not limited to: logic devices based on emerging technologies (e.g., spintronics, ferroelectrics, 2D materials, tunnel transistors, coupled oscillators, NEMS, etc.); alternative interconnect technologies (e.g., optical, RF, 3D, 2D materials, spintronics, etc.); monolithic 3D integration (including TSV modelling and design space exploration, etc.).

Chair: Michael Niemier, University of Notre Dame, US

Co-Chair: Moritz Fieback, Delft University of Technology, NL

Topic Members

D15 Emerging design technologies for future memories

Modelling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, Computation-in-memory, neuromorphic computing, DNN accelerator, near memory, 3D-integration, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

Chair: Rajendra Bishnoi, Delft University of Technology,, NL

Co-Chair: Sonal Shreya, Aarhus University, DK

Topic Members

D16 Design Automation for Quantum Computing

Design methodologies and design automation for quantum and hybrid quantum-classical architectures; compilation, mapping and synthesis methods for quantum circuits; design and performance evaluation of NISQ and beyond algorithms and applications; quantum technologies and hardware architectures; simulation, verification, reliability, test, quantum error correction and error mitigation in quantum systems; design of full-stack quantum computing systems and cross-layer methodologies for NISQ and scalable modular architectures; hardware-software co-design; cryo-CMOS control electronics.

Chair: Ilia Polian, University of Stuttgart, DE

Co-Chair: Carmen G. Almudever, Technical University of Valencia, ES

Topic Members

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Track A: Application Design

A1 Power-efficiency and Smart Energy Systems for Sustainable Computing

Application design experiences and real-world implementations of power-efficient systems, smart energy systems (from uW to microgrid), life cycle optimization approaches, or minimized environmental impact circuits with high industrial relevance, especially targeting ultra-low-power, high-performance, or large-scale computing systems and related Internet-of-Things/Cyber-Physical applications for sustainable computing (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centres, and cloud systems).

Chair: David Novo, CNRS, LIRMM, University of Montpellier, FR

Co-Chair: Maxime Pelcat, IETR-INSA, FR

Topic Members

A2 Smart Society and Digital Wellness

Design experiences, practical applications, optimization, and real-life implementations of software, devices, systems, and services, from the Edge to the Cloud, for smart cities, smart homes and people wellness, based on mass market electronics, Internet of Things (IoT), Internet of Medical Things (IoMT), and Internet-of-Everything (IoE). This encompasses a diverse array of subjects, ranging from the development and deployment of advanced technologies to their seamless integration into modern everyday life by means of a variety of AI-powered smart devices and intelligent systems with sensing and acting capabilities, which are adopted in different sectors: from individual’s social care and healthcare to home automation and management of urban infrastructures. Topics of interests include, but are not limited to, the design, the optimization and the application of sensors, sensor networks, wearables, smart devices, cyberphysical and robotic systems for smart home, smart cities, and people wellness, including augmented and assisted living, social care products, healthcare devices, technologies and services for disease’s prevention, diagnosis, treatment and rehabilitation, smart transportation, environmental monitoring, resources’ supply and management (e.g., water, air, energy, etc.), lighting, street cleaning, disposal facilities, etc. including also the use of security-privacy techniques and blockchain technology, 5G and 6G mobile communications, networking devices, audio and video technologies, and advanced human-machine interfaces.

Chair: Tiziana Margaria, University of Limerick and Lero, IE

Co-Chair: Florenc Demrozi, Department of Electrical Engineering and Computer Science, University of Stavanger, NO

Topic Members

A3 Secure Systems, Circuits and Architectures

Focus on secure systems, circuits, and architectures, with an emphasis on design experiences, real-world deployments, applications, and silicon prototypes. Topics of interest include: secure hardware architectures; hardware/software implementations for post-quantum embedded cryptography (e.g., post-quantum, lightweight, homomorphic); emerging technologies for secure system design; novel architectures for embedded cryptography; demonstrations of physical attacks (e.g., fault injection, side-channel) and countermeasures; embedded processors and co-processors for security; protection of off-chip memory; secure Network-on-Chip communication and integrity; hardware-enabled security demonstrated on real systems or prototypes; logic-level security; firmware security.

Chair: Mirjana Stojilovic, EPFL, CH

Co-Chair: Cedric Marchand, Ecole centrale Lyon, FR

Topic Members

A4 Autonomous Systems and Smart Industry

This topic focuses on self-adaptive, learning and/or context-aware systems with run-time decision-making for smart sensing/acting and efficient computing/communication. It targets the compute continuum, covering high-performance compute nodes, power-constrained IoT/edge devices, reconfigurable systems, and heterogeneous/collaborative platforms. Optimization goals involve computing performance, energy/power, reliability, temperature, aging, or quality. Topics of interest include but are not limited to: Adaptive strategies for run-time resource management; Prediction/forecasting and control of self-adaptive systems; Systems and/or algorithms that can adapt their operation based on available resources and context; Data mining, modelling, and optimization techniques for adaptive systems (e.g. control automation and game theory.); Automotive; Autonomous Driving; Mobile Robotics; Human-Robot collaborations in smart factories; Industry 4.0 and 5.0; Digital Twins; Virtualization; Metaverse; 5G/6G; MEMS; Integrated sensors and transducers; Design experiences and industrial use-cases of self-adaptive systems.

Chair: Antonio Miele, Politecnico di Milano, IT

Co-Chair: Heba Khdr, Karlsruhe Institute of Technology (KIT), DE

Topic Members

A5 Applications of Emerging Technologies

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.); photonic and optoelectronic computing; memristive and memcapacitive systems; hybrid classical-quantum architectures; analogue in-memory computing; brain-inspired edge AI; molecular and chemical computing; AI-assisted materials discovery for computing devices; spintronic and skyrmionic computing; carbon nanotube based circuit and architecture design; atom-based computing platforms; quantum networking and quantum internet protocols; energy-autonomous embedded systems; sustainable and green computing technologies.

Chair: Guillermo Botella, Complutense University of Madrid, ES

Co-Chair: Yuanqing Cheng, Beihang University, CN

Topic Members

A6 Applications of Artificial Intelligence Systems

Advanced technologies and systems, software, algorithmic and co-design approaches and optimizations for artificial intelligence (AI), machine learning and deep learning solutions for domain-specific applications in the context of computing continuum and embodied AI: from resource-constrained edge devices (for example machine learning on microcontrollers and low-power processors embedded in mobile and/or autonomous systems) up to high-performance computing in the cloud and their applications. Topics of interests include Computer Vision, Natural Language Processing, Generative AI, Large Language Models, Large Vision Models, Vision-Language Models, Few-Shot Learning, Continual Learning, Distributed and Federated AI, Robust AI, Real-Time and Adaptive Inference, Quantization and Pruning, Neural Architecture Search.

Chair: Qing Wang, Delft University of Technology, NL

Co-Chair: Stefanos Laskaridis, Brave Software, GB

Topic Members

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Track T: Test and Dependability

T1 Modelling and mitigation of defects, faults, variability, and reliability

Identification, characterization, and modelling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability assessment and modelling at device, circuit, or system level; process yield modelling and enhancement; design-for-manufacturability, design-for-yield and design-for-reliability; noise and uncertainty modelling at device or circuit level; modelling and mitigation of physical sources of faults and errors such as process, voltage, temperature and temporal variations at device or circuit level.

Chair: Arnaud Virazel, LIRMM, FR

Co-Chair: Cristina Meinhardt, UFSC, BR

Topic Members

T2 Test generation, test architectures, design for test, and diagnosis

Automated test pattern generation targeting basic and advanced fault models (timing-related, defect-based, cell-aware) in a wide range of semiconductor digital integrated circuits including microprocessors, SoC, FPGAs, memories, NoCs, accelerators, hardware for machine learning and artificial intelligence, 2.5D and 3D architectures; silent data corruption; fault simulation; power and thermal issues in test; design for testability (DFT); test compression; multi-corner stress tests; volume fault diagnosis and yield analysis; logic built-in self-test (BIST) and memory BIST; in-system test; board and system-level test; test scheduling; machine learning and artificial intelligence in IC testing.

Chair: Sybille Hellebrand, Paderborn University, DE

Co-Chair: Jerzy Tyszer, Poznan University of Technology, PL

Topic Members

T3 Dependability and system-level test

As computing systems evolve—from embedded and edge devices to large-scale cloud and HPC infrastructures—ensuring reliability, safety, and fault tolerance is increasingly critical. This topic addresses system-wide dependability, spanning microarchitecture to system-level design, with a focus on cross-layer fault modelling, runtime verification, and real-time self-monitoring. It explores application-level resilience across diverse platforms, emphasizing performance, energy efficiency, and scalable runtime management through dynamic adaptation and reconfiguration. Dependability-aware high-level synthesis, approximate computing, and AI/ML techniques are investigated for predictive fault handling and adaptive control, this includes addressing the dependability of AI models is considered as well. Emerging failure modes and silent data corruptions are also considered, especially at scale, with strategies for recovery, redundancy, and survivability in all segments including cloud, edge, and embedded systems. We welcome contributions combining theoretical insights with practical solutions for building dependable, safe, and testable systems across the computing spectrum.

Chair: Stefano Di Carlo, Politecnico di Torino, IT

Co-Chair: Giulio Gambardella, Synopsys, IE

Topic Members

DT4 Design and test for analogue and mixed-signal circuits and systems, and MEMS

Analogue, radio-frequency, mixed-signal, MEMS, circuit and system synthesis and optimization; layout and parasitic-aware synthesis; design for manufacturability, yield, reliability; analysis of variability effects; performance modelling; formal, numerical and symbolic simulation methods; topology generation; HW description languages and models of computation; self-healing and self-calibration; test generation, built-in self-test and design for testability; fault modelling, diagnosis and simulation; defect characterization and failure analysis; on-line test and fault tolerance; test metrics.

Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

Co-Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

Topic Members

DT5 Design and test of hardware security primitives

Hardware security primitives, including classical and post-quantum cryptographic circuits, multiparty computation (MPC), zero-knowledge proof systems, homomorphic encryption; side-channel countermeasure primitives and analysis (including modelling, verification, and simulation); fault injection countermeasures and attacks; physically unclonable functions (PUF) and true random number generators (TRNG); hardware trojan primitives; AI methods in hardware security; AI accelerators and their relevant physical attacks and countermeasures; nano security primitives.

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

DT6 Design and test of secure systems

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

Chair: Elif Bilge Kavun, Barkhausen Institut & TU Dresden, DE

Co-Chair: Tobias Schneider, NXP Semiconductors, AT

Topic Members

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Track E: Embedded Systems Design

E1 Embedded software architecture, compilers and tool chains

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

Chair: Michele Lora, University of Verona, IT

Co-Chair: Sara Royuela, Barcelona Supercomputing Center, ES

Topic Members

E2 Real-time, dependable and privacy-enhanced systems

Real-time performance modelling, analysis and empirical evaluation; worst-case performance analysis techniques; WCET analysis techniques, real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time systems, networked and dependable systems; adaptive real-time systems; dependable real-time systems including fault-tolerance and criticality; timing analysis of security attack protection and privacy-enhancement in time-critical systems; network control and QoS for embedded applications; resource allocation and design-space exploration for real-time embedded systems; time-critical distributed systems; time-critical IoT; real-time edge and cloud computing; use of ML for real-time scheduling and analysis.

Chair: Mohammad Ashjaei, Mälardalen University, SE

Co-Chair: Federico Reghenzani, Politecnico di Milano, IT

Topic Members

E3 Machine learning solutions for embedded and cyber-physical systems

Hardware architectures, software and algorithmic approaches for embedded and edge artificial intelligence & machine learning, including deep learning, generative AI, and neuromorphic systems; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; resource-constrained embedded architectures and software for autonomy, automated reasoning, and planning algorithms; software frameworks, compilers, and techniques for deployment of ML/AI on embedded and cyber-physical devices; embedded, cyber-physical, and robotic systems exploiting edge machine learning and AI solutions; hardware/software solutions for embedded AI and machine learning in mixed-criticality systems for automotive, space, and other applications.

Chair: Francesco Conti, University of Bologna, IT

Co-Chair: Irem Boybat, IBM Research Europe - Zurich, CH

Topic Members

E4 Design methodologies for machine learning architectures

Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures; Specializations, and resource-efficient optimizations for machine learning architectures; Embedded architectures and software for autonomy, automated reasoning, and planning algorithms; Approximate architectures for machine learning applications; Learning from limited data sets; Frameworks for probabilistic and deep learning programming; Safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; In-memory and near-memory architectures design for ML; Hyperdimensional computing architectures and ML applications; Quantum computing for ML; Co-design space exploration for ML applications.

Chair: Steven Latre, University of Antwerp - IMEC, BE

Co-Chair: Hadjer Benmeziane, IBM Research, CH

Topic Members

E5 Design, specification, modelling and verification for embedded and cyber-physical systems

Modelling, design, verification, validation and optimization of complex, heterogeneous, distributed Cyber-Physical Systems (CPS); specification and analysis of functional and non-functional properties, including performance, timing, memory usage, quality-of-service, safety and reliability; meta-models and models of computation, communication, and concurrency for complex HW-SW systems and components of CPS; theories, standards, languages and tools supporting model-based design flows covering software, control, and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining, autonomy, and adaptivity in CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behaviour in smart grids); predictive and learning-based models for CPS.

Chair: Chung-Wei Lin, National Taiwan University, TW

Co-Chair: Gianluca Palermo, Politecnico di Milano, IT

Topic Members

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