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DATE 2023 Technical Programme Committee

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Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems. The track focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows and environments.

Track Chair: Lukas Sekanina, Brno University of Technology, CZ

Topics

D1 System Specification and Modelling

Chair: Julio Medina, University of Cantabria, ES

Co-Chair: Matthias Jung, Fraunhofer IESE, DE

Topic Members

  • Rainer Doemer, EECS, UC Irvine, US
  • Jakob Engblom, Intel, SE
  • Tim Kogel, Synopsys, DE
  • Laurence Pierre, Univ. Grenoble Alpes, TIMA Lab., FR
  • Todor Stefanov, Leiden University, NL
  • Min Zhang, East China Normal University, CN

Modelling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modelling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modelling and analysis of functional and non-functional system properties; modelling of system adaptivity; time and performance modelling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level- Synthesis

Chair: Christian Pilato, Politecnico di Milano, IT

Co-Chair: Lana Josipovic, ETH Zurich, CH

Topic Members

  • Lars Bauer, Karlsruhe Institute of Technology, DE
  • Alberto Antonio Del Barrio Garcia, Complutense University of Madrid, ES
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP
  • Kaan Kara, Oracle Corporation, CH
  • Dirk Koch, University of Manchester, GB
  • Preeti Ranjan Panda, Indian Institute of Technology Delhi, IN
  • Ana Lucia Varbanescu, University of Amsterdam, NL
  • Cunxi Yu, University of Utah, US
  • Wei Zhang, Hong Kong University of Science and Technology, HK
  • Peipei Zhou, University of Pittsburgh, US

High-level and system-level synthesis techniques; high-level languages for system and behavioural descriptions; system-level models for design and optimization; methods for HW-SW co-design and partitioning; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; control and data flow analysis; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures, including accelerator-rich architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems; high-level synthesis and system-level design for machine-learning applications.

D3 System Simulation and Validation

Chair: Katell Morin-Allory, TIMA Laboratory, FR

Co-Chair: Monica Farkash, AMD, US

Topic Members

  • Mingsong Chen, East China Normal University, CN
  • Tara Ghasempouri, Department of Computer System, Tallinn University of Technology, Estonia, EE
  • Daniel Grosse, Johannes Kepler University Linz, AT
  • Yusuke Kimura, Fujitsu Limited, JP
  • Avi Ziv, IBM Research - Haifa, IL

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

DT4 Design and Test for Analogue and Mixed-Signal Circuits and Systems, and MEMS

Chair: Helmut Graeb, Technical University of Munich, DE

Co-Chair: Rosa Rodríguez-Montañés, UPC, ES

Topic Members

  • Günhan Dündar, Bogazici University, TR
  • Maria Helena Fino, Nova University of Lisbon, PT
  • Linda Milor, Georgia Tech, US
  • Shahriar Mirabbasi, University of British Columbia, CA
  • Sule Ozev, ASU, US
  • Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR
  • Dani Tannir, Lebanese American University, LB

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modelling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Nele Mentens, KU Leuven, BE

Co-Chair: Kazuo Sakiyama, The University of Electro-Communications, JP

Topic Members

  • Arthur Beckers, NXP, BE
  • Ileana Buhan, Radboud University, NL
  • Milos Drutarovsky, Technical University of Kosice, SK
  • Fatemeh Ganji, Worcester Polytechnic Institute, US
  • Mike Hutter, Cryptography Research Inc., US
  • Guilherme Perin, Delft University of Technology, NL
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Rei Ueno, Tohoku University, JP
  • Bohan Yang, Tsinghua University, CN
  • Fan Zhang, Zhejiang University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modelling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Topic Members

  • Josep Balasch, KU Leuven, BE
  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Elke De Mulder, Rambus, Cryptography Research Division, FR
  • Apostolos Fournaris, Industrial Systems Institute/Research Center ATHENA, GR
  • Elif Bilge Kavun, University of Passau, DE
  • Osnat Keren, Bar-Ilan University, IL
  • Johann Knechtel, New York University Abu Dhabi, AE
  • Hristina Mihajloska, Ss. Cyril and Methodius University, Faculty of Computer Science and Engineering, MK
  • Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
  • Martin Novotny, Czech Technical University in Prague, CZ
  • Patrick Schaumont, Worcester Polytechnic Institute, US
  • Tobias Schneider, NXP Semiconductors, AT
  • Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

D7 Formal Methods and Verification

Chair: Yakir Vizel, The Technion, IL

Co-Chair: Rolf Drechsler, University of Bremen/DFKI, DE

Topic Members

  • Erika Abraham, RWTH Aachen University, DE
  • Ivana Černá, Masaryk University, CZ
  • Alexander Ivrii, IBM, IL
  • Stefano Quer, Politecnico di Torino, IT
  • Georg Weissenbacher, Vienna University of Technology, AT

Formal models of software and hardware systems; formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis; formal methods in emerging technologies.

D8 Network-on-Chip and on-chip communication

Chair: Romain Lemaire, CEA-List, FR

Co-Chair: Davide Zoni, Politecnico di Milano, IT

Topic Members

  • Jose L. Abellan, Universidad Católica San Antonio de Murcia, ES
  • José Cano, University of Glasgow, GB
  • Angelo Garofalo, University of Bologna, IT
  • Cedric Killian, University of Rennes, FR
  • John Kim, KAIST, KR
  • Hamid Sarbazi-Azad, Sharif U of Tech, IR

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, network-on-chip and on-chip communication infrastructure, including, but not limited to, topology, routers, interfaces, flow control, quality of service, security, reliability, design space exploration frameworks, on-chip communication specifications and programming models for communication-centric design. Contributions from specific applicative domains are welcomed such as interconnects for high-performance computing, in- or near-memory computing, machine-learning, artificial intelligence accelerators, GPU-based architecture. The topic also covers the design of on-chip communication infrastructures with technological constraints (FPGA, interposer/chiplet for 2.5D, 3D, photonics, non-volatile memory…).

D9 Architectural and Microarchitectural Design

Chair: Jeronimo Castrillon, TU Dresden, DE

Co-Chair: Leonidas Kosmidis, Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), ES

Topic Members

  • Pedro Benedicte, Barcelona Supercomputing Center, ES
  • Sanjukta Bhanja, University of South Florida, US
  • Francisco J Cazorla, Barcelona Supercomputing Center, ES
  • Pedro Diniz, Informatics Engineering Dept. at FEUP, PT
  • Christina Giannoula, National Technical University of Athens, GR
  • Paula Herber, University of Münster, DE
  • Alex Jones, University of Pittsburgh, US
  • Lei Ju, School of Cyber Science and Technology, Shandong University, CN
  • Vasileios Karakostas, University of Athens, GR
  • Guy Lemieux, The University of British Columbia, CA
  • Tanguy Risset, Univ Lyon, INSA Lyon, Inria, CITI, FR
  • Tajana Rosing, UCSD, US
  • Cristina Silvano, Politecnico di Milano, IT
  • Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN
  • Magnus Själander, Norwegian University of Science and Technology, NO
  • Chundong Wang, ShanghaiTech University, CN

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D10 Low-power, Energy-efficient and Thermal-aware Design

Chair: Masanori Hashimoto, Kyoto University, JP

Co-Chair: William Fornaciari, Politecnico di Milano - DEIB, IT

Topic Members

  • Sylvain Clerc, STMicroelectronics, FR
  • Amlan Ganguly, Rochester Institute of Technology, US
  • Diana Goehringer, TU Dresden, DE
  • Tohru Ishihara, Nagoya University, JP
  • Georgios Karakonstantis, Queen's University Belfast, GB
  • Ivan Miro-Panades, CEA-List, FR
  • Youngsoo Shin, KAIST, KR
  • Dimitrios Soudris, NTUA, GR
  • Grace Li Zhang, TU Darmstadt, DE
  • Cheng Zhuo, Zhejiang University, CN

Theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behaviour. These can be applied to a full range of applications, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centres and cloud computing). Topics of interest include: thermal/power monitors and knobs at circuit level; hardware/software cross-layer optimizations, with emphasis on power modelling and optimization; temperature modelling and prediction; thermal-power-aware optimization; energy-aware design, battery-aware design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems.

D11 Approximate Computing

Chair: Jie Han, University of Alberta, CA

Co-Chair: Daniel Menard, INSA Rennes, FR

Topic Members

  • Mario Barbareschi, University of Naples Federico II, IT
  • Honglan Jiang, Shanghai Jiao Tong University, CN
  • Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
  • Veljko Pejovic, University of Ljubljana, SI
  • Laura Pozzi, USI Lugano, CH
  • Florian Scheidegger, IBM Research GmbH, CH
  • Zdenek Vasicek, Brno University of Technology, CZ
  • Lan Wei, University of Waterloo, CA

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking; design techniques for stochastic computing.

D12 Reconfigurable Systems

Chair: Ioannis Sourdis, Chalmers University of Technology, SE

Co-Chair: Christos Bouganis, Imperial College London, GB

Topic Members

  • Mohamed Abdelfattah, Samsung AI Center, GB
  • Catalin Bogdan Ciobanu, Transilvania University of Brasov, RO
  • Jan Korenek, Brno University of Technology, CZ
  • Miriam Leeser, Northeastern University, US
  • Bogdan Pasca, Intel, FR
  • Dionisios Pnevmatikatos, School of ECE, National Technical University of Athens & FORTH-ICS, GR
  • Mirjana Stojilovic, EPFL, CH

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data centre and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D13 Logical and Physical Analysis and Design

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT

Co-Chair: L. Miguel Silveira, INESC ID/IST - Lisbon University, PT

Topic Members

  • Laleh Behjat, University of Calgary, CA
  • Valentina Ciriani, Universita' degli Studi di Milano, IT
  • Luca Daniel, M.I.T., US
  • Alper Demir, Koc University, TR
  • Elena Dubrova, Royal Institute of Technology - KTH, SE
  • Shao-Yun Fang, National Taiwan University of Science and Technology, TW
  • Amin Farshidi, Cadence Design Systems, US
  • Petr Fišer, Czech Technical University in Prague, FIT, CZ
  • Masahiro Fujita, University of Tokyo, JP
  • Igor L. Markov, University of Michigan, US
  • Mayler Martins, Mentor Graphics, US
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
  • Eleonora Testa, Synopsys Inc., CH
  • Wenjian Yu, Tsinghua University, CN

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modelling, behavioural and reduced order modelling; modelling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D14 Emerging Design Technologies for Future Computing

Chair: Alessio Spessot, Imec, BE

Co-Chair: Vihar Georgiev, University of Glasgow, GB

Topic Members

  • Mohamed M. Sabry Aly, Nanyang Technological University, SG
  • Veeresh Deshpande, Helmholtz Zentrum Berlin, DE
  • Andrea Ghetti, Micron Technology, IT
  • Maria Loreto Mateu Saez, Fraunhofer IIS, DE
  • Pierpaolo Palestri, DPIA, University of Udine, IT
  • Heike Riel, IBM Research, CH
  • Victor Sverdlov, CDL NovoMemLog IuE TUWien, AT
  • Aida Todri-Sanial, LIRMM, University of Montpellier, CNRS, FR
  • Elisa Vianello, CEA Leti, FR
  • Tony Wu, Facebook, US

Modelling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modelling and design space exploration).

D15 Emerging Design Technologies for Future Memories

Chair: Alexandre Levisse, EPFL, CH

Co-Chair: Jean-Philippe Noel, CEA, FR

Topic Members

  • Rajendra Bishnoi, Delft University of Technology,, NL
  • Irem Boybat, IBM Research - Zurich, CH
  • Amlan Ghosh, Intel Corporation, US
  • Daniele Ielmini, Poltecnico di Milano, IT
  • Fabrizio Riente, Politecnico di Torino, IT
  • Joachim Rodrigues, Lund University, SE
  • Stefan Slesazeck, NaMLab gGmbH, DE
  • Nima TaheriNejad, TU Wien, AT
  • Xueyan Wang, Beihang University, CN
  • Tianyao Xiao, Sandia National Laboratories, US
  • Mengying Zhao, Shandong University, CN

Modelling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.


Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which will provide viable solutions in tomorrow’s silicon, embedded systems and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Alberto Bosio, University of Lyon, FR

Topics

A1 Power-efficient and Sustainable Computing

Chair: Andreas Burg, EPFL-TCL, CH

Co-Chair: Semeen Rehman, TU Wien, AT

Topic Members

  • Andrea Bartolini, University of Bologna, IT
  • Koushik Chakraborty, Utah State University, US
  • Mingu Kang, University of Illinois at Urbana Champaign, US
  • Saibal Mukhopadhyay, Georgia Institute of Technology, US
  • Anuj Pathania, University of Amsterdam, NL
  • Qinru Qiu, Syracuse University, US
  • Georgios Zervakis, University of Patras, GR

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centres, and cloud systems). Topics of interest include: hardware and software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; approximate arithmetic HW designs; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-centre management strategies; smart maintenance for embedded devices; SW/OS-level implementations in real systems and data centres; energy-efficient big data management; data centres powered by renewable energy sources and data centres in smart grids; simulation methodologies, open-source tools, frameworks, data sets.

A2 Smart Cities, Internet of Everything, Industry 4.0

Chair: Graziano Pravadelli, University of Verona, IT

Co-Chair: Christos Kyrkou, KIOS CoE, University of Cyprus, CY

Topic Members

  • UmaMaheswari Devi, IBM Research - India, IN
  • Franco Fummi, University of Verona, IT
  • Michael Huebner, Brandenburg Technical University Cottbus, DE
  • Prachi Joshi, General Motors, R&D, US
  • Srinivas Katkoori, University of South Florida, US
  • Kamalakanta Mahapatra, NIT Rourkela, INDIA, IN
  • Tiziana Margaria, University of Limerick and Lero, IE

Applications, design experiences and real-life implementations of theory, design, construction, manufacture and/or end-use of mass market electronics, systems, software, and services for smart cities, smart industries, smart homes, smart consumer electronics, Internet of Things (IoT), and Internet-of-Everything (IoE). Topics of interest include: smart and sustainable mobility; smart transportation; smart economy; smart environment (including street cleaning, water management, water supply, air quality monitoring, disposal facilities, lighting, etc.). Other topics of interest are the verticals of IoT, IoE, Industry 4.0, Consumer Electronics, smart home, and smart cities including: smart wearables; robotic systems for smart cities and smart homes; smart sensors; blockchain technology; video technology; audio technology; white goods; home care products; mobile communications; gaming; air care products; home automation and networking devices; home theatre; digital imaging; in-vehicle technology; cable & satellite technology; home security; domestic lighting; human interface; consumer storage technology; AI/ML techniques for these smart systems; energy-management techniques for these systems; security-privacy techniques for these systems.

A3 Automotive Systems and Smart Energy Systems

Chair: Selma Saidi, Technische Universität Dortmund, DE

Co-Chair: Michele Magno, ETH Zurich, CH

Topic Members

  • Donkyu Baek, Chungbuk National University, KR
  • Domenico Balsamo, Newcastle University, GB
  • Jan Beutel, University of Innsbruck, AT
  • Davide Brunelli, University of Trento, IT
  • Lulu Chan, NXP Semiconductors, NL
  • Philipp Mundhenk, Robert Bosch GmbH, DE
  • Massimo Poncino, Politecnico di Torino, IT

Design experiences for automotive systems, autonomous robotics and UAV, energy-neutral embedded systems, smart energy systems (from uW to microgrid) and energy efficient smart sensors, and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits, smart energy systems, and embedded platforms with particular interest in energy efficient intelligent system; MEMS; integrated sensors and transducers; machine learning on microcontrollers and low power processors, RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; smart autonomous algorithms and systems for electric vehicles and unmanned aerial vehicle; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalised Healthcare

Chair: Marina Zapater, University of Applied Sciences Western Switzerland (HES-SO), CH

Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT

Topic Members

  • Simone Benatti, University of Bologna, IT
  • Andrea Cossettini, ETH Zurich, CH
  • Brendan O'Flynn, Tyndall National Institute - University College Cork, IE
  • Josué Pagán, Technical University of Madrid, ES
  • Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR
  • Amir M. Rahmani, University of California, Irvine, US

Design experiences covering the use of body area networks, assistive and wearable technologies, robot-assisted living and healthcare, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures

Chair: Pascal Benoit, University of Montpellier, FR

Co-Chair: Johanna Sepúlveda, Airbus Defence and Space, DE

Topic Members

  • Noémie Boher, SGS Brightsight, NL
  • Ray Cheung, City University of Hong Kong, HK
  • Julien Francq, Naval Group, FR
  • Bogdan Groza, Politehnica Unviersity Timisoara, RO
  • Jawad Haj-Yahya, ETH Zurich, CH
  • Basel Halak, Southampton University, GB
  • Matthias Hiller, Fraunhofer AISEC, DE
  • Michail Maniatakos, New York University Abu Dhabi, AE
  • Haiyu Mao, ETH Zurich, CH
  • Amir Moradi, Ruhr University Bochum, DE
  • Maria Mushtaq, Telecom Paris, FR
  • Johannes Obermaier, -, DE
  • Pascal Sasdrich, Ruhr-Universität Bochum, DE
  • Nicolas Sklavos, Computer Engineering and Informatics Department, University of Patras, GR
  • Jo Vliegen, ES&S, imec-COSIC, ESAT, KU Leuven, BE

Secure systems, circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; hardware/software implementations architectures for post quantum embedded cryptography (e.g., post-quantum, lightweight, homomorphic); emerging technologies for secure systems, circuits and architectures; novel architectures for embedded cryptography; demonstrations of fault or other physical attacks (e.g., fault, side-channel) and countermeasures; embedded processors or co-processors for security; protection of off-chip memories, and Network-on-Chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Context-aware Systems

Chair: Geoff Merrett, University of Southampton, GB

Co-Chair: Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR

Topic Members

  • Woongki Baek, UNIST, KR
  • Heba Khdr, Karlsruhe Institute of Technology (KIT), DE
  • Antonio Miele, Politecnico di Milano, IT
  • Priyadarshini Panda, Yale University, US
  • Amit Kumar Singh, University of Essex, GB
  • Stefanos Skalistis, United Technologies Research Centre, IE

Self-adaptive, learning and context-aware systems for run-time decision-making. This includes systems and algorithms targeting various optimization goals such as compute performance, energy/power-efficiency, reliability, temperature, aging or quality. It also considers various architectural platforms, such as high-performance compute nodes, power-constrained IoT/edge computing technologies, reconfigurable systems and heterogeneous/collaborative platforms. Such approaches may utilise machine learning techniques to achieve the desired behaviour. The relationship to computer and/or electronic system design must be clearly apparent in all submissions. Topics of interests include, but are not limited to: adaptive strategies for run-time resource management; prediction/forecasting and control of self-adaptive systems (for example using machine learning techniques for offline and/or online modelling); adaptive systems and/or algorithms which can adapt their operation based on available resources, external contexts, etc; application of diverse data mining, modelling and optimization techniques for adaptive systems (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems.

A7 Applications of Emerging Technologies

Chair: Mariagrazia Graziano, Politecnico di Torino, IT

Co-Chair: Sébastien Le Beux, Concordia University, CA

Topic Members

  • Ilke Ercan, TU Delft, NL
  • Giulia Meuli, Synopsys, IT
  • Sudip Poddar, Johannes Kepler University, AT
  • Paulina Powroznik, Silesian University of Technology, PL
  • Frank Sill Torres, German Aerospace Center, DE
  • Elena Ioana Vatajelu, TIMA, FR
  • Shigeru Yamashita, Ritsumeikan University, JP
  • Yaoyao Ye, Department of Micro/Nano Electronics, School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, CN
  • Xunzhao Yin, Zhejiang University, CN

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers

Chair: Christian Weis, University of Kaiserslautern, DE

Co-Chair: Michelangelo Grosso, STMicroelectronics s.r.l., IT

Topic Members

  • Mohamed Ibrahim, University of California, Berkeley, US
  • Veit B. Kleeberger, Infineon Technologies, DE
  • Marta Portela Garcia, Arquimea Research Center, ES
  • Wenjing Rao, University of Illinois at Chicago, US

Short 2-pages industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


Track T: Test and Dependability

covers all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit- and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges and test or fault injection methods addressing system security.

Track Chair: Ilia Polian, University of Stuttgart, DE

Topics

T1 Modelling and Mitigation of Defects, Faults, Variability, and Reliability

Chair: Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT

Co-Chair: Mottaqiallah Taouil, Delft University of Technology, NL

Topic Members

  • Hussam Amrouch, University of Stuttgart, DE
  • Davide Appello, STMicroelectronics, IT
  • Daniel Arumi, UPC, ES
  • Leticia Maria Bolzani Poehls, RWTH Aachen University, DE
  • Naghmeh Karimi, University of Maryland Baltimore County, US
  • Huawei Li, Institute of Computing Technology, Chinese Academy of Sciences, CN
  • Christian Sauer, Cadence Design Systems, DE
  • Hank Walker, Texas A&M University, US

Identification, characterization, and modelling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modelling at device, circuit, or component level; process yield modelling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modelling at circuit and component level; modelling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY

Co-Chair: Grzegorz Mrugalski, Siemens EDA, PL

Topic Members

  • Sybille Hellebrand, University of Paderborn, DE
  • Maksim Jenihhin, Tallinn University of Technology, EE
  • Chrysovalantis Kavousianos, Department of Computer Science and Engineering, University of Ioannina, GR
  • Teresa McLaurin, ARM, US
  • Melanie Schillinsky, NXP Germany GmbH, DE
  • Xiaoqing Wen, Kyushu Institute of Technology, JP

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Dependability and System-Level Test

Chair: Karthik Pattabiraman, University of British Columbia, CA

Co-Chair: Dimitris Gizopoulos, University of Athens, GR

Topic Members

  • Nandhini Chandramoorthy, IBM Research, US
  • Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
  • Michael Paulitsch, Intel, DE
  • Paolo Rech, LANL/UFRGS, US
  • Juan Carlos Ruiz Garcia, Universitat Politecnica de Valencia, ES
  • Rishad Shafik, Newcastle University, GB
  • Taiki Uemura, Samsung Electronics, KR
  • Radha Venkatagiri, Oregon State University, US

HW and SW solutions for system’s dependability crossing all layers of the system’s stack: microarchitecture-level and system-level error/fault modelling; cross-layer dependability analysis and evaluation; reliable and fail-safe architectures and systems design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT4 Design and Test for Analogue and Mixed-Signal Circuits and Systems, and MEMS

Chair: Helmut Graeb, Technical University of Munich, DE

Co-Chair: Rosa Rodríguez-Montañés, UPC, ES

Topic Members

  • Günhan Dündar, Bogazici University, TR
  • Maria Helena Fino, Nova University of Lisbon, PT
  • Linda Milor, Georgia Tech, US
  • Shahriar Mirabbasi, University of British Columbia, CA
  • Sule Ozev, ASU, US
  • Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR
  • Dani Tannir, Lebanese American University, LB

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modelling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Nele Mentens, KU Leuven, BE

Co-Chair: Kazuo Sakiyama, The University of Electro-Communications, JP

Topic Members

  • Arthur Beckers, NXP, BE
  • Ileana Buhan, Radboud University, NL
  • Milos Drutarovsky, Technical University of Kosice, SK
  • Fatemeh Ganji, Worcester Polytechnic Institute, US
  • Mike Hutter, Cryptography Research Inc., US
  • Guilherme Perin, Delft University of Technology, NL
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Rei Ueno, Tohoku University, JP
  • Bohan Yang, Tsinghua University, CN
  • Fan Zhang, Zhejiang University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modelling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Topic Members

  • Josep Balasch, KU Leuven, BE
  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Elke De Mulder, Rambus, Cryptography Research Division, FR
  • Apostolos Fournaris, Industrial Systems Institute/Research Center ATHENA, GR
  • Elif Bilge Kavun, University of Passau, DE
  • Osnat Keren, Bar-Ilan University, IL
  • Johann Knechtel, New York University Abu Dhabi, AE
  • Hristina Mihajloska, Ss. Cyril and Methodius University, Faculty of Computer Science and Engineering, MK
  • Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
  • Martin Novotny, Czech Technical University in Prague, CZ
  • Patrick Schaumont, Worcester Polytechnic Institute, US
  • Tobias Schneider, NXP Semiconductors, AT
  • Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.


Track E: Embedded Systems Design

is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems and dependable systems. Emphasis is, also, on model-based design and verification, embedded software platforms, software compilation and integration for these systems.

Track Chair: Liliana Cucu, Inria, FR

Topics

E1 Embedded Software Architecture, Compilers and Tool Chains

Chair: Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG

Co-Chair: Ahmed Rezine, Linköping University, SE

Topic Members

  • Urbi Chatterjee, Indian Institute of Technology Kanpur, IN
  • Eunsuk Kang, Carnegie Mellon University, US
  • Michele Lora, University of Southern California, US
  • Hiren Patel, University of Waterloo, CA
  • Eduardo Quinones, Barcelona Supercomputing Center, ES
  • Marjan Sirjani, Mälardalen University, SE
  • Yi Wang, Shenzhen University, CN
  • Chen Yu-Fang, Academia Sinica, TW

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E2 Real-time, Dependable and Privacy-Enhanced Systems

Chair: Marko Bertogna, University of Modena, IT

Co-Chair: Mitra Nasri, Eindhoven University of Technology, NL

Topic Members

  • Yasmina ABDEDDAÏM, Univ Gustave Eiffel, CNRS, LIGM, FR
  • Matthias Becker, KTH Royal Institute of Technology, SE
  • Gedare Bloom, University of Colorado Colorado Springs, US
  • Dakshina Dasari, Robert Bosch GmbH, Germany, DE
  • Julien Forget, Univ. Lille, FR
  • Nan Guan, City University of Hong Kong, HK
  • Xu Jiang, Northeastern University, CN
  • Jing Li, New Jersey Institute of Technology, US
  • Martina Maggio, Saarland University, DE
  • Renato Mancuso, Boston University, US
  • claire pagetti, ONERA, FR
  • Federico Reghenzani, Politecnico di Milano, IT
  • Christine Rochange, University of Toulouse, FR

Real-time performance modelling, analysis and empirical evaluation; worst-case performance analysis techniques; WCET analyses, real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; security attack protection and analysis of embedded systems' hardware and software; privacy-enhanced and safety-enhanced systems; network control and QoS for embedded applications.

E3 Machine Learning Solutions for Embedded and Cyber-Physical Systems

Chair: Mario R. Casu, Politecnico di Torino, Department of Electronics and Telecommunications, IT

Co-Chair: Cong Hao, Georgia Institute of Technology, US

Topic Members

  • Mladen Berekovic, Universität zu Lübeck, DE
  • Yao Chen, National University of Singapore, SG
  • Anup Das, Drexel University, US
  • Kaoutar El Maghraoui, IBM, US
  • Charlotte Frenkel, Delft University of Technology, NL
  • Maryam Hemmati, University of Auckland, NZ
  • Axel Jantsch, TU Wien, AT
  • Jung-Eun Kim, Department of Computer Science, North Carolina State University, US
  • Kyuho Lee, UNIST, KR
  • Andrés Otero, Universidad Politécnica de Madrid, ES
  • Hamza Ouarnoughi, INSA Hauts-de-France, FR
  • Işıl Öz, Izmir Institute of Technology, TR
  • Abbas Rahimi, IBM Research, CH
  • Sander Stuijk, Eindhoven University of Technology, NL
  • Li-Rong Zheng, Fudan University, CN
  • Guanwen Zhong, AMD-Xilinx Research Labs, SG

Hardware architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning solutions; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; case studies of machine learning applications implemented on embedded systems and cyber physical systems.

E4 Design Methodologies for Machine Learning Architectures

Chair: Tushar Krishna, Georgia Institute of Technology, US

Co-Chair: Smail Niar, INSA Hauts-de-France and CNRS, FR

Topic Members

  • Giovanni Ansaloni, EPFL, CH
  • Francesco Conti, University of Bologna, IT
  • Henk Corporaal, TU/e (Eindhoven University of Technology), NL
  • Steve Dai, NVIDIA, US
  • Giulio Gambardella, Synopsys, IE
  • Jan Moritz Joseph, RWTH Aachen University, DE
  • Sheng-Chun Kao, Georgia Institute of Technology, US
  • Souvik Kundu, Intel AI Labs, US
  • Steven Latre, University of Antwerp - IMEC, BE
  • Huichu Liu, Facebook Inc., US
  • Paolo Meloni, Università degli Studi di Cagliari, IT
  • Miguel Peón Quirós, EPFL ESL, CH
  • Priyanka Raina, Stanford University, US
  • Jae-sun Seo, Arizona State University, US
  • Swagath Venkataramani, IBM T. J. Watson Research Center, US
  • Lei Yang, George Mason University, US

Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures; specializations, and resource-efficient optimizations for machine learning architectures; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing.

E5 Design Modelling and Verification for Embedded and Cyber-Physical Systems

Chair: Roberto Passerone, University of Trento, IT

Co-Chair: Patricia Derler, Kontrol, US

Topic Members

  • Luís Almeida, University of Porto, PT
  • Jian-Jia Chen, TU Dortmund, DE
  • Martin Horauer, University of Applied Sciences Technikum Wien, AT
  • Hokeun Kim, Hanyang University, KR
  • Chung-Wei Lin, National Taiwan University, TW
  • Ahlem Mifdaoui, University of Toulouse- ISAE, FR
  • Pierluigi Nuzzo, University of Southern California, US
  • Qi Zhu, Northwestern University, US

modelling, design, verification, validation and optimization of embedded systems and Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things as well as software-intensive CPS; modelling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, quality-of-service, safety and reliability; theories, languages and tools supporting model-based design flows covering software, control and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining and CPS, autonomous CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behavior in smart grids).