Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Cristiana Bolchini, Politecnico di Milano, IT

Topics

D1 System Specification and Modeling

Chair: Frederic Mallet, Universite Cote d'Azur, FR

Co-Chair: Gianluca Palermo, Politecnico di Milano, IT

Topic Members

• Patricia Derler, National Instruments, US
• Abdoulaye Gamatie, CNRS LIRMM / University of Montpellier, FR
• Sabine Glesner, Technische Universität Berlin, DE
• Jorn Janneck, Lund University, SE
• Matthias Jung, Fraunhofer IESE, DE
• Julio Medina, University of Cantabria, ES

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; modeling of system adaptivity; time and performance modeling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level Synthesis

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR

Topic Members

• Alberto Antonio Del Barrio Garcia, Complutense University of Madrid, ES
• Michael Glaß, Ulm University, DE
• Soonhoi Ha, Seoul National University, KR
• Luciano Lavagno, Politecnico di Torino, IT
• Razvan Nane, TU Delft, NL
• Preeti Ranjan Panda, IIT Delhi, IN
• Sudeep Pasricha, Colorado State University, US
• Christian Pilato, Politecnico di Milano, IT
• Donatella Sciuto, Politecnico di Milano, IT
• Jason Xue, City University of Hong Kong, HK
• Wei Zhang, Hong Kong University of Science and Technology, HK
• Zhiru Zhang, Cornell University, US

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

D3 System Simulation and Validation

Chair: Graziano Pravadelli, University of Verona, IT

Co-Chair: Avi Ziv, IBM Research - Haifa, IL

Topic Members

• Mingsong Chen, East China Normal University, CN
• Flavio M. de Paula, IBM Corporation, US
• Masahiro Fujita, University of Tokyo, JP
• Daniel Grosse, University of Bremen/DFKI, DE
• Katell Morin-Allory, TIMA Laboratory, FR
• Jaan Raik, Tallinn University of Technology, EE

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

D4 Formal Methods and Verification

Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT

Co-Chair: Anna Slobodova, Centaur Technology, US

Topic Members

• Stefano Quer, Politecnico di Torino, IT
• Heinz Riener, EPFL, CH
• Christoph Scholl, University Freiburg, DE
• Yakir Vizel, The Technion, IL
• Georg Weissenbacher, Vienna University of Technology, AT

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Manuel Barragan, TIMA Laboratory, FR

Co-Chair: Mark Po-Hung Lin, National Chiao Tung University, TW

Topic Members

• Günhan Dündar, Bogazici University, TR
• Helmut Graeb, Technical University of Munich, DE
• Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
• Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR
• Shahriar Mirabbasi, University of British Columbia, CA
• Manoj Sachdev, University of Waterloo, CA
• Zheng Zhang, University of California, Santa Barbara, US

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics; verification and simulation of analog and mixed-signals.

DT6 Design and Test of Secure Systems

Chair: Ilia Polian, University of Stuttgart, DE

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL

Topic Members

• Georg T. Becker, DSI Berlin, DE
• Anupam Chattopadhyay, Nanyang Technological University, SG
• Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
• Viktor Fischer, Hubert Curien Laboratory, Jean Monnet University, FR
• Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
• Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
• Mike Hutter, Cryptography Research Inc., US
• Elif Bilge Kavun, The University of Sheffield, GB
• Kerstin Lemke-Rust, Bonn-Rhein-Sieg University of Applied Sciences, DE
• Nele Mentens, KU Leuven, BE
• Stjepan Picek, TU Delft, NL
• Francesco Regazzoni, ALaRI, CH
• Kazuo Sakiyama, The University of Electro-Communications, JP
• Patrick Schaumont, Worcester Polytechnic Institute, US
• Matthias Schunter, Intel Labs, DE
• Johanna Sepúlveda, Airbus Defence and Space, DE
• Ruggero Susella, STMicroelectronics, IT
• Vincent Verneuil, NXP Semiconductors, DE

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW Trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; interplay between machine learning and security.

D7 Network on Chip and Communication-Centric Design

Chair: Romain Lemaire, CEA-Leti, FR

Co-Chair: Li-Shiuan Peh, Professor, National University of Singapore, SG

Topic Members

• Daniel Chillet, University of Rennes 1, FR
• Jean-Philippe Diguet, Lab-STICC, CNRS, FR
• Paul Gratz, Texas A&M University, US
• Gabriela Nicolescu, Polytechnique Montréal, CA
• Vassos Soteriou, Cyprus University of Technology, CY
• Jiang Xu, Hong Kong University of Science and Technology, HK
• Davide Zoni, Politecnico di Milano, IT

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, in-memory computing, machine learning, etc.); design of interconnects using alternative/emerging technologies (photonics, 2.5D/3D, quantum computing, etc.).

D8 Architectural and Microarchitectural Design

Chair: Francisco J Cazorla, Barcelona Supercomputing Center, ES

Co-Chair: Olivier Sentieys, INRIA, FR

Topic Members

• Hossein Asadi, Sharif University of Technology, IR
• Jeronimo Castrillon, TU Dresden, DE
• Caroline Collange, Inria, FR
• Zhenman Fang, Simon Fraser University, CA
• Houman Homayoun, George Mason University, US
• Christophe Jego, IMS Labo, Bordeaux INP, FR
• Lei Ju, School of Cyber Science and Technology, Shandong University, CN
• Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
• Leonidas Kosmidis, Barcelona Supercomputing Center (BSC), ES
• Guy Lemieux, The University of British Columbia, CA
• Gokhan Memik, Northwestern University, US
• Miquel Pericas, Chalmers University of Technology, SE
• Tanguy Risset, Inria/INSA-Lyon, FR
• Alberto Ros, Universidad de Murcia, ES
• Cristina Silvano, Politecnico di Milano, IT
• Magnus Själander, Norwegian University of Science and Technology, NO

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D9 Low-power, Energy-efficient and Thermal-aware Design

Chair: Andrea Calimera, Politecnico di Torino, IT

Co-Chair: Pascal Vivet, CEA-Leti, FR

Topic Members

• Paolo Amato, Micron, IT
• Nadine Azemard, LIRMM, FR
• Yiran Chen, Duke University, US
• Mahesh Chowdhary, STMicroelectronics, US
• Masanori Hashimoto, Osaka University, JP
• Mohamed M. Sabry, Nanyang Technological University, SG
• Alberto Macii, Politecnico di Torino, IT
• Alberto Nannarelli, Technical University, DK
• Davide Rossi, University Of Bologna, IT
• Sheldon Tan, University of California at Riverside, US
• Chi Ying Tsui, HKUST, HK
• Rene van Leuken, Delft University of Technology, NL
• Daniel Wong, University of California, Riverside, US

Theories, tools and methodologies to design electronic systems with low power consumption, high energy efficiency, and correct thermal behavior, ranging from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centers and cloud computing). Topics of interest include: solutions applicable to all layers of design (hardware, software and any cross-layers) with emphasis on power modeling and optimization, temperature modeling and prediction, thermal-power-aware optimization, energy-aware design, battery-aware design, including thermal-power-aware optimization for application specific designs (e.g. AI, ML, etc), smart management of heterogeneous energy-sources, energy harvesting for cyber-physical systems.

D10 Approximate Computing

Chair: Lukas Sekanina, Brno University of Technology, CZ

Co-Chair: Tajana Rosing, UCSD, US

Topic Members

• Nikolaos Bellas, University of Thessaly, GR
• Benjamin Carrion Schaefer, The University of Texas at Dallas, US
• Nikil Dutt, University of California, US
• Andreas Gerstlauer, The University of Texas at Austin, US
• Seokhyeong Kang, Pohang University of Science and Technology, KR
• Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
• Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
• Fabrizio Lombardi, Northeastern University, US
• Cristiano Malossi, IBM Research - Zurich, CH
• Daniel Menard, INSA Rennes, FR
• David Novo, CNRS, LIRMM, University of Montpellier, FR
• Marco Platzner, University of Paderborn, DE
• Anand Raghunathan, Purdue University, US
• Sotirios Xydis, National Technical University of Athens, GR

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking.

D11 Reconfigurable Systems

Chair: Philip Brisk, University of California, Riverside, US

Co-Chair: Suhaib A. Fahmy, University of Warwick, GB

Topic Members

• Christos Bouganis, Imperial College London, GB
• Alessandro Cilardo, University of Naples Federico II, IT
• Nachiket Kapre, University of Waterloo, CA
• Bogdan Pasca, Intel, FR
• Marco D. Santambrogio, Politecnico di Milano, IT
• Ioannis Sourdis, Chalmers University of Technology, SE
• Stephan Wong, Delft University of Technology, NL

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D12 Logical and Physical Analysis and Design

Chair: L. Miguel Silveira, INESC ID/IST - Lisbon University, PT

Co-Chair: Mathias Soeken, EPFL, CH

Topic Members

• Luca Amaru, Synopsys, US
• Anna Bernasconi, Universita' di Pisa, IT
• Vinicius Callegaro, Mentor, a Siemens Business, USA, US
• Alper Demir, Koc University, TR
• Petr Fišer, Czech Technical University in Prague, FIT, CZ
• Igor L. Markov, University of Michigan, US
• Christos Sotiriou, Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE), GR
• Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
• Bei Yu, The Chinese University of Hong Kong, HK
• Wenjian Yu, Tsinghua University, CN

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D13 Emerging Design Technologies for Future Computing

Chair: Elena Gnani, University of Bologna, IT

Co-Chair: Subhasish Mitra, Stanford University, US

Topic Members

• Yuanqing Cheng, Beihang University, CN
• Maria Merlyne De Souza, The university of Sheffield, GB
• Thomas Ernst, Cea Leti, FR
• Mariagrazia Graziano, Politecnico di Torino, IT
• Gage Hills, Massachusetts Institute of Technology, US
• Shaloo Rakheja, University of Illinois at Urbana-Champaign, US
• Arijit Raychowdhury, Georgia Institute of Technology, US
• Heike Riel, IBM Research, CH
• Alessio Spessot, Imec, BE
• Walter Weber, TU Wien, AT

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D14 Emerging Design Technologies for Future Memories

Chair: Shahar Kvatinsky, Technion, IL

Co-Chair: Chengmo Yang, University of Delaware, US

Topic Members

• Joseph Friedman, University of Texas at Dallas, US
• Arne Heittman, RWTH Aachen University, DE
• Yu Hua, Huazhong University of Science and Technology, CN
• Alexandre Levisse, EPFL, CH
• Shuangchen Li, Alibaba Group, US
• Chenchen Liu, University of Maryland, Baltimore County, US
• Jean-Philippe Noel, CEA, FR
• Damien Querlioz, Univ Paris-Sud, FR
• Stefan Slesazeck, NaMLab gGmbH, DE
• Marco Vacca, Politecnico di Torino, IT
• Wujie Wen, Lehigh Unversity, US
• Hao Yu, Southern University of Science and Technology, China, CN
• Weisheng Zhao, Beihang University, CN
• Cheng Zhuo, Zhejiang University, CN

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

---

Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Theocharis Theocharides, University of Cyprus, CY

Topics

A1 Power-efficient and Sustainable Computing

Chair: Baris Aksanli, San Diego State University, US

Co-Chair: Jungwook Choi, Hanyang University, KR

Topic Members

• Andreas Burg, EPFL-TCL, CH
• Thidapat (Tam) Chantem, Virginia Tech, US
• William Fornaciari, Politecnico di Milano - DEIB, IT
• Hai (Helen) Li, Duke University/TUM-IAS, US
• Saibal Mukhopadhyay, Georgia Institute of Technology, US
• semeen rehman, TU Wien, AT
• Amit Kumar Singh, University of Essex, GB

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Robotics and Industry 4.0

Chair: Ulrike Thomas, Technical University of Chemnitz, DE

Co-Chair: Federica Ferraguti, University of Modena and Reggio Emilia, IT

Topic Members

• Dirk Pesch, University College Cork, IE
• Anders Robertsson, Lund University, SE
• Matteo Saveriano, University of Innsbruck, AT

Bringing together robotics and machine learning concepts requires research and development efforts in interdisciplinary domains. With Industry 4.0 and its goal of adding utility value through data analytics and optimiztion, the Topic "Robotics and Industry 4.0" will remain at the core of the value creation chain during the next decade. The topic covers the field of robotics on topics from sensors and sensory interpretations to kinematics in motion planning, from distributed software concepts for data collection and analysis to large-scale machine learning algorithms, and sensor-based robot and machine control to safe human-robot interaction concepts.

A3 Automotive Systems and Smart Energy Systems

Chair: Sebastian Steinhorst, Technical University of Munich, DE

Co-Chair: David Boyle, Imperial College London, GB

Topic Members

• Dip Goswami, Eindhoven University of Technology, NL
• Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
• Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
• Massimo Poncino, Politecnico di Torino, IT
• Selma Saidi, Technische Universität Dortmund, DE
• Dirk Ziegenbein, Robert Bosch GmbH, DE

Design experiences for automotive systems, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits; MEMS; integrated sensors and transducers; RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; battery management and E/E architecture for electric vehicles; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalized Healthcare

Chair: Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR

Co-Chair: Daniela De Venuto, Politecnico di Bari, IT

Topic Members

• Amir Aminifar, Swiss Federal Institute of Technology Lausanne (EPFL), CH
• Guillermo Botella, Complutense University of Madrid, ES
• Eduardo de la Torre, Technical University of Madrid, ES
• Michele Magno, ETH Zurich, CH
• Dimitrios Tzovaras, CERTH/ITI, GR

Design experiences covering the use of body area networks, assistive and wearable technologies, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures

Chair: Lionel Torres, University of Montpellier, FR

Co-Chair: Bertrand Cambou, Northern Arizona University, US

Topic Members

• Aydin Aysu, North Carolina State University, US
• Lilian Bossuet, University of Lyon, FR
• Ray Cheung, City University of Hong Kong, HK
• Guillaume Duc, Télécom ParisTech, FR
• Basel Halak, Southampton University, GB
• Ajay Joshi, Boston University, US
• Michail Maniatakos, New York University Abu Dhabi, AE
• Cedric Marchand, Ecole centrale Lyon, FR
• Marcel Medwed, NXP Semiconductors Austria GmbH, AT
• Fernando Moraes, PUCRS University, BR
• Nicolas Sklavos, Computer Engineering & Informatics Department, University of Patras, GR
• Ingrid Verbauwhede, KU Leuven - COSIC, BE

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Learning Systems

Chair: Antonio Miele, Politecnico di Milano, IT

Co-Chair: Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR

Topic Members

• Woongki Baek, UNIST, KR
• Giovanni Beltrame, Polytechnique Montreal, CA
• Geoff Merrett, University of Southampton, GB
• Andy Pimentel, University of Amsterdam, NL

Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling, prediction/forecasting and control of self-adaptive systems; hybrid offline/online techniques for online decision-making; context-aware adaptation strategies and mechanisms; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems possibly based on machine learning techniques.

A7 Applications of Emerging Technologies

Chair: Robert Wille, Johannes Kepler University Linz, AT

Co-Chair: Michael Niemier, University of Notre Dame, US

Topic Members

• Armin Alaghi, University of Washington, US
• Kerem Camsari, Purdue University, US
• Deliang Fan, Arizona State University, US
• Bastien Giraud, CEA LETI, FR
• Jim Harkin, Ulster University, GB
• Li Jiang, Shanghai Jiao Tong University, CN
• Bing Li, Technical University of Munich, DE
• Yongpan Liu, Tsinghua University, CN
• Vasilis Pavlidis, University of Manchester, GB
• Martin Albrecht Trefzer, University of York, GB
• Shigeru Yamashita, Ritsumeikan University, JP
• Hailong Yao, Tsinghua University, CN
• Yang (Cindy) Yi, Virginia Tech, US

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers

Chair: Norbert Wehn, University of Kaiserslautern, DE

Co-Chair: Nicolas Ventroux, CEA, LIST, FR

Topic Members

• Mohamed Ibrahim, Intel Corporation, US
• Doris Keitel-Schulz, Infineon AG, DE
• Enrico Macii, Politecnico di Torino, IT
• Dionisios Pnevmatikatos, School of ECE, National Technical University of Athens & FORTH-ICS, GR

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

---

Track T: Test and Dependability

covers all test, design-for-test, reliability, and designfor-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Jaume Abella, BSC, ES

Topics

T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability

Chair: Arnaud Virazel, LIRMM, FR

Co-Chair: Bram Kruseman, NXP Semiconductors, NL

Topic Members

• Lorena Anghel, Grenoble-Alpes University, FR
• Rubio Antonio, Universitat Politècnica Catalunya (UPC), ES
• Seiji Kajihara, Kyushu Institute of Technology, JP
• Naghmeh Karimi, University of Maryland, Baltimore County, US
• Michele Portolan, TIMA, Univesité Grenoble Alpes, FR
• Christian Sauer, Cadence Design Systems, DE
• Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
• Hank Walker, Texas A&M University, US

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis

Chair: Patrick Girard, LIRMM / CNRS, FR

Co-Chair: Bernd Becker, University of Freiburg, DE

Topic Members

• Davide Appello, STMicroelectronics, IT
• Paolo Bernardi, Politecnico di Torino, IT
• Artur Jutman, Testonica Lab, EE
• Daniel Tille, Infineon Technologies, DE
• Jerzy Tyszer, Poznan University of Technology, PL
• Xiaoqing Wen, Kyushu Institute of Technology, JP

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Microarchitecture-Level Dependability

Chair: Ramon Canal, Universitat Politècnica de Catalunya, ES

Co-Chair: Stefano Di Carlo, Politecnico di Torino, IT

Topic Members

• Nikos Foutris, University of Manchester, GB
• Dimitris Gizopoulos, University of Athens, GR
• Brett Meyer, McGill University, CA
• Dimitris Nikolos, University of Patras, GR
• Ernesto Sanchez, Politecnico di Torino, IT
• Vasileios Tenentes, University of Ioannina, GR

Micro/architectures for fault-tolerant systems against permanent, transient and soft errors, including (but not limited to) processors, memories and accelerators; micro/architectural solutions for safety- and mission-critical systems; analysis and evaluation of reliability, availability and maintainability at micro/architectural level; hardware/software micro/architectural solutions for fault detection, recovery and aging mitigation. 

T4 System-Level Dependability

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY

Co-Chair: Georgios Karakonstantis, Queen's University Belfast, GB

Topic Members

• Luca Cassano, Politecnico di Milano, IT
• Goerschwin Fey, Hamburg University of Technology, DE
• Ernesto Sanchez, Politecnico di Torino, IT
• Rishad Shafik, Newcastle University, GB
• Vasileios Tenentes, University of Ioannina, GR

HW and SW solutions for dependability at system level; system level error/fault modeling; dependability analysis and evaluation; reliable and fail-safe system design; system-level on-line test and functional safety;  runtime system management for dependability; cross-layer solutions; application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Manuel Barragan, TIMA Laboratory, FR

Co-Chair: Mark Po-Hung Lin, National Chiao Tung University, TW

Topic Members

• Günhan Dündar, Bogazici University, TR
• Helmut Graeb, Technical University of Munich, DE
• Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
• Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR
• Shahriar Mirabbasi, University of British Columbia, CA
• Manoj Sachdev, University of Waterloo, CA
• Zheng Zhang, University of California, Santa Barbara, US

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT6 Design and Test of Secure Systems

Chair: Ilia Polian, University of Stuttgart, DE

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL

Topic Members

• Georg T. Becker, DSI Berlin, DE
• Anupam Chattopadhyay, Nanyang Technological University, SG
• Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
• Viktor Fischer, Hubert Curien Laboratory, Jean Monnet University, FR
• Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
• Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
• Mike Hutter, Cryptography Research Inc., US
• Elif Bilge Kavun, The University of Sheffield, GB
• Kerstin Lemke-Rust, Bonn-Rhein-Sieg University of Applied Sciences, DE
• Nele Mentens, KU Leuven, BE
• Stjepan Picek, TU Delft, NL
• Francesco Regazzoni, ALaRI, CH
• Kazuo Sakiyama, The University of Electro-Communications, JP
• Patrick Schaumont, Worcester Polytechnic Institute, US
• Matthias Schunter, Intel Labs, DE
• Johanna Sepúlveda, Airbus Defence and Space, DE
• Ruggero Susella, STMicroelectronics, IT
• Vincent Verneuil, NXP Semiconductors, DE

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation.

---

Track E: Embedded and Cyber-Physical Systems

is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.

Track Chair: Valeria Bertacco, University of Michigan, US

Topics

E1 Real-time and Dependable Systems

Chair: Dionisio de Niz, Carnegie Mellon University, US

Co-Chair: Liliana Cucu-Grosjean, INRIA, FR

Topic Members

• Marko Bertogna, University of Modena, IT
• Arvind Easwaran, Nanyang Technological University, SG
• Leandro Indrusiak, University of York, GB
• Hyoseung Kim, University of California, Riverside, US
• Giuseppe Lipari, Université de Lille 1, FR
• Martina Maggio, Lund University, SE
• Renato Mancuso, Boston University, US

Real-time performance modeling, analysis and empirical evaluation; Worst-case performance analysis techniques; Worst-case execution time analysis; Real-time schedulability of multicore systems; Mixed-Criticality scheduling; Real-time operating systems, microkernels and software; Use of hardware virtualization techniques in time critical applications, Power-aware real-time systems; Industrial case studies of real-time, networked and dependable systems; Adaptive real-time systems; Dependable systems including safety and criticality; Network control and QoS for embedded applications.

E2 Embedded Systems for Deep Learning

Chair: Tulika Mitra, National University of Singapore, SG

Co-Chair: Luca Carloni, Columbia University, US

Topic Members

• Giovanni Ansaloni, USI Lugano, CH
• David Atienza, École Polytechnique Fédérale de Lausanne (EPFL), CH
• Mladen Berekovic, TU Braunschweig, DE
• Michaela Blott, Xilinx, IE
• Luigi Carro, UFRGS, BR
• Mario R. Casu, Politecnico di Torino, Department of Electronics and Telecommunications, IT
• Bita Darvish Rouhani, Microsoft, US
• Anup Das, Drexel University, US
• Rolf Drechsler, University of Bremen/DFKI, DE
• Ujjwal Gupta, Intel Corporation, US
• Tushar Krishna, Georgia Institute of Technology, US
• Kyuho Lee, UNIST, KR
• Smail Niar, Université Polytechnique Hauts-de-France, FR
• Abbas Rahimi, ETH Zurich, CH
• Brandon Reagen, NYU/Facebook, US
• Sander Stuijk, Eindhoven University of Technology, NL
• Marian Verhelst, KU Leuven, BE
• Paul Whatmough, Arm Research, US
• Shouyi YIN, Tsinghua University, CN
• Xuan (Silvia) Zhang, Washington University in St. Louis, US

Hardware and architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; case studies of machine learning applications implemented on embedded systems.

E3 Model-Based Design, Verification and Security for Embedded Systems

Chair: Ylies Falcone, Univ. Grenoble Alpes, Inria, FR

Co-Chair: Todd Austin, University of Michigan, US

Topic Members

• Ezio Bartocci, TU Wien, AT
• Stéphanie Delaune, Univ Rennes, CNRS, IRISA, FR
• radu grosu, Vienna University of Technology, AT
• Mohamad Jaber, American University of Beirut, LB
• Laurent Mounier, VERIMAG / UGA, FR

Verification techniques for embedded ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as security, timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems. Security attacks, protection and analysis of embedded systems' hardware and software.

E4 Embedded Software Architecture, Compilers and Tool Chains

Chair: Sara Vinco, Politecnico di Torino, IT

Co-Chair: Borzoo Bonakdarpour, Iowa State University, US

Topic Members

• Nicola Bombieri, University of Verona, IT
• Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG
• Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), DE
• Ramy Medhat, University of Waterloo, CA
• Anca Molnos, CEA-Leti, Grenoble, FR
• Rodolfo Pellizzoni, University of Waterloo, CA
• Linh Thi Xuan Phan, University of Pennsylvania, US

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; Real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E5 Cyber-Physical Systems Design

Chair: Shiyan Hu, Michigan Technological University, US

Co-Chair: Davide Quaglia, University of Verona, IT

Topic Members

• Mohammad Al Faruque, University of California Irvine, US
• Wanli Chang, University of York, GB
• Robert de Simone, INRIA, FR
• Martin Horauer, University of Applied Sciences Technikum Wien, AT
• Wenchao Li, Boston University, US
• Roberto Passerone, University of Trento, IT

Modeling, design, verification, validation and optimization of Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things; safety and security aspects in CPS; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids); cognitive control for CPS; networked and switched control systems (e.g., control/architecture co-design and architecture-aware controller synthesis).

---