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DATE 2024 Technical Programme Committee

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Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Lukas Sekanina, Brno University of Technology, CZ

Topics

D1 System Specification and Modelling

Chair: Julio Medina, University of Cantabria, ES

Co-Chair: Matthias Jung, Universität Würzburg, DE

Topic Members

  • Rainer Doemer, EECS, UC Irvine, US
  • Sabine Glesner, Technische Universität Berlin, DE
  • Gianluca Palermo, Politecnico di Milano, IT
  • Laurence Pierre, Univ. Grenoble Alpes, TIMA Lab., FR
  • Todor Stefanov, Leiden University, NL
  • Min Zhang, East China Normal University, CN

Modelling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modelling; design and specification languages; application and workload models; models of computation and their analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modelling and analysis of functional and non-functional system properties; modelling of system adaptivity; time and performance modelling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level-Synthesis

Chair: Lana Josipovic, ETH Zurich, CH

Co-Chair: John Wickerson, Imperial College London, GB

Topic Members

  • Lars Bauer, Karlsruhe Institute of Technology, DE
  • Jovan Blanusa, IBM Research Europe - Zurich, CH
  • Benjamin Carrion Schaefer, The University of Texas at Dallas, US
  • Steven Derrien, University of Rennes 1/IRISA, FR
  • Zhenman Fang, Simon Fraser University, CA
  • Tong Geng, University of Rochester, US
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP
  • Chandan Karfa, Indian Institute of Technology Guwahati, IN
  • Luciano Lavagno, Politecnico di Torino, IT
  • Souradip Sarkar, Cadence Design Systems, DE
  • Linghao Song, UCLA, US
  • Cunxi Yu, University of Maryland, College Park, US
  • Wei Zhang, Hong Kong University of Science and Technology, HK
  • Peipei Zhou, University of Pittsburgh, US

High-level and system-level synthesis techniques; high-level languages for system and behavioural descriptions; system-level models for design and optimization; methods for HW-SW co-design and partitioning; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; control and data flow analysis; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures, including accelerator-rich architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems; high-level synthesis and system-level design for machine-learning applications.

D3 System Simulation and Validation

Chair: Monica Farkash, AMD, US

Co-Chair: Georg Weissenbacher, Vienna University of Technology, AT

Topic Members

  • Abdoulaye Gamatie, CNRS LIRMM / University of Montpellier, FR
  • Tara Ghasempouri, Department of Computer System, Tallinn University of Technology, Estonia, EE
  • Daniel Grosse, Johannes Kepler University Linz, AT
  • Roope Kaivola, Intel Corporation, US
  • Yusuke Kimura, Fujitsu Limited, JP
  • Ondrej Lengal, Brno University of Technology, CZ
  • Prabhat Mishra, University of Florida, US
  • Sander Stuijk, Eindhoven University of Technology, NL

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Helmut Graeb, Technical University of Munich, DE

Co-Chair: Rosa Rodríguez-Montañés, UPC, ES

Topic Members

  • Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
  • Mohamed Dessouky, Ain Shams University, EG
  • Maria Helena Fino, Nova University of Lisbon, PT
  • Marie-Minerve Louerat, CNRS and Sorbonne Universite, FR
  • Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT
  • Sule Ozev, ASU, US
  • Michael Pronath, MunEDA, DE
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR
  • Dani Tannir, Lebanese American University, LB

Analog, mixed-signal, MEMS system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; design for manufacturability, yield, reliability; self-healing and self-calibration; test generation; fault modelling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

  • Aydin Aysu, North Carolina State University, US
  • Scott Best, Rambus, Inc., US
  • Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ
  • Milos Drutarovsky, Technical University of Kosice, SK
  • Xiaolu Hou, Nanyang Technological University, SG
  • Sandhya Koteshwara, IBM T J Watson Research Center, US
  • Pierre-Yvan Liardet, eShard, FR
  • Guilherme Perin, Leiden University, NL
  • Svetla Petkova-Nikova, KU Leuven, BE
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Pascal Sasdrich, Ruhr-Universität Bochum, DE
  • Sujoy Sinha Roy, TU Graz, AT
  • Mirjana Stojilovic, EPFL, CH
  • Rei Ueno, Tohoku University, JP
  • Bohan Yang, Tsinghua University, CN
  • Fan Zhang, Zhejiang University; Key Laboratory of Blockchain and Cyberspace Governance of Zhejiang Province; Alibaba-Zhejiang University Joint Research Institute of Frontier Technologies;ZJU-Hangzhou Global Scientific and Technological Innovation Center; Jiaxing Res, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; MPC and homomorphic encryption; side-channel analysis (including modelling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG); AI methods in hardware security; security of hardware AI accelerators

DT6 Design and Test of Secure Systems

Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Co-Chair: Elif Bilge Kavun, University of Passau, DE

Topic Members

  • Anita Aghaie, Siemens AG, DE
  • Victor Arribas, Rambus Inc., NL
  • Josep Balasch, KU Leuven, BE
  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Elke De Mulder, Google, US
  • Giorgio Di Natale, TIMA, FR
  • Osnat Keren, Bar-Ilan University, IL
  • Yang Li, University of Electro-Communications, JP
  • Hadi Mardani Kamali, University of Florida, US
  • Ahmet Can Mert, Graz University of Technology, AT
  • Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
  • Martin Novotny, Czech Technical University in Prague, CZ
  • Siddika Ors Yalcin, Istanbul Technical University, TR
  • David Oswald, University of Birmingham, GB
  • Erdinc Ozturk, Intel, FR
  • Hammond Pearce, University of New South Wales, AU
  • Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH
  • Tobias Schneider, NXP Semiconductors, AT
  • Nicolas Sklavos, Computer Engineering and Informatics Department, University of Patras, GR
  • Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

D7 Formal Methods and Verification

Chair: Yakir Vizel, The Technion, IL

Co-Chair: Rolf Drechsler, University of Bremen/DFKI, DE

Topic Members

  • Erika Abraham, RWTH Aachen University, DE
  • Alessandro Cimatti, Fondazione Bruno Kessler, IT
  • Hadar Frenkel, CISPA Helmholtz Center for Information Security, DE
  • Sumana Ghosh, Indian Statistical Institute, IN
  • Shachar Itzhaky, Technion, IL
  • Alexander Ivrii, IBM, IL
  • Priyank Kalla, University of Utah, US
  • Stefano Quer, Politecnico di Torino, IT
  • Sven Reimer, Siemens EDA, DE

Formal models of software and hardware systems; formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis; formal methods in emerging technologies.

D8 Network-on-Chip and on-chip communication

Chair: Davide Zoni, Politecnico di Milano, IT

Co-Chair: Amlan Ganguly, Rochester Institute of Technology, US

Topic Members

  • Cristinel Ababei, Marquette University, US
  • Jose L. Abellan, University of Murcia, ES
  • Poona Bahrebar, Ghent University, US
  • Davide Bertozzi, University of Ferrara, IT
  • Cedric Killian, Universite Jean Monnet, FR
  • Alejandro Valero, Universidad de Zaragoza, ES
  • Qiaoyan Yu, University of New Hampshire, US

Architecture, design methodologies, modelling and simulation techniques for intra- and inter-chip interconnects, network-on-chip and on-chip communication infrastructure, including, but not limited to, topology, routers, interfaces, flow control, quality of service, security, reliability, design space exploration frameworks, on-chip communication specifications and programming models for communication-centric design. Contributions from specific applicative domains are welcomed such as interconnects for high-performance computing, in- or near-memory computing, machine-learning, artificial intelligence accelerators. The topic also covers the design of on-chip communication infrastructures with technological constraints (FPGA, interposer/chiplet for 2.5D, 3D, photonics, non-volatile memory…)

D9 Architectural and Microarchitectural Design

Chair: Leonidas Kosmidis, Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), ES

Co-Chair: Paula Herber, University of Münster, DE

Topic Members

  • Fitsum Assamnew Andargie, Addis Ababa University, ET
  • Eli Bozorgzadeh, Univ. of California, Irvine, US
  • Trevor E. Carlson, National University of Singapore, SG
  • Francisco J Cazorla, Barcelona Supercomputing Center, ES
  • Olivia Chen, Tokyo City University, JP
  • Izzat El Hajj, American University of Beirut, LB
  • Diana Goehringer, TU Dresden, DE
  • Lei Ju, School of Cyber Science and Technology, Shandong University, CN
  • Vasileios Karakostas, University of Athens, GR
  • Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
  • Rakesh Kumar, NTNU, Norway, NO
  • Sohan Lal, Technical University of Hamburg, DE
  • Guy Lemieux, The University of British Columbia, CA
  • Scott Miller, JPL, US
  • Miquel Pericas, Chalmers University of Technology, SE
  • Lucana Santos, European Space Agency, NL
  • Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN
  • Magnus Själander, Norwegian University of Science and Technology, NO
  • Mladen Slijepcevic, SiFive, FR
  • Chundong Wang, ShanghaiTech University, CN

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D10 Low-power, Energy-efficient and Thermal-aware Design

Chair: Masanori Hashimoto, Kyoto University, JP

Co-Chair: William Fornaciari, Politecnico di Milano - DEIB, IT

Topic Members

  • Sylvain Clerc, STMicroelectronics, FR
  • Tohru Ishihara, Nagoya University, JP
  • Rouwaida Kanj, Synopsys/American University of Beirut(on Leave), LB
  • Taeyoung Kim, Intel Corporation, US
  • Woojoo Lee, Chung-Ang University, KR
  • Vojtech Mrazek, Brno University of Technology, CZ
  • Donghwa Shin, Department of Intelligent Systems, Soongsil University, KR
  • Dimitrios Soudris, NTUA, GR
  • Sara Vinco, Politecnico di Torino, IT
  • Grace Li Zhang, TU Darmstadt, DE
  • Cheng Zhuo, Zhejiang University, CN

Theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behaviour. These can be applied to a full range of applications, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centres and cloud computing). Topics of interest include: thermal/power monitors and knobs at circuit level; hardware/software cross-layer optimizations, with emphasis on power modelling and optimization; temperature modelling and prediction; thermal-power-aware optimization; energy-aware design, battery-aware design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems.

D11 Approximate Computing

Chair: Daniel Menard, INSA Rennes, FR

Co-Chair: Anca Molnos, CEA-LIST, FR

Topic Members

  • Mario Barbareschi, University of Naples Federico II, IT
  • Nikolaos Bellas, University of Thessaly, GR
  • Andreas Gerstlauer, The University of Texas at Austin, US
  • Honglan Jiang, Shanghai Jiao Tong University, CN
  • Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
  • Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
  • Veljko Pejovic, University of Ljubljana, SI
  • Alessandro Savino, Politecnico di Torino, IT
  • Florian Scheidegger, IBM Research GmbH, CH
  • Zdenek Vasicek, Brno University of Technology, CZ
  • Lan Wei, University of Waterloo, CA

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; finite precision arithmetic, inexact operators; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking; design techniques for stochastic computing.

D12 Reconfigurable Systems

Chair: Christos Bouganis, Imperial College London, GB

Co-Chair: Dionisios Pnevmatikatos, National Technical University of Athens & ICCS, GR

Topic Members

  • Michaela Blott, Xilinx, IE
  • Catalin Bogdan Ciobanu, Transilvania University of Brasov, RO
  • Jan Korenek, Brno University of Technology, CZ
  • Xavier Martorell, Universitat Politècnica de Catalunya, ES
  • Bogdan Pasca, Intel, FR
  • Stefania Perri, University of Calabria - DIMEG, IT
  • Laura Pozzi, USI Lugano, CH
  • Stylianos Venieris, Samsung AI, GB
  • Sotirios Xydis, National Technical University of Athens, GR

Reconfigurable computing platforms and architectures; heterogeneous, run-time reconfigurable platforms; reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data centre and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D13 Logical Analysis and Design

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE

Topic Members

  • Valentina Ciriani, Universita' degli Studi di Milano, IT
  • Petr Fišer, Czech Technical University in Prague, FIT, CZ
  • Masahiro Fujita, University of Tokyo, JP
  • Rajeev Murgai, Synopsys India Pvt. Ltd., IN
  • Weikang Qian, Shanghai Jiao Tong University, CN
  • Andre Reis, UFRGS, BR
  • Eleonora Testa, Synopsys Inc., US

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; FPGA synthesis; arithmetic circuits; logic ECO (engineering change order); logic synthesis utilizing AI/ML techniques; interaction between logic synthesis and physical design.

D14 Physical Analysis and Design

Chair: Laleh Behjat, University of Calgary, CA

Co-Chair: Shao-Yun Fang, National Taiwan University of Science and Technology, TW

Topic Members

  • Shaahin Angizi, New Jersey Institute of Technology, US
  • Alper Demir, Koc University, TR
  • Aysa Fakheri Tabrizi, University of Calgary, CA
  • Amin Farshidi, Cadence Design Systems, US
  • Matthias Fuegger, CNRS & LMF, ENS Paris-Saclay, FR
  • Patrick Groeneveld, DAC, US
  • Nima Karimpour Darav, Xilinx, Inc (AMD)., CA
  • Cristina Meinhardt, UFSC, BR
  • Renan Netto, Federal University of Santa Catarina, BR
  • Vojin Oklobdzija, University of California Davis, US
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
  • Mehmet Yildiz, Cadence Design Systems, US
  • Wenjian Yu, Tsinghua University, CN

Statistical timing analysis and closure; asynchronous and mixed synchronous/asynchronous circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modelling, behavioural and reduced order modelling; modelling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D15 Emerging Design Technologies for Future Computing

Chair: Alessio Spessot, Imec, BE

Co-Chair: Vihar Georgiev, University of Glasgow, GB

Topic Members

  • Ari Alastalo, VTT, FI
  • Mohamed M. Sabry Aly, Nanyang Technological University, SG
  • Salvatore Amoroso, Synopsys Inc, GB
  • Veeresh Deshpande, IIT Bombay, IN
  • Maria Loreto Mateu Saez, Fraunhofer IIS, DE
  • Pierpaolo Palestri, DPIA, University of Udine, IT
  • Victor Sverdlov, CDL NovoMemLog IuE TUWien, AT
  • Aida Todri-Sanial, Eindhoven University of Technology, NL
  • Tony Wu, Facebook, US

Modelling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modelling and design space exploration).

D16 Emerging Design Technologies for Future Memories

Chair: Rajendra Bishnoi, Delft University of Technology,, NL

Co-Chair: Jean-Philippe Noel, CEA, FR

Topic Members

  • Harshit Agarwal, IIT Jodhpur, IN
  • Charles Augustine, Intel Circuit Research Lab, US
  • Deliang Fan, Johns Hopkins University, US
  • Andre Guntoro, Bosch, DE
  • Daniele Ielmini, Poltecnico di Milano, IT
  • Jongsun Park, Korea University, KR
  • Guillaume Prenat, Spintec, FR
  • Fabrizio Riente, Politecnico di Torino, IT
  • Joachim Rodrigues, Lund University, SE
  • Sonal Shreya, Aarhus University, DK
  • William Simon, IBM, CH
  • Stefan Slesazeck, NaMLab gGmbH, DE
  • Xueyan Wang, Beihang University, CN
  • Tianyao Xiao, Sandia National Laboratories, US
  • Amirreza Yousefzadeh, IMEC, NL

Modelling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, Computation-in-memory, neuromorphic computing, DNN accelerator, near memory, 3D-integration, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.


Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Alberto Bosio, University of Lyon, FR

Topics

A1 Power-efficient and Sustainable Computing

Chair: Semeen Rehman, TU Wien, AT

Co-Chair: David Novo, CNRS, LIRMM, University of Montpellier, FR

Topic Members

  • David Castells-Rufas, Universitat Autònoma de Barcelona, ES
  • Kuan-Hsun Chen, University of Twente, NL
  • Yehan Ma, Shanghai Jiao Tong University, CN
  • Thijs Metsch, Intel, DE
  • Orlando Moreira, GrAI Matter Labs, NL
  • Mahdi Nikdast, Colorado State University, US
  • Anuj Pathania, University of Amsterdam, NL
  • Qinru Qiu, Syracuse University, US
  • Ourania Spantidi, Eastern Michigan University, US
  • Arun Subramaniyan, Illumina Inc., US
  • Nishil Talati, University of Michigan, US
  • Ana Lucia Varbanescu, University of Amsterdam, NL
  • Swagath Venkataramani, IBM T. J. Watson Research Center, US
  • Georgios Zervakis, University of Patras, GR

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centres, and cloud systems). Topics of interest include: hardware and software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; approximate arithmetic HW designs; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-centre management strategies; smart maintenance for embedded devices; SW/OS-level implementations in real systems and data centres; energy-efficient big data management; data centres powered by renewable energy sources and data centres in smart grids; simulation methodologies, open-source tools, frameworks, data sets.

A2 Smart Cities, Internet of Everything, Industry 4.0

Chair: Graziano Pravadelli, University of Verona, IT

Co-Chair: Christos Kyrkou, KIOS CoE, University of Cyprus, CY

Topic Members

  • UmaMaheswari Devi, IBM Research - India, IN
  • Franco Fummi, University of Verona, IT
  • Srinivas Katkoori, University of South Florida, US
  • Sefki Kolozali, University of Essex, GB
  • Tiziana Margaria, University of Limerick and Lero, IE

Applications, design experiences and real-life implementations of theory, design, construction, manufacture and/or end-use of mass market electronics, systems, software, and services for smart cities, smart industries, smart homes, smart consumer electronics, Internet of Things (IoT), and Internet-of-Everything (IoE). Topics of interest include: smart and sustainable mobility; smart transportation; smart economy; smart environment (including street cleaning, water management, water supply, air quality monitoring, disposal facilities, lighting, etc.). Other topics of interest are the verticals of IoT, IoE, Industry 4.0, Digital Twins, Virtualization, Metaverse, Consumer Electronics, smart home, and smart cities including: smart wearables; robotic systems for smart cities and smart homes; smart sensors; blockchain technology; video technology; audio technology; white goods; home care products; mobile communications; gaming; air care products; home automation and networking devices; home theatre; digital imaging; in-vehicle technology; cable & satellite technology; home security; domestic lighting; human interface; consumer storage technology; AI/ML techniques for these smart systems; energy-management techniques for these systems; security-privacy techniques for these systems.

A3 Automotive Systems and Smart Energy Systems

Chair: Michele Magno, ETH Zurich, CH

Co-Chair: Lulu Chan, NXP Semiconductors, NL

Topic Members

  • Donkyu Baek, Chungbuk National University, KR
  • Domenico Balsamo, Newcastle University, GB
  • Davide Brunelli, University of Trento, IT
  • Seonyeong Heo, Kyung Hee University, KR
  • Philipp Mundhenk, Robert Bosch GmbH, DE

Design experiences for automotive systems, autonomous robotics and UAV, energy-neutral embedded systems, smart energy systems (from uW to microgrid) and energy efficient smart sensors, and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits, smart energy systems, and embedded platforms with particular interest in energy efficient intelligent system; MEMS; integrated sensors and transducers; machine learning on microcontrollers and low power processors, RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; smart autonomous algorithms and systems for electric vehicles and unmanned aerial vehicle; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalised Healthcare

Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT

Co-Chair: Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR

Topic Members

  • Simone Benatti, University of Bologna, IT
  • Andrea Cossettini, ETH Zurich, CH
  • Amir M. Rahmani, University of California, Irvine, US

Design experiences covering the use of body area networks, assistive and wearable technologies, robot-assisted living and healthcare, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures

Chair: Johanna Sepúlveda, Airbus Defence and Space, DE

Co-Chair: Cedric Marchand, Ecole centrale Lyon, FR

Topic Members

  • M. Khurram Bhatti, Information Technology University (ITU), PK
  • Noemie Boher, Intrinsic-ID, NL
  • Luca Cassano, Politecnico di Milano, IT
  • Ray Cheung, City University of Hong Kong, HK
  • Julien Francq, Naval Group, FR
  • Bogdan Groza, Politehnica Unviersity Timisoara, RO
  • Basel Halak, Southampton University, GB
  • Matthias Hiller, Fraunhofer AISEC, DE
  • Naghmeh Karimi, University of Maryland Baltimore County, US
  • Michail Maniatakos, New York University Abu Dhabi, AE
  • Sarah McCarthy, University of Waterloo, CA
  • Maria Méndez Real, IETR UMR CNRS 6164 Nantes Université, FR
  • Michael Pehl, Technical University of Munich, DE
  • Amin Rezaei, California State University, Long Beach, US
  • Jo Vliegen, ES&S, imec-COSIC, ESAT, KU Leuven, BE

Secure systems, circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; hardware/software implementations architectures for post quantum embedded cryptography (e.g., post-quantum, lightweight, homomorphic); emerging technologies for secure systems, circuits and architectures; novel architectures for embedded cryptography; demonstrations of fault or other physical attacks (e.g., fault, side-channel) and countermeasures; embedded processors or co-processors for security; protection of off-chip memories, and Network-on-Chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Context-aware Systems

Chair: Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR

Co-Chair: Heba Khdr, Karlsruhe Institute of Technology (KIT), DE

Topic Members

  • Antonio Miele, Politecnico di Milano, IT
  • Daniel Mueller-Gritschneder, Technical University of Munich, DE
  • Jose Nunez-Yanez, Linkoping University, SE
  • Behnaz Pourmohseni, Robert Bosch GmbH, DE
  • Amit Kumar Singh, University of Essex, GB
  • Lucas Wanner, Unicamp, BR
  • Stefan Wildermann, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE

Self-adaptive, learning and context-aware systems for run-time decision-making. This includes systems and algorithms targeting various optimization goals such as compute performance, energy/power-efficiency, reliability, temperature, aging, or quality. It also considers various architectural platforms, such as high-performance compute nodes, power-constrained IoT/edge computing technologies, reconfigurable systems and heterogeneous/collaborative platforms. Such approaches may utilise machine learning techniques to achieve the desired behaviour. The relationship to computer and/or electronic system design must be clearly apparent in all submissions. Topics of interests include, but are not limited to: adaptive strategies for run-time resource management; prediction/forecasting and control of self-adaptive systems (for example using machine learning techniques for offline and/or online modelling); adaptive systems and/or algorithms which can adapt their operation based on available resources, external contexts, etc; application of diverse data mining, modelling and optimization techniques for adaptive systems (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems.

A7 Applications of Emerging Technologies

Chair: Mariagrazia Graziano, Politecnico di Torino, IT

Co-Chair: Sébastien Le Beux, Concordia University, CA

Topic Members

  • Guillermo Botella, Complutense University of Madrid, ES
  • Yuanqing Cheng, Beihang University, CN
  • Giovanni Amedeo Cirillo, STMicroelectronics, IT
  • Florin Ciubotaru, Imec, BE
  • Panagiotis Dimitrakis, NCSR Demokritos, GR
  • Andreas Fuhrer Janett, IBM Research, CH
  • Georgi Gaydadjiev, Delft University of Technology / Imperial College, NL
  • M. Hassan Najafi, University of Louisiana at Lafayette, US
  • Luca Pezzarossa, Technical University of Denmark, DK
  • Paulina Powroznik, Silesian University of Technology, PL
  • Azzurra Pulimeno, Camlin Group, IT
  • Frank Sill Torres, German Aerospace Center, DE
  • Himanshu Thapliyal, University of Tennessee, US
  • Elena Ioana Vatajelu, TIMA, FR
  • Shigeru Yamashita, Ritsumeikan University, JP
  • Xunzhao Yin, Zhejiang University, CN

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers

Chair: Michelangelo Grosso, STMicroelectronics s.r.l., IT

Co-Chair: Daniel Tille, Infineon Technologies, DE

Topic Members

  • Anthony Coyette, Onsemi, BE
  • Mohamed Ibrahim, Georgia Institute of Technology, US
  • Ciganda Lyl, Facultad de Ingeniería, Universidad de la República, UY
  • Wenjing Rao, University of Illinois at Chicago, US

Short 2-pages industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


Track T: Test and Dependability

covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Matteo Sonza Reorda, Politecnico di Torino, IT

Topics

T1 Modelling and Mitigation of Defects, Faults, Variability, and Reliability

Chair: Leticia Maria Bolzani Poehls, RWTH Aachen University, DE

Co-Chair: Mottaqiallah Taouil, Delft University of Technology, NL

Topic Members

  • Hussam Amrouch, Technical University of Munich (TUM), DE
  • Lorena Anghel, Grenoble-Alpes University, Grenoble, France, FR
  • Davide Appello, Technoprobe, IT
  • Daniel Arumi, UPC, ES
  • Sarah Azimi, Politecnico di Torino, IT
  • Riccardo Cantoro, Politecnico di Torino, IT
  • Bram Kruseman, NXP Semiconductors, NL
  • Soumya Mittal, Qualcomm India Pvt Ltd, IN
  • Arnaud Virazel, LIRMM, FR

Identification, characterization, and modelling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability assessment and modelling at device, circuit, or system level; process yield modelling and enhancement; design-for-manufacturability, design-for-yield and design-for-reliability; noise and uncertainty modelling at device or circuit level; modelling and mitigation of physical sources of faults and errors such as process, voltage, temperature and temporal variations at device or circuit level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY

Co-Chair: Grzegorz Mrugalski, Siemens EDA, PL

Topic Members

  • Paolo Bernardi, Politecnico di Torino, IT
  • Jennifer Dworak, Southern Methodist University, US
  • Sybille Hellebrand, University of Paderborn, DE
  • Maksim Jenihhin, Tallinn University of Technology, EE
  • Chrysovalantis Kavousianos, Department of Computer Science and Engineering, University of Ioannina, GR
  • Erik Larsson, Lund University, SE
  • Teresa McLaurin, ARM, US
  • Jerzy Tyszer, Poznan University of Technology, PL

Test generation and test architectures for AI/ML, microprocessors, accelerators, SoC, FPGAs, memories, NoC, approximate solutions and 3D ICs; test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Dependability and System-Level Test

Chair: Dimitris Gizopoulos, University of Athens, GR

Co-Chair: Osman Unsal, Barcelona supercomputing center, ES

Topic Members

  • Jyotika Athavale, Synopsys, US
  • Stefano Di Carlo, Politecnico di Torino, IT
  • Harish Dixit, Meta Platforms Inc., US
  • Sudhanva Gurumurthi, Advanced Micro Devices, Inc (AMD), US
  • Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
  • Jingwen Leng, Shanghai Jiao Tong University, CN

Dependability evaluation and improvement solutions crossing all layers of the system’s stack including but not limited to: microarchitecture-level, architecture-level, and system-level error/fault modelling; cross-layer dependability analysis and evaluation; reliable and fail-safe architectures and systems design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Helmut Graeb, Technical University of Munich, DE

Co-Chair: Rosa Rodríguez-Montañés, UPC, ES

Topic Members

  • Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
  • Mohamed Dessouky, Ain Shams University, EG
  • Maria Helena Fino, Nova University of Lisbon, PT
  • Marie-Minerve Louerat, CNRS and Sorbonne Universite, FR
  • Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT
  • Sule Ozev, ASU, US
  • Michael Pronath, MunEDA, DE
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR
  • Dani Tannir, Lebanese American University, LB

Analog, mixed-signal, MEMS system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; design for manufacturability, yield, reliability; self-healing and self-calibration; test generation; fault modelling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

  • Aydin Aysu, North Carolina State University, US
  • Scott Best, Rambus, Inc., US
  • Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ
  • Milos Drutarovsky, Technical University of Kosice, SK
  • Xiaolu Hou, Nanyang Technological University, SG
  • Sandhya Koteshwara, IBM T J Watson Research Center, US
  • Pierre-Yvan Liardet, eShard, FR
  • Guilherme Perin, Leiden University, NL
  • Svetla Petkova-Nikova, KU Leuven, BE
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Pascal Sasdrich, Ruhr-Universität Bochum, DE
  • Sujoy Sinha Roy, TU Graz, AT
  • Mirjana Stojilovic, EPFL, CH
  • Rei Ueno, Tohoku University, JP
  • Bohan Yang, Tsinghua University, CN
  • Fan Zhang, Zhejiang University; Key Laboratory of Blockchain and Cyberspace Governance of Zhejiang Province; Alibaba-Zhejiang University Joint Research Institute of Frontier Technologies;ZJU-Hangzhou Global Scientific and Technological Innovation Center; Jiaxing Res, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; MPC and homomorphic encryption; side-channel analysis (including modelling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG); AI methods in hardware security; security of hardware AI accelerators

DT6 Design and Test of Secure Systems

Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Co-Chair: Elif Bilge Kavun, University of Passau, DE

Topic Members

  • Anita Aghaie, Siemens AG, DE
  • Victor Arribas, Rambus Inc., NL
  • Josep Balasch, KU Leuven, BE
  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Elke De Mulder, Google, US
  • Giorgio Di Natale, TIMA, FR
  • Osnat Keren, Bar-Ilan University, IL
  • Yang Li, University of Electro-Communications, JP
  • Hadi Mardani Kamali, University of Florida, US
  • Ahmet Can Mert, Graz University of Technology, AT
  • Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
  • Martin Novotny, Czech Technical University in Prague, CZ
  • Siddika Ors Yalcin, Istanbul Technical University, TR
  • David Oswald, University of Birmingham, GB
  • Erdinc Ozturk, Intel, FR
  • Hammond Pearce, University of New South Wales, AU
  • Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH
  • Tobias Schneider, NXP Semiconductors, AT
  • Nicolas Sklavos, Computer Engineering and Informatics Department, University of Patras, GR
  • Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.


Track E: Embedded Systems Design

is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems, and dependable systems. Emphasis is, also, on model-based design and verification, embedded software platforms, software compilation and integration for these systems.

Track Chair: Liliana Cucu, Inria, FR

Topics

E1 Embedded Software Architecture, Compilers and Tool Chains

Chair: Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG

Co-Chair: Ahmed Rezine, Linköping University, SE

Topic Members

  • Urbi Chatterjee, Indian Institute of Technology Kanpur, IN
  • Soumyajit Dey, IIT Kharagpur, IN
  • Timo Hönig, Ruhr University Bochum, DE
  • Michele Lora, University of Verona, IT
  • Hiren Patel, University of Waterloo, CA
  • Linh Thi Xuan Phan, University of Pennsylvania, US
  • Sara Royuela, Barcelona Supercomputing Center, ES
  • Soheil Samii, Linköping University, SE
  • Yi Wang, Shenzhen University, CN
  • Chen Yu-Fang, Academia Sinica, TW

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E2 Real-time, Dependable and Privacy-Enhanced Systems

Chair: Mitra Nasri, Eindhoven University of Technology, NL

Co-Chair: Jing Li, New Jersey Institute of Technology, US

Topic Members

  • Yasmina ABDEDDAIM, Univ Gustave Eiffel, CNRS, LIGM, FR
  • Mohammad Ashjaei, Mälardalen University, SE
  • Andrea Bastoni, TUM, DE
  • Matthias Becker, KTH Royal Institute of Technology, SE
  • Gedare Bloom, University of Colorado Colorado Springs, US
  • Emmanuel Grolleau, LIAS, ISAE-ENSMA, Universite de Poitiers, FR
  • Nan Guan, City University of Hong Kong, HK
  • Sena Hounsinou, Metro State University, US
  • Zhe Jiang, University of Cambridge, GB
  • Federico Reghenzani, Politecnico di Milano, IT
  • Lei Yang, George Mason University, US

Real-time performance modelling, analysis and empirical evaluation; worst-case performance analysis techniques; WCET analyses, real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; security attack protection and analysis of embedded systems' hardware and software; privacy-enhanced and safety-enhanced systems; network control and QoS for embedded applications.

E3 Machine Learning Solutions for Embedded and Cyber-Physical Systems

Chair: Mario R. Casu, Politecnico di Torino, Department of Electronics and Telecommunications, IT

Co-Chair: Francesco Conti, University of Bologna, IT

Topic Members

  • Elnaz Ansari, Meta, US
  • Mladen Berekovic, Universität zu Lübeck, DE
  • Irem Boybat, IBM Research Europe - Zurich, CH
  • Anup Das, Drexel University, US
  • Kaoutar El Maghraoui, IBM, US
  • Maryam Hemmati, University of Auckland, NZ
  • Daniele Jahier Pagliari, Politecnico di Torino, IT
  • Axel Jantsch, TU Wien, AT
  • Jung-Eun Kim, Assistant professor, Computer Science, North Carolina State University, US
  • Hyoukjun Kwon, University of California, Irvine, US
  • Charles Mackin, IBM Research, US
  • Andres Otero, Universidad Politecnica de Madrid, ES
  • Hamza Ouarnoughi, INSA Hauts-de-France, FR
  • Işıl Öz, Izmir Institute of Technology, TR
  • Lirong Zheng, Fudan University, CN
  • Guanwen Zhong, AMD Research and Advanced Development (RAD), SG

Hardware architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning solutions; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; case studies of machine learning applications implemented on embedded systems and cyber physical systems.

E4 Design Methodologies for Machine Learning Architectures

Chair: Smail Niar, INSA Hauts-de-France and CNRS, FR

Co-Chair: Priyadarshini Panda, Yale University, US

Topic Members

  • Giovanni Ansaloni, EPFL, CH
  • Riyadh Baghdadi, New York University Abu Dhabi, AE
  • Prabal Basu, Senior Principal Software Engineer, Cadence Design Systems, US
  • Hadjer Benmeziane, IBM Research, CH
  • José Cano, University of Glasgow, GB
  • Henk Corporaal, TU/e (Eindhoven University of Technology), NL
  • Jana Doppa, Washington State University, US
  • Jan Moritz Joseph, RWTH Aachen University, DE
  • Sheng-Chun Kao, Georgia Institute of Technology, US
  • Souvik Kundu, Intel Labs, US
  • Steven Latre, University of Antwerp - IMEC, BE
  • Jinho Lee, Seoul National University, KR
  • Huichu Liu, Facebook Inc., US
  • Maria Mushtaq, Telecom Paris, FR
  • Umit Ogras, University of Wisconsin - Madison, US
  • Ozcan Ozturk, Bilkent University, TR
  • Mazen Saghir, American University of Beirut, LB
  • Jae-sun Seo, Cornell Tech, US
  • Manan Suri, IIT-Delhi, IN
  • Marian Verhelst, KU Leuven, BE

Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures; specializations, and resource-efficient optimizations for machine learning architectures; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; in-memory and near-memory architectures design for ML; hyperdimensional computing architectures and ML applications; quantum computing for ML; co-design space exploration for ML applications.

E5 Design Modelling and Verification for Embedded and Cyber-Physical Systems

Chair: Roberto Passerone, University of Trento, IT

Co-Chair: Patricia Derler, PARC, US

Topic Members

  • Luis Almeida, University of Porto, PT
  • Susanne Graf, University Grenoble Alpes, CNRS, FR
  • Chadlia Jerad, University of Manouba, TN
  • Hokeun Kim, Arizona State University, US
  • Chung-Wei Lin, National Taiwan University, TW
  • Ahlem Mifdaoui, University of Toulouse- ISAE, FR

Modelling, design, verification, validation and optimization of embedded systems and Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things as well as software-intensive CPS; modelling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, quality-of-service, safety and reliability; theories, languages and tools supporting model-based design flows covering software, control and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining and CPS, autonomous CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behaviour in smart grids).