Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organising Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organising Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

DATE 2021 Technical Programme Committee

TPC chairs and members can update their personnel data like affiliation in SoftConf only. Please update your data in your SoftConf Profile. This page is updated automatically each full hour.

Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Ian O'Connor, École Centrale de Lyon, FR

Topics

D1 System Specification and Modeling

Chair: Frederic Mallet, Universite Cote d'Azur, FR

Co-Chair: Gianluca Palermo, Politecnico di Milano, IT

Topic Members

  • Abdoulaye Gamatie, CNRS LIRMM / University of Montpellier, FR
  • Sabine Glesner, Technische Universität Berlin, DE
  • Jorn Janneck, Lund University, SE
  • Matthias Jung, Fraunhofer IESE, DE
  • Pierluigi Nuzzo, University of Southern California, US
  • Min Zhang, East China Normal University, CN

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; modeling of system adaptivity; time and performance modeling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level Synthesis

Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR

Co-Chair: Christian Pilato, Politecnico di Milano, IT

Topic Members

  • Lars Bauer, Karlsruhe Institute of Technology, DE
  • Alberto Antonio Del Barrio Garcia, Complutense University of Madrid, ES
  • Dionysios Diamantopoulos, IBM Research, CH
  • Soonhoi Ha, Seoul National University, KR
  • Dirk Koch, University of Manchester, GB
  • Luciano Lavagno, Politecnico di Torino, IT
  • Razvan Nane, TU Delft, NL
  • David Novo, CNRS, LIRMM, University of Montpellier, FR
  • Preeti Ranjan Panda, IIT Delhi, IN
  • Sudeep Pasricha, Colorado State University, US
  • Donatella Sciuto, Politecnico di Milano, IT
  • Wei Zhang, Hong Kong University of Science and Technology, HK
  • Zhiru Zhang, Cornell University, US

High-level and system-level synthesis techniques; high-level languages for system and behavioral descriptions; system-level models for design and optimization; methods for HW-SW co-design and partitioning; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; control and data flow analysis; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures, including accelerator-rich architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems; high-level synthesis and system-level design for machine-learning applications.

D3 System Simulation and Validation

Chair: Avi Ziv, IBM Research - Haifa, IL

Co-Chair: Katell Morin-Allory, TIMA Laboratory, FR

Topic Members

  • Mingsong Chen, East China Normal University, CN
  • Monica Farkash, AMD, US
  • Masahiro Fujita, University of Tokyo, JP
  • Daniel Grosse, Johannes Kepler University Linz, AT
  • Shobha Vasudevan, UIUC, US

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Manuel Barragan, TIMA Laboratory, FR

Co-Chair: Mark Po-Hung Lin, National Chiao Tung University, TW

Topic Members

  • Davide Appello, STMicroelectronics, IT
  • Florence AZAIS, Univ. Montpellier, CNRS, LIRMM, FR
  • Günhan Dündar, Bogazici University, TR
  • Helmut Graeb, Technical University of Munich, DE
  • Jiun-Lang Huang, National Taiwan University, TW
  • Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
  • Shahriar Mirabbasi, University of British Columbia, CA
  • Sule Ozev, ASU, US
  • Manoj Sachdev, University of Waterloo, CA
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Lejla Batina, Radboud University Nijmegen, NL

Co-Chair: Nele Mentens, KU Leuven, BE

Topic Members

  • Ileana Buhan, Radboud University, NL
  • Fatemeh Ganji, Worcester Polytechnic Institute, US
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
  • Mike Hutter, Cryptography Research Inc., US
  • Kostas Papagiannopoulos, Radboud University Nijmegen, NL
  • Stjepan Picek, TU Delft, NL
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Kazuo Sakiyama, The University of Electro-Communications, JP
  • Johanna Sepúlveda, Airbus Defence and Space, DE
  • Bohan Yang, Tsinghua University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modeling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Marcel Medwed, NXP Semiconductors Austria GmbH, AT

Topic Members

  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
  • Giorgio Di Natale, TIMA, FR
  • Junfeng Fan, Open Security Research, Inc., CN
  • Samaneh Ghandali, Google, US
  • Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
  • Johann Heyszl, Fraunhofer AISEC, DE
  • Elif Bilge Kavun, University of Passau, DE
  • Osnat Keren, Bar-Ilan University, IL
  • Patrick Schaumont, Worcester Polytechnic Institute, US
  • Tobias Schneider, NXP Semiconductors, AT
  • Ruggero Susella, STMicroelectronics, IT
  • Russ Tessier, University of Massachusetts, US
  • Yuval Yarom, The University of Adelaide and Data61, AU

Design-for-trust (secure design methods); test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; design and design automation (for HW tampering attacks and protection, for countermeasures, for side-channel protection verification, for fault protection verification); microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); machine learning for the above topics; adversarial attacks on machine learning.

D7 Formal Methods and Verification

Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT

Co-Chair: Anna Slobodova, Centaur Technology, US

Topic Members

  • Jade Alglave, Arm and University College London, GB
  • Barbara Jobstmann, EPFL and Jasper Design Automation, CH
  • Stefano Quer, Politecnico di Torino, IT
  • Heinz Riener, EPFL, CH
  • Yakir Vizel, The Technion, IL
  • Georg Weissenbacher, Vienna University of Technology, AT

Formal models of software and hardware systems; formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis; formal methods in emerging technologies.

D8 Network on Chip and Communication-Centric Design

Chair: Romain Lemaire, CEA-Leti, FR

Co-Chair: Li-Shiuan Peh, Professor, National University of Singapore, SG

Topic Members

  • Chia-Hsin Chen, Marvell Semiconductor, Inc, US
  • Daniel Chillet, University of Rennes 1, FR
  • Jana Doppa, Washington State University, US
  • Kees Goossens, Eindhoven university of technology, NL
  • Paul Gratz, Texas A&M University, US
  • Ajay Joshi, Boston University, US
  • Sébastien Le Beux, Concordia University, CA
  • Fernando Moraes, PUCRS University, BR
  • Vassos Soteriou, Cyprus University of Technology, CY
  • Davide Zoni, Politecnico di Milano, IT

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, in-memory computing, machine learning, etc.); design of interconnects using alternative/emerging technologies (photonics, 2.5D/3D, quantum computing, etc.).

D9 Architectural and Microarchitectural Design

Chair: Olivier Sentieys, INRIA, FR

Co-Chair: Jeronimo Castrillon, TU Dresden, DE

Topic Members

  • Caroline Collange, Inria, FR
  • Pedro Diniz, Univ. Southern California, US
  • Zhenman Fang, Simon Fraser University, CA
  • Paula Herber, University of Münster, DE
  • Christophe Jego, IMS Labo, Bordeaux INP, FR
  • Lei Ju, School of Cyber Science and Technology, Shandong University, CN
  • Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
  • Leonidas Kosmidis, Barcelona Supercomputing Center (BSC), ES
  • Guy Lemieux, The University of British Columbia, CA
  • Gokhan Memik, Northwestern University, US
  • Miquel Pericas, Chalmers University of Technology, SE
  • Tanguy Risset, Univ Lyon, INSA Lyon, Inria, CITI, FR
  • Cristina Silvano, Politecnico di Milano, IT
  • Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN
  • Magnus Själander, Norwegian University of Science and Technology, NO

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D10 Low-power, Energy-efficient and Thermal-aware Design

Chair: Andrea Calimera, Politecnico di Torino, IT

Co-Chair: Pascal Vivet, CEA-Leti, FR

Topic Members

  • Nadine Azemard, LIRMM, FR
  • Laleh Behjat, University of Calgary, CA
  • Sylvain Clerc, STMicroelectronics, FR
  • Shao-Yun Fang, National Taiwan University of Science and Technology, TW
  • Masanori Hashimoto, Osaka University, JP
  • Alberto Macii, Politecnico di Torino, IT
  • Umit Ogras, Arizona State University, US
  • Davide Rossi, University Of Bologna, IT
  • Rene van Leuken, Delft University of Technology, NL

Theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behavior. These can be applied to a full range of applications, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centers and cloud computing). Topics of interest include: thermal/power monitors and knobs at circuit level; hardware/software cross-layer optimizations, with emphasis on power modeling and optimization; temperature modeling and prediction; thermal-power-aware optimization; energy-aware design, battery-aware design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems.

D11 Approximate Computing

Chair: Lukas Sekanina, Brno University of Technology, CZ

Co-Chair: Jie Han, University of Alberta, CA

Topic Members

  • Nikolaos Bellas, University of Thessaly, GR
  • Benjamin Carrion Schaefer, The University of Texas at Dallas, US
  • Nikil Dutt, UC Irvine, US
  • Honglan Jiang, Tsinghua University, CN
  • Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
  • Seokbum Ko, University of Saskatchewan, CA
  • Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
  • Daniel Menard, INSA Rennes, FR
  • Laura Pozzi, USI Lugano, CH
  • Anand Raghunathan, Purdue University, US
  • Semeen Rehman, TU Wien, AT
  • Daniel Wong, University of California, Riverside, US

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking.

D12 Reconfigurable Systems

Chair: Suhaib A. Fahmy, University of Warwick, GB

Co-Chair: Michaela Blott, Xilinx, IE

Topic Members

  • Christos Bouganis, Imperial College London, GB
  • Jean-Philippe Diguet, Lab-STICC, CNRS, FR
  • Miriam Leeser, Northeastern University, US
  • Bogdan Pasca, Intel, FR
  • Thomas Preußer, Accemic Technologies, DE
  • Marco D. Santambrogio, Politecnico di Milano, IT
  • David Sidler, Microsoft Corporation, CH
  • Ioannis Sourdis, Chalmers University of Technology, SE
  • Stephan Wong, Delft University of Technology, NL
  • Daniel Ziener, Technische Universität Ilmenau, DE

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D13 Logical and Physical Analysis and Design

Chair: L. Miguel Silveira, INESC ID/IST - Lisbon University, PT

Co-Chair: Mathias Soeken, Microsoft, CH

Topic Members

  • Vinicius Callegaro, Mentor, a Siemens Business, USA, US
  • Alper Demir, Koc University, TR
  • Elena Dubrova, Royal Institute of Technology - KTH, SE
  • Petr Fišer, Czech Technical University in Prague, FIT, CZ
  • Igor L. Markov, University of Michigan, US
  • Christos Sotiriou, Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE), GR
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
  • Eleonora Testa, Synopsys Inc., CH
  • Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT
  • Bei Yu, The Chinese University of Hong Kong, HK
  • Wenjian Yu, Tsinghua University, CN

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D14 Emerging Design Technologies for Future Computing

Chair: Elena Gnani, University of Bologna, IT

Co-Chair: Gage Hills, Massachusetts Institute of Technology, US

Topic Members

  • Mohamed M. Sabry Aly, Nanyang Technological University, SG
  • Yuanqing Cheng, Beihang University, CN
  • Maria Merlyne De Souza, The university of Sheffield, GB
  • Veeresh Deshpande, Helmholtz Zentrum Berlin, DE
  • Thomas Ernst, Cea Leti, FR
  • Vihar Georgiev, University of Glasgow, GB
  • Mariagrazia Graziano, Politecnico di Torino, IT
  • Kai Ni, Rochester Institute of Technology, US
  • Heike Riel, IBM Research, CH
  • Tajana Rosing, UCSD, US
  • Alessio Spessot, Imec, BE
  • Tony Wu, Facebook, US

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D15 Emerging Design Technologies for Future Memories

Chair: Shahar Kvatinsky, Technion, IL

Co-Chair: Chengmo Yang, University of Delaware, US

Topic Members

  • Yiran Chen, Duke University, US
  • Joseph Friedman, University of Texas at Dallas, US
  • Arne Heittman, RWTH Aachen University, DE
  • Xiaotao Jia, School of Microeletronics, Beihang University, CN
  • Alexandre Levisse, EPFL, CH
  • Jean-Philippe Noel, CEA, FR
  • Damien Querlioz, Univ Paris-Sud, FR
  • Marco Vacca, Politecnico di Torino, IT
  • Mengying Zhao, Shandong University, CN

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.


Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Theocharis Theocharides, University of Cyprus, CY

Topics

A1 Power-efficient and Sustainable Computing

Chair: Andreas Burg, EPFL-TCL, CH

Co-Chair: Jungwook Choi, Hanyang University, KR

Topic Members

  • Jose L. Ayala, Complutense University of Madrid, ES
  • Simone Benatti, University of Bologna, IT
  • Thidapat (Tam) Chantem, Virginia Tech, US
  • Mingu Kang, University of Illinois at Urbana Champaign, US
  • Saibal Mukhopadhyay, Georgia Institute of Technology, US
  • Qinru Qiu, Syracuse University, US
  • Amit Kumar Singh, University of Essex, GB

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Smart Cities, Internet of Everything, Smart Consumer Electronics

Chair: Saraju Mohanty, University of North Texas, US

Co-Chair: Fabrizio Lamberti, Politecnico di Torino, IT

Topic Members

  • Lucio Ciabattoni, Università Politecnica delle Marche, IT
  • Dhireesha Kudithipudi, University of Texas San Antonio, US
  • San Murugesan, BRITE Professional Resources; Western Sydney University, AU
  • Chrysostomos Nicopoulos, University of Cyprus, CY
  • Gordana Velikic, RTRK Institute, RS
  • Hui Zhao, UNT, US

Applications, design experiences and real-life implementations of theory, design, construction, manufacture and/or end-use of mass market electronics, systems, software, and services for smart cities, smart industries, smart homes, smart consumer electronics, Internet of Things (IoT), and Internet-of-Everything (IoE). Topics of interest include: smart and sustainable mobility; smart transportation; smart economy; smart environment (including street cleaning, water management, water supply, air quality monitoring, disposal facilities, lighting, etc.). Other topics of interest are the verticals of IoT, IoE, Industry 4.0, Consumer Electronics, smart home, and smart cities including: smart wearables; robotic systems for smart cities and smart homes; smart sensors; blockchain technology; video technology; audio technology; white goods; home care products; mobile communications; gaming; air care products; home automation and networking devices; home theater; digital imaging; in-vehicle technology; cable & satellite technology; home security; domestic lighting; human interface; consumer storage technology; AI/ML techniques for these smart systems; energy-management techniques for these systems; security-privacy techniques for these systems.

A3 Automotive Systems and Smart Energy Systems

Chair: Selma Saidi, Technische Universität Dortmund, DE

Co-Chair: Massimo Poncino, Politecnico di Torino, IT

Topic Members

  • Donkyu Baek, Chungbuk National University, KR
  • Davide Brunelli, University of Trento, IT
  • Lulu Chan, NXP Semiconductors, NL
  • Dip Goswami, Eindhoven University of Technology, NL
  • Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
  • Dirk Ziegenbein, Robert Bosch GmbH, DE

Design experiences for automotive systems, autonomous robotics, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits, systems, and embedded platforms; MEMS; integrated sensors and transducers; RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; battery management and E/E architecture for electric vehicles; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalized Healthcare

Chair: Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR

Co-Chair: Marina Zapater, University of Applied Sciences Western Switzerland (HES-SO), CH

Topic Members

  • Amir Aminifar, Lund University, SE
  • Guillermo Botella, Complutense University of Madrid, ES
  • Eduardo de la Torre, Technical University of Madrid, ES
  • Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT
  • Michele Magno, ETH Zurich, CH
  • Amir M. Rahmani, University of California, Irvine, US

Design experiences covering the use of body area networks, assistive and wearable technologies, robot-assisted living and healthcare, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures

Chair: Pascal Benoit, University of Montpellier, FR

Co-Chair: Bertrand Cambou, Northern Arizona University, US

Topic Members

  • Aydin Aysu, North Carolina State University, US
  • M. Khurram Bhatti, Information Technology University (ITU), PK
  • Lilian Bossuet, University of Lyon, FR
  • Ray Cheung, City University of Hong Kong, HK
  • Guillaume Duc, Télécom ParisTech, FR
  • Jean-Max Dutertre, Mines Saint-Etienne, FR
  • julien francq, Naval Group, FR
  • Kris Gaj, George Mason University, US
  • Basel Halak, Southampton University, GB
  • David Hély, Univ. Grenoble Alpes, Grenoble INP, LCIS, FR
  • Michail Maniatakos, New York University Abu Dhabi, AE
  • Cedric Marchand, Ecole centrale Lyon, FR
  • Nicolas Sklavos, Computer Engineering & Informatics Department, University of Patras, GR
  • Arnaud Tisserand, CNRS, IRISA, FR

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories, network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Learning Systems

Chair: Antonio Miele, Politecnico di Milano, IT

Co-Chair: Geoff Merrett, University of Southampton, GB

Topic Members

  • Woongki Baek, UNIST, KR
  • Giovanni Beltrame, Polytechnique Montreal, CA
  • X. Sharon Hu, University of Notre Dame, US
  • Andy Pimentel, University of Amsterdam, NL
  • Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR

Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling; prediction/forecasting and control of self-adaptive systems; adaptive systems and/or algorithms which can adapt their operation based on available resources, external contexts, etc.; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.) for adaptive systems; design experiences and industrial use-cases of self-adaptive systems, including those based on machine learning techniques.

A7 Applications of Emerging Technologies

Chair: Robert Wille, Johannes Kepler University Linz, AT

Co-Chair: Michael Niemier, University of Notre Dame, US

Topic Members

  • Matthew Amy, Dalhousie University, CA
  • Kerem Camsari, University of California, Santa Barbara, US
  • Anupam Chattopadhyay, Nanyang Technological University, SG
  • Deliang Fan, Arizona State University, US
  • Carmen G. Almudever, TU Delft, NL
  • Bastien Giraud, CEA LETI, FR
  • Said Hamdioui, Delft University of Technology, NL
  • Jim Harkin, Ulster University, GB
  • Bing Li, Technical University of Munich, DE
  • Vasilis Pavlidis, University of Manchester, GB
  • Frank Sill Torres, German Aerospace Center, DE
  • Michael Taylor, University of Washington, US
  • Xunzhao Yin, Zhejiang University, CN
  • Shimeng Yu, Georgia Institute of Technology, US

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers

Chair: Christian Weis, University of Kaiserslautern, DE

Co-Chair: Nicolas Ventroux, CEA, LIST, FR

Topic Members

  • vincent huard, Dolphin Design, FR
  • Mohamed Ibrahim, Intel Corporation, US
  • Dionisios Pnevmatikatos, School of ECE, National Technical University of Athens & FORTH-ICS, GR

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


Track T: Test and Dependability

covers all test, design-for-test, reliability, and designfor-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Ilia Polian, University of Stuttgart, DE

Topics

T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability

Chair: Arnaud Virazel, LIRMM, FR

Co-Chair: Bram Kruseman, NXP Semiconductors, NL

Topic Members

  • Lorena Anghel, Grenoble-Alpes University, FR
  • Seiji Kajihara, Kyushu Institute of Technology, JP
  • Naghmeh Karimi, University of Maryland Baltimore County, US
  • Antonio Rubio, Universitat Politècnica Catalunya (UPC), ES
  • Christian Sauer, Cadence Design Systems, DE
  • Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
  • Mottaqiallah Taouil, Delft University of Technology, NL
  • Hank Walker, Texas A&M University, US

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis

Chair: Patrick Girard, LIRMM / CNRS, FR

Co-Chair: Bernd Becker, University of Freiburg, DE

Topic Members

  • Paolo Bernardi, Politecnico di Torino, IT
  • Artur Jutman, Testonica Lab, EE
  • Melanie Schillinsky, NXP Germany GmbH, DE
  • Jerzy Tyszer, Poznan University of Technology, PL
  • Xiaoqing Wen, Kyushu Institute of Technology, JP

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Dependability and System-Level Test

Chair: Karthik Pattabiraman, University of British Columbia, CA

Co-Chair: Stefano Di Carlo, Politecnico di Torino, IT

Topic Members

  • Jyotika Athavale, Intel Corporation, US
  • Goerschwin Fey, Hamburg University of Technology, DE
  • Dimitris Gizopoulos, University of Athens, GR
  • Marco Ottavi, University of Rome "Tor Vergata", IT
  • Jaan Raik, Tallinn University of Technology, EE
  • Paolo Rech, LANL/UFRGS, US
  • Juan Carlos Ruiz Garcia, Universitat Politecnica de Valencia, ES
  • Rishad Shafik, Newcastle University, GB
  • Daniel Tille, Infineon Technologies, DE

HW and SW solutions for system’s dependability crossing all layers of the system’s stack: microarchitecture-level and system-level error/fault modeling; cross-layer dependability analysis and evaluation; reliable and fail-safe architectures and systems design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Manuel Barragan, TIMA Laboratory, FR

Co-Chair: Mark Po-Hung Lin, National Chiao Tung University, TW

Topic Members

  • Davide Appello, STMicroelectronics, IT
  • Florence AZAIS, Univ. Montpellier, CNRS, LIRMM, FR
  • Günhan Dündar, Bogazici University, TR
  • Helmut Graeb, Technical University of Munich, DE
  • Jiun-Lang Huang, National Taiwan University, TW
  • Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
  • Shahriar Mirabbasi, University of British Columbia, CA
  • Sule Ozev, ASU, US
  • Manoj Sachdev, University of Waterloo, CA
  • Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Lejla Batina, Radboud University Nijmegen, NL

Co-Chair: Nele Mentens, KU Leuven, BE

Topic Members

  • Ileana Buhan, Radboud University, NL
  • Fatemeh Ganji, Worcester Polytechnic Institute, US
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
  • Mike Hutter, Cryptography Research Inc., US
  • Kostas Papagiannopoulos, Radboud University Nijmegen, NL
  • Stjepan Picek, TU Delft, NL
  • Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
  • Kazuo Sakiyama, The University of Electro-Communications, JP
  • Johanna Sepúlveda, Airbus Defence and Space, DE
  • Bohan Yang, Tsinghua University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modeling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Marcel Medwed, NXP Semiconductors Austria GmbH, AT

Topic Members

  • Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
  • Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
  • Giorgio Di Natale, TIMA, FR
  • Junfeng Fan, Open Security Research, Inc., CN
  • Samaneh Ghandali, Google, US
  • Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
  • Johann Heyszl, Fraunhofer AISEC, DE
  • Elif Bilge Kavun, University of Passau, DE
  • Osnat Keren, Bar-Ilan University, IL
  • Patrick Schaumont, Worcester Polytechnic Institute, US
  • Tobias Schneider, NXP Semiconductors, AT
  • Ruggero Susella, STMicroelectronics, IT
  • Russ Tessier, University of Massachusetts, US
  • Yuval Yarom, The University of Adelaide and Data61, AU

Design-for-trust (secure design methods); test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; design and design automation (for HW tampering attacks and protection, for countermeasures, for side-channel protection verification, for fault protection verification); microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); machine learning for the above topics; adversarial attacks on machine learning.


Track E: Embedded and Cyber-Physical Systems

is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.

Track Chair: Valeria Bertacco, University of Michigan, US

Topics

E1 Embedded Software Architecture, Compilers and Tool Chains

Chair: Sara Vinco, Politecnico di Torino, IT

Co-Chair: Rodolfo Pellizzoni, University of Waterloo, CA

Topic Members

  • Nicola Bombieri, University of Verona, IT
  • Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG
  • Christian Fabre, CEA LIST, FR
  • Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), DE
  • Andrea Marongiu, Università di Modena e Reggio Emilia, IT
  • Maryam Mehri Dehnavi, University of Toronto, CA
  • Eduardo Quinones, Barcelona Supercomputing Center, ES

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E2 Real-time, dependable and privacy-enhanced systems

Chair: Liliana Cucu-Grosjean, INRIA, FR

Co-Chair: Marko Bertogna, University of Modena, IT

Topic Members

  • Arvind Easwaran, Nanyang Technological University, SG
  • Julien Forget, Univ. Lille, FR
  • Leandro Indrusiak, University of York, GB
  • Hyoseung Kim, University of California, Riverside, US
  • Claire Maiza, Grenoble INP / Verimag, FR
  • Renato Mancuso, Boston University, US
  • Laurent Mounier, VERIMAG / UGA, FR
  • Elena Troubitsyna, KTH -- Royal Institute of Technology, SE

Real-time performance modeling, analysis and empirical evaluation; worst-case performance analysis techniques; real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; security attack protection and analysis of embedded systems' hardware and software; privacy-enhanced and safety-enhanced systems; network control and QoS for embedded applications.

E3 Machine Learning Solutions for Embedded and Cyber-Physical Systems

Chair: Luca Carloni, Columbia University, US

Co-Chair: Mario R. Casu, Politecnico di Torino, Department of Electronics and Telecommunications, IT

Topic Members

  • David Atienza, École Polytechnique Fédérale de Lausanne (EPFL), CH
  • Anup Das, Drexel University, US
  • Diana Goehringer, TU Dresden, DE
  • Kyuho Lee, UNIST, KR
  • Tulika Mitra, National University of Singapore, SG
  • Smail Niar, Université Polytechnique Hauts-de-France, FR
  • Alessandro Pinto, Raytheon Technologies Research Center, US
  • Abbas Rahimi, UC Berkeley, US
  • Brandon Reagen, NYU/Facebook, US

Hardware architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning solutions; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; case studies of machine learning applications implemented on embedded systems and cyber physical systems.

E4 Design Methodologies for Machine Learning Architectures

Chair: Marian Verhelst, KU Leuven, BE

Co-Chair: Tushar Krishna, Georgia Institute of Technology, US

Topic Members

  • Giovanni Ansaloni, EPFL, CH
  • Luigi Carro, UFRGS, BR
  • Henk Corporaal, TU/e (Eindhoven University of Technology), NL
  • Giulio Gambardella, Xilinx, IE
  • Ujjwal Gupta, Intel Corporation, US
  • Callie Hao, Georgia Institute of Technology, US
  • Axel Jantsch, TU Wien, AT
  • Ben Keller, NVIDIA Corporation, US
  • Huichu Liu, Facebook Inc., US
  • Bert Moons, Qualcomm, NL
  • Jae-sun Seo, Arizona State University, US
  • Sander Stuijk, Eindhoven University of Technology, NL
  • Paul Whatmough, Arm Research, US

Design methodologies, flows, and tools targeting ML designs on ASICs/FPGAs, encompassing design exploration, high level synthesis, architecture optimizations, algorithm mapping and scheduling, verification, performance, reliability, accuracy and power modeling; frameworks for exact or approximate AI/ML, exploiting deep learning, neuromorphic computing, probabilistic reasoning, planning, reinforcement learning, and other emerging ML techniques; exploration methodologies for digital, analog, mixed-signal and compute-in-memory platforms.

E5 Design modeling and verification for embedded and cyber-physical systems

Chair: Davide Quaglia, University of Verona, IT

Co-Chair: Mohammad Al Faruque, University of California Irvine, US

Topic Members

  • Wanli Chang, University of York, GB
  • Jyotirmoy Deshmukh, University of Southern California, US
  • Martin Horauer, University of Applied Sciences Technikum Wien, AT
  • Wenchao Li, Boston University, US
  • Chung-Wei Lin, National Taiwan University, TW
  • Roberto Passerone, University of Trento, IT

Modeling, design, verification, validation and optimization of embedded systems and Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things as well as software-intensive CPS; modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, quality-of-service, safety and reliability; theories, languages and tools supporting model-based design flows covering software, control and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining and CPS, autonomous CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behavior in smart grids).