Programme | DATE 2023

The DATE 2023 programme will be available here in January 2023.

BPA_6 Logic Synthesis and verification

Date: Monday, 17 April 2023
Time: 14:00 - 16:00 CET

Time	Label	Presentation Title Authors
00:39 CET		COMPUTING EFFECTIVE RESISTANCES ON LARGE GRAPHS BASED ON APPROXIMATE INVERSE OF CHOLESKY FACTOR Authors: Zhiqiang Liu and Wenjian Yu, Tsinghua University, CN Abstract Effective resistance, which originates from the field of circuits analysis, is an important graph distance in spectral graph theory. It has found numerous applications in various areas, such as graph data mining, spectral graph sparsification, circuits simulation, etc. However, computing effective resistances accurately can be intractable and we still lack efficient methods for estimating effective resistances on large graphs. In this work, we propose an efficient algorithm to compute effective resistances on general weighted graphs, based on a sparse approximate inverse technique. Compared with a recent competitor, the proposed algorithm shows several hundreds of speedups and also one to two orders of magnitude improvement in the accuracy of results. Incorporating the proposed algorithm with the graph sparsification based power grid (PG) reduction framework, we develop a fast PG reduction method, which achieves an average 6.4X speedup in the reduction time without loss of reduction accuracy. In the applications of power grid incremental analysis and transient analysis, the proposed method shows 2.5X and 1.7X advantages over the PG reduction method based on accurate effective resistances, with no increase in the errors of solutions.
00:39 CET		FANOUT-BOUNDED LOGIC SYNTHESIS FOR EMERGING TECHNOLOGIES - A TOP-DOWN APPROACH Authors: Dewmini Marakkalage¹ and Giovanni De Micheli² ¹EPFL, CH; ²École Polytechnique Fédérale de Lausanne (EPFL), CH Abstract In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. In this work, we study the problem of resynthesizing a logic network with bounded-fanout gates while minimizing area. We 1) formulate this problem for a fixed target logic depth as an integer linear program (ILP) and present exact solutions for small logic networks, and 2) propose a top-down approach to construct a feasible solution to the ILP which yields an efficient algorithm for fanout bounded synthesis. When using the minimum depth achievable with unbounded fanouts as the target logic depth, our top-down approach achieves 11.82% better area as compared to the state-of-the-art with matching or better delays.
00:39 CET		SYNTHESIS WITH EXPLICIT DEPENDENCIES Authors: Priyanka Golia¹, Subhajit Roy² and Kuldeep S Meel³ ¹IIT Kanpur and NUS Singapore, SG; ²IIT Kanpur, IN; ³National University of Singapore, SG Abstract Quantified Boolean Formulas (QBF) extend propositional logic with quantification /forall exists for propositional variables. In QBF, an existentially quantified variable is allowed to depend on all universally quantified variables in its scope. Dependency Quantified Boolean Formulas (DQBF) restrict the dependencies of existentially quantified variables. In DQBF, existentially quantified variables have explicit dependencies on a subset of universally quantified variables, called Henkin dependencies. Given a Boolean specification between the set of inputs and outputs, the problem of Henkin synthesis is to synthesize each output variable as a function of its Henkin dependencies such that the specification is met. Henkin synthesis has wide-ranging applications, including verification of partial circuits, controller synthesis, and circuit realizability. In this work, we propose a data-driven approach for Henkin synthesis called HSynth. On an extensive evaluation of over 563 instances arising from past DQBF solving competitions, we demonstrate that HSynth is competitive with state-of-the-art tools. Furthermore, HSynth solves 26 benchmarks that none of the current state-of-the-art techniques could solve.

BPA_9 Memory Centric Computing

Date: Monday, 17 April 2023
Time: 14:00 - 16:00 CET

Time	Label	Presentation Title Authors
00:39 CET		MINIMIZING COMMUNICATION CONFLICTS IN NETWORK-ON-CHIP BASED PROCESSING-IN-MEMORY ARCHITECTURE Authors: Hanbo Sun, Tongxin Xie, Zhenhua Zhu, Guohao Dai, Huazhong Yang and Yu Wang, Tsinghua University, CN Abstract Deep Neural Networks (DNNs) have made significant breakthroughs in various fields. However, their enormous computation and parameters seriously hinder their application. Emerging Processing-In-Memory (PIM) architectures provide extremely high energy efficiency to accelerate DNN computing. Moreover, Network-on-Chip (NoC) based PIM architectures significantly improve the scalability of PIM architectures. However, the contradiction between high communication and limited NoC bandwidth introduces severe communication conflicts. Existing work neglects the impact of communication conflicts. On the one hand, neglecting communication conflicts leads to the lack of precise performance estimations in the mapping process, making it hard to find optimal results. On the other hand, communication conflicts cause low NoC bandwidth utilization in the schedule process. And there is over 70% latency gap in existing work caused by communication conflicts. This paper proposes communication conflict optimized mapping and schedule strategies for NoC based PIM architectures. The proposed mapping strategy constructs communication conflict graphs to model communication conflicts. Based on this constructed graph, we adopt a Graph Neural Network (GNN) as a precise performance estimator. Our schedule strategy predefines the communication priority and NoC communication behavior tables for target DNN workloads. In this way, it can improve the NoC bandwidth utilization effectively. Compared with existing work, for typical classification DNNs on the CIFAR and ImageNet datasets, the proposed strategies reduce 78% latency and improve the throughput by 3.33x on average with negligible deployment and hardware overhead. Experimental results also show that our strategies decrease the average gap to ideal cases without communication conflicts from 80.7% and 70% to 12.3% and 1.26% for latency and throughput, respectively.
00:39 CET		HIERARCHICAL NON-STRUCTURED PRUNING FOR COMPUTING-IN-MEMORY ACCELERATORS WITH REDUCED ADC RESOLUTION REQUIREMENT Authors: Wenlu Xue¹, Jinyu Bai², Sifan Sun³ and Wang Kang² ¹Beihang Universiry, CN; ²Beihang University, CN; ³Beiahng University, CN Abstract The crossbar architecture, which is comprised of novel nano-devices, enables high-speed and energy-efficient computing-in-memory (CIM) for neural networks. However, the overhead from analog-to-digital converters (ADCs) substantially degrades the energy efficiency of CIM accelerators. In this paper, we introduce a hierarchical non-structured pruning strategy where value-level and bit-level pruning are performed jointly on neural networks to reduce the resolution of ADCs by using the famous alternating direction method of multipliers (ADMM). To verify the effectiveness, we deployed the proposed method to a variety of state-of-the-art convolutional neural networks on two image classification benchmark datasets: CIFAR10, and ImageNet. The results show that our pruning method can reduce the required resolution of ADCs to 2 or 3 bits with only slight accuracy loss (∼0.25%), and thus can improve the hardware efficiency by 180%.
00:39 CET		PIC-RAM: PROCESS-INVARIANT CAPACITIVE MULTIPLIER BASED ANALOG IN MEMORY COMPUTING IN 6T SRAM Authors: Kailash Prasad¹, Aditya Biswas¹, Arpita Kabra² and Joycee Mekie² ¹IIT Gandhinagar, IN; ²Indian Institute of Technology Gandhinagar, IN Abstract In-Memory Computing (IMC) is a promising approach to enabling energy-efficient Deep Neural Network-based applications on edge devices. However, analog domain dot product and multiplication suffers accuracy loss due to process variations. Furthermore, wordline degradation limits its minimum pulsewidth, creating additional non-linearity and limiting IMC's dynamic range and precision. This work presents a complete end-to-end process invariant capacitive multiplier based IMC in 6T-SRAM (PIC-RAM). The proposed architecture employs the novel idea of two-step multiplication in column-major IMC to support 4-bit multiplication. The PIC-RAM uses an operational amplifier-based capacitive multiplier to reduce bitline discharge allowing good enough WL pulse width. Further, it employs process tracking voltage reference and fuse capacitor to tackle dynamic and post-fabrication process variations, respectively. Our design is compute-disturb free and provides a high dynamic range. To the best of our knowledge, PIC-RAM is the first analog SRAM IMC approach to tackle process variation with a focus on its practical implementation. PIC-RAM has a high energy efficiency of about 25.6 TOPS/W for 4-bit X 4-bit multiplication and has only 0.5% area overheads due to the use of the capacitance multiplier. We obtain 409 bit-wise TOPS/W, which is about 2X better than state-of-the-art. PIC-RAM shows the TOP-1 accuracy for ResNet-18 on CIFAR10 and MNIST is 89.54% and 98.80% for 4bitX4bit multiplication.

S_D6 Reconfigurable architectures, machine learning and circuit design

Date: Monday, 17 April 2023
Time: 16:30 - 18:00 CET

Time	Label	Presentation Title Authors
00:39 CET		TOWARDS EFFICIENT NEURAL NETWORK MODEL PARALLELISM ON MULTI-FPGA PLATFORMS Authors: David Rodriguez Agut¹, Rafael Tornero² and Josè Flich³ ¹Universitat Politecnica de Valencia, ES; ²Universitat Polit�cnica de Val�ncia, ES; ³Associate Professor, Universitat Politècnica de València, ES Abstract Nowadays, convolutional neural networks (CNN) are common in a wide range of applications. Their high accuracy and efficiency contrast with their computing requirements, leading to the search for efficient hardware platforms. FPGAs are suitable due to their flexibility, energy efficiency and low latency. However, the ever increasing complexity of CNNs demands higher capacity devices, forcing the need for multi-FPGA platforms. In this paper, we present a multi-FPGA platform with distributed shared memory support for the inference of CNNs. Our solution, in contrast with previous works, enables combining different model parallelism strategies applied to CNNs, thanks to the distributed shared memory support. For a four FPGA setting, the platform reduces the execution time of 2D convolutions by a factor of 3.95 when compared to single FPGA. The inference of standard CNN models is improved by factors ranging 3.63-3.87.
00:39 CET		HIGH-ACCURACY LOW-POWER RECONFIGURABLE ARCHITECTURES FOR DECOMPOSITION-BASED APPROXIMATE LOOKUP TABLE Authors: Xingyue Qian¹, Chang Meng¹, Xiaolong Shen², Junfeng Zhao², Leibin Ni² and Weikang Qian¹ ¹Shanghai Jiao Tong University, CN; ²2012Labs, Huawei technologies Co.,Ltd., CN Abstract Storing pre-computed results of frequently-used functions into lookup table (LUT) is a popular way to improve energy efficiency, but its advantage diminishes as the number of input bits increases. A recent work shows that by decomposing the target function approximately, the total LUT entries can be dramatically reduced, leading to significant energy saving. However, its heuristic approximate decomposition algorithm explores the solution space greedily, so the approximation quality is not optimal. Also, its rigid hardware architecture only supports disjoint decomposition and may have unnecessary extra power consumption in some cases. To address these issues, we develop a novel beam search and simulated annealing-based approximate decomposition algorithm, which can reduce 11.1% error. We also implement a non-disjoint approximate decomposition method and propose two reconfigurable architectures. The first one has 10.4% less error using 19.2% less energy and the other has 23.0% less error with same energy consumption compared to the state-of-the-art design.
00:39 CET		FPGA ACCELERATION OF GCN IN LIGHT OF THE SYMMETRY OF GRAPH ADJACENCY MATRIX Authors: Gopikrishnan Raveendran Nair¹, Han-sok Suh¹, Mahantesh Halappanavar², Frank Liu³, Jae-sun Seo¹ and Yu Cao¹ ¹Arizona State University, US; ²Pacific Northwest National Laboratory, US; ³Oak Ridge National Lab, US Abstract Graph Convolutional Neural Networks (GCNs) are widely used to process large-scale graph data. Different from deep neural networks (DNNs), GCNs are sparse, irregular, and unstructured, posing unique challenges to hardware acceleration with regular processing elements (PEs). In particular, the adjacency matrix of a GCN is extremely sparse, leading to frequent but irregular memory access, low spatial-temporal data locality and poor data reuse. Furthermore, a realistic graph usually consists of unstructured data (e.g., unbalanced distributions), creating significantly different processing times and imbalanced workload for each node in GCN acceleration. To overcome these challenges, we propose an end-to-end hardware-software co-design to accelerate GCNs on resource-constrained FPGAs with the features including: (1) A custom dataflow that leverages symmetry along the diagonal of the adjacency matrix to accelerate feature aggregation for undirected graphs. We utilize either the upper or the lower triangular matrix of the adjacency matrix to perform aggregation in GCN to improve data reuse. (2) Unified compute cores for both aggregation and transform phases, with full support to the symmetry-based dataflow. These cores can be dynamically reconfigured to the systolic mode for transformation or as individual accumulators for aggregation in GCN processing. (3) Prepossessing of the graph in software to rearrange the edges and features to match the custom dataflow. This step improves the regularity in memory access and data reuse in the aggregation phase. Moreover, we quantize the GCN precision from FP32 to INT8 to reduce the memory footprint without losing the inference accuracy. We implement our accelerator design in Intel Stratix10 MX FPGA board with HBM2, and demonstrate significant improvement in end-to-end GCN operations as compared to the state of the art, on the graph datasets of Cora, Pubmed, Citeseer and Reddit.
00:39 CET		PR-ESP: AN OPEN-SOURCE PLATFORM FOR DESIGN AND PROGRAMMING OF PARTIALLY RECONFIGURABLE SOCS Authors: Biruk Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter and Luca Carloni, Columbia University, US Abstract Despite its presence for more than two decades and its proven benefits in expanding the space of system design, dynamic partial reconfiguration (DPR) is rarely integrated into frameworks and platforms that are used to design complex reconfigurable system-on-chip (SoC) architectures. This is due to the complexity of the DPR FPGA flow as well as the lack of architectural and software runtime support to enable and fully harness DPR. Moreover, as DPR designs involve additional design steps and constraints, they often have a higher FPGA compilation (RTL-to-bitstream) runtime compared to equivalent monolithic designs. In this work, we present PR-ESP, an open-source platform for a system-level design flow of partially reconfigurable FPGA-based SoC architectures targeting embedded applications that are deployed on resource-constrained FPGAs. Our approach is realized by combining SoC design methodologies and tools from the open-source ESP platform with a fully-automated DPR flow that features a novel size-driven technique for parallel FPGA compilation. We also developed a software runtime reconfiguration manager on top of Linux. Finally, we evaluated our proposed platform using the WAMI-App benchmark application on Xilinx VC707.
00:39 CET		ISOP: MACHINE LEARNING ASSISTED INVERSE STACK-UP OPTIMIZATION FOR ADVANCED PACKAGE DESIGN Authors: Hyunsu Chae¹, Bhyrav Mutnury², Keren Zhu¹, Doug Wallace², Doug Winterberg², Daniel de Araujo³, Jay Reddy², Adam Klivans¹ and David Z. Pan¹ ¹University of Texas at Austin, US; ²Dell Enterprise Product Group, US; ³Siemens EDA, US Abstract Future computing calls for heterogeneous integration, e.g., the recent adoption of the chiplet methodology. However, high-speed cross-chip interconnects, and packaging shall be critical for the overall system performance. As an example of advanced packaging, a high-density interconnect (HDI) printed circuit board (PCB) has been widely used in complex electronics from cell phones to computing servers. A modern HDI PCB may have over 20 layers, each with its unique material properties and geometrical dimensions, i.e., stack-up, to meet various design constraints and performance optimizations. However, stack-up design is usually done manually in the industry, where experienced designers may devote many hours adjusting the physical dimensions and materials in order to meet the desired specifications. This process, however, is time-consuming, tedious, and sub-optimal, largely depending on the designer's expertise. In this paper, we propose to automate the stack-up design with a new framework, ISOP, using machine learning for inverse stack-up optimization for advanced package design. Given a target design specification, ISOP automatically searches for ideal stack-up design parameters while optimizing performance. We develop a novel machine learning-assisted hyper-parameter optimization method to make the search efficient and reliable. Experimental results demonstrate that ISOP is 11.6%, 40.7%, 24.8%, and 26.6% better in figure-of-merit (FoM) than conventional simulated annealing and Bayesian optimization algorithms with all our design targets met with a shorter runtime. We also compare our fully-automated ISOP with expert designers in the industry and achieve very promising results, with orders of magnitude reduction of turn-around time.
00:39 CET		FAST AND ACCURATE WIRE TIMING ESTIMATION BASED ON GRAPH LEARNING Authors: Yuyang Ye¹, Tinghuan Chen², Yifei Gao¹, Hao Yan¹, Bei Yu² and Longxing Shi¹ ¹Southeast University, CN; ²The Chinese University of Hong Kong, HK Abstract Accurate wire timing estimation has become a bottleneck in timing optimization caused by the long turn-around time using a sign-off timer. Unlike gate timing is calculated accurately by interpolating lookup tables in cell libraries, wire timing calculation has low accuracy and efficiency for complex RC nets, including both tree-like and non-tree nets. The limited number of wire paths opens a door for the graph learning method used to estimate wire timing. In this work, we present a fast and accurate wire timing estimator based on a novel graph learning architecture, namely GNNTrans. GNNTrans can generate wire path representations through aggregating local structure information and global relationships of whole RC nets, which cannot be collected with traditional graph learning work efficiently. Experimental results on both tree-like and non-tree nets of real-world open-source designs demonstrate improved accuracy with the max error of wire delay being lower than 5 ps. Our estimator can predict the timing of over 200K nets in less than 100 secs and can be integrated into incremental timing optimization.
00:39 CET		DTOC: INTEGRATING DEEP-LEARNING DRIVEN TIMING OPTIMIZATION INTO STATE-OF-THE-ART COMMERCIAL EDA TOOL Authors: Kyungjoon Chang¹, Heechun Park², Jaehoon Ahn¹, Kyu-Myung Choi¹ and Taewhan Kim¹ ¹Seoul National University, KR; ²Kookmon University, KR Abstract Recently, deep-learning (DL) models have been paid a considerable attention to timing prediction in the placement and routing (P&R) flow. As yet, the DL based prior works are confined to timing prediction at the time-consuming global routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. This is because it is not easy to "accurately” predict various timing parameters at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through making use of commercial P&R tools. In this work, we propose a framework, called DTOC, to be used at the pre-route stage for this end. Precisely, the framework is composed of two models: (1) a DL driven arc delay and arc output slew prediction model, performing in two levels: (level1) predicting net resistance (R), net capacitance (C), and arc length (Len), followed by (level-2) predicting arc delay and arc output slew from the R/C/Len prediction obtained in (level-1); (2) a timing optimization model, which uses the inference outcomes in our DL driven prediction model to enable the commercial P&R tools to calculate the full path delays, setting update timing margins on paths, so that the P&R tools should use more accurate margins on timing optimization. Experimental results show that, by using our DTOC framework during timing optimization in P&R, we improve the pre-route prediction accuracy on arc delay and arc output slew by 20∼26% on average, and improve the WNS, TNS, and the number of timing violation paths by 50∼63% on average.
00:39 CET		RL-LEGALIZER: REINFORCEMENT LEARNING-BASED CELL PRIORITY OPTIMIZATION IN MIXED-HEIGHT STANDARD CELL LEGALIZATION Authors: Sung-Yun Lee¹, Seonghyeon Park², Daeyeon Kim², Minjae Kim², Tuyen Le³ and Seokhyeong Kang⁴ ¹Pohang University of Science and Technology (POSTECH), KR; ²POSTECH, KR; ³AgileSoDA, KR; ⁴Pohang University of Science and Technology, KR Abstract Cell legalization order has a substantial effect on the quality of modern VLSI designs, which use mixed-height standard cells. In this paper, we propose a deep reinforcement learning framework to optimize cell priority in the legalization phase of various designs. We extract the selected features of movable cells and their surroundings, then embed them into cell-wise deep neural networks. We then determine cell priority and legalize them in order using a pixel-wise search algorithm. The proposed framework uses a policy gradient algorithm and several training techniques, including grid-cell subepisode, data normalization, reduced-dimensional state, and network optimization. We aim to resolve the suboptimality of existing sequential legalization algorithms with respect to displacement and wirelength. On average, our proposed framework achieved 34% lower legalization costs in various benchmarks compared to that of the state-of-the-art legalization algorithm.
00:39 CET		NEURAL NETWORK ON THE EDGE: EFFICIENT AND LOW COST FPGA IMPLEMENTATION OF DIGITAL PREDISTORTION IN MIMO SYSTEMS Authors: Yiyue Jiang¹, Andrius Vaicaitis², John Dooley² and Miriam Leeser¹ ¹Department of Electrical and Computer Engineering at Northeastern University, US; ²Department of Electronic Engineering at Maynooth University, IE Abstract Processing on the edge with low latency is increasingly important in wireless systems, and reconfigurable hardware provides the necessary performance for this application domain. The focus of this research is Digital PreDistortion (DPD) in Multiple-Input and Multiple-Output (MIMO) systems and particularly in processing data to rapidly adapt to the current wireless environment. We accomplish this by implementing a training sample reduced and hardware efficient Real Valued Time Delay Neural Network (RVTDNN) implemented on FPGA hardware. Data streams from four Power Amplifiers (PAs) are combined and processed using a single neural network to perform DPD. This implementation exploits a novel way to minimize the training signal sample selection based on a biased probability density function (pdf) to reduce the training time of the neural network. The paper describes hardware specific optimizations in the implementation of the NN including a pipelined RVTDNN structure with low digital cost along with high throughput, and an activation function that is efficient to implement in hardware. The design has been validated using an AMD/Xilinx RFSoC ZCU216 board and surpasses the data throughput of conventional RVTDNN based DPD while only using a fraction of their hardware utilization.
00:39 CET		QUANTISED NEURAL NETWORK ACCELERATORS FOR LOW-POWER IDS IN AUTOMOTIVE NETWORKS Authors: Shashwat Khandelwal, Anneliese Walsh and Shreejith Shanker, Trinity College Dublin, IE Abstract Rising connectivity in vehicles in response to an increase in in-vehicle driving assistance with systems like Advanced Driver Assistance Systems (ADAS) has exposed inherent hidden vulnerabilities in modern-day vehicular networks. This has led to an increase in both active (injection) and passive (eavesdropping/sniffing) attacks in vehicles. Intrusion detection systems (IDSs) have been proposed for automotive networks to address these risks; however, these often struggle to meet the latency and power requirements for an in-vehicle deployment. In this paper, we present low-power custom quantised Multi Layer Perceptrons (MLPs) as an Intrusion Detection System for automotive controller area network (CAN). We utilise the FINN framework from AMD/Xilinx to quantise, train and generate the hardware IP of our MLP to detect denial of service (DoS), fuzzing, and spoofing attacks (RPM & Gear) on CAN network, using ZCU104 (XCZU7EV) FPGA as our target ECU architecture with integrated IDS capabilities. Our approach achieves significant improvements in latency (0.12 ms per-message processing latency) and inference energy consumption (0.25 mJ per inference) while achieving similar classification performance as state-of-the-art approaches proposed in the research literature.

S_D7 Logical and physical analysis and design

Date: Monday, 17 April 2023
Time: 16:30 - 18:00 CET

Time	Label	Presentation Title Authors
00:39 CET		SYNTHESIS AND UTILIZATION OF STANDARD CELLS AMENABLE TO GEAR RATIO OF GATE-METAL PITCHES FOR IMPROVING PIN ACCESSIBILITY Authors: Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo and Taewhan Kim, Seoul National University, KR Abstract Traditionally, the synthesis of standard cells invariably assumes that the gear ratio (GR) between the gate poly pitch in the cells and the metal pitch of the first vertical metal layer (to be used for routing) over the gate poly is 1:1 for chip implementation. However, the scaling trend in sub-10nm node CMOS designs is that GR is changing from 1:1 to 3:2 or 4:3, which means the number and location of pin access points vary depending on the cell placement location, thereby causing hard-to-pin-access if the pin access points were aligned on the offtrack routing pattern. This work overcomes the pin inaccessibility problem caused by non-1:1 GR in chip implementation. Precisely, we propose a non-1:1 GR aware DTCO (design and technology co-optimization) flow to generate cells with pin patterns that are best suited to the implementation of target design. To this end, we propose two new tasks to be installed in our DTCO framework: (1) from the existing cells optimized for 1:1 GR, we relocate their pin patterns amenable to non-1:1 GR, so that a maximal pin accessibility should be achieved; (2) we incrementally update the pin patterns of the cell instances with routing failures due to pin inaccessibility in the course of the DTCO iterations to produce the cells with best fitted pin patterns to the implementation of target design. Through experiments with benchmark circuits, it is shown that our DTCO methodology optimizing pin patterns amenable to non-1:1 GR is able to produce chip implementations with on average 5.88× fewer routing failures at no additional wirelength, timing, and power cost.
00:39 CET		CENTER-OF-DELAY: A NEW METRIC TO DRIVE TIMING MARGIN AGAINST SPATIAL VARIATION IN COMPLEX SOCS Authors: Christian Lutkemeyer¹ and Anton Belov² ¹Marvell Semiconductor, Inc., US; ²Synopsys Inc, IE Abstract Complex VLSI SOCs are manufactured on large 300mm wafers. Individual SOCs can show significant spatial performance gradients in the order of 10% per 10mm. The traditional approach to handling this variation in STA tools is a margin look-up table indexed by the diagonal of the bounding box around the gates in a timing path. In this paper we propose a new approach based on the concept of the Center-of-Delay of a timing path. We justify this new approach theoretically for linear performance gradients and present experimental data that shows that the new approach is both safe, and significantly less pessimistic than the existing method.
00:39 CET		A NOVEL DELAY CALIBRATION METHOD CONSIDERING INTERACTION BETWEEN CELLS AND WIRES Authors: Leilei Jin, Jia Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling and Longxing Shi, Southeast University, CN Abstract In the advanced technology, the accuracy of cell and wire delay modeling are the key metrics for timing analysis. However, when the supply voltage decreases to the near-threshold regime, the complicated process variation effect causes the cell delay and the wire delay hard to model. Most researchers study cell or wire delay separately, ignoring the coefficients between them. In this paper, we propose an N-sigma delay model by characterizing different sigma levels (-3σ to +3σ) of the cell and wire delay distribution. The N-sigma cell delay model is represented by the first four moments and calibrated by the operating conditions (input slew, output load). Meanwhile, based on the Elmore model, the wire delay variability is calculated by considering the effect of drive and load cells. The delay models are verified through the ISCAS85 benchmarks and the functional units of PULPino processor with TSMC 28 nm technology. Compared to the SPICE results, the average errors for estimating the +⁄- 3σ cell delay are 2.1% and 2.7% and those of the wire delay are 2.4% and 1.6%, respectively. The errors of path delay analysis keep below 6.6% and the speed is 103X over SPICE MC simulations.
00:39 CET		RETHINKING NPN CLASSIFICATION FROM FACE AND POINT CHARACTERISTICS OF BOOLEAN FUNCTIONS Authors: Jiaxi Zhang¹, Shenggen Zheng², Liwei Ni³, Huawei Li³ and Guojie Luo¹ ¹Peking University, CN; ²Peng Cheng Laboratory, CN; ³Institute of Computing Technology, Chinese Academy of Sciences, CN Abstract NPN classification is an important problem in the synthesis flows of digital circuits. Most existing works explored variable symmetries and cofactor signatures to develop their classification methods. However, cofactor signatures only consider the face characteristics of Boolean functions. In this paper, we propose a new NPN classifier using both face and point characteristics of Boolean functions, including cofactor, influence, and sensitivity. The new method brings a new perspective to the classification of Boolean functions. The classifier only needs to compute some signatures, and the equality of corresponding signatures is a prerequisite for NPN equivalence. Therefore, these signatures can be directly used for NPN classification, thus avoiding the exhaustive transformation enumeration. The experiments show that the proposed NPN classifier gains better NPN classification accuracy with comparable speed.
00:39 CET		EXACT SYNTHESIS BASED ON SEMI-TENSOR PRODUCT CIRCUIT SOLVER Authors: Hongyang Pan¹ and Zhufei Chu² ¹Ningbo university, CN; ²Ningbo University, CN Abstract In logic synthesis, Boolean satisfiability (SAT) is widely used as a reasoning engine, especially for exact synthesis. By representing input formulas as logic circuits instead of conjunction normal forms (CNFs) as in off-the-shelf CNF-based SAT solvers, circuit-based SAT solvers enable decoding after solution to be easier. An exact synthesis method based on a semi-tensor product (STP) circuit solver is presented in this paper. As opposed to other SAT-based exact synthesis algorithms, our method calculates the matrix forms of logic circuits efficiently so that all optimal solutions are obtained in one pass. In particular, all solutions are expressed as 2-lookup tables (LUTs), rather than homogenous logic representations. Hence, different costs can be considered when selecting the optimal circuit. In experiments, we demonstrate that our method accelerates the runtime up to 6.9X while reducing timeout instances by up to 63%.
00:39 CET		AN EFFECTIVE AND EFFICIENT HEURISTIC FOR RATIONAL-WEIGHT THRESHOLD LOGIC GATE IDENTIFICATION Authors: Ting Yu Yeh, Yueh Cho and Yung Chih Chen, National Taiwan University of Science and Technology, TW Abstract In CMOS-based current mode realization, the threshold logic gate (TLG) implementation with rational weights has been shown to be more cost-effective than the conventional TLG implementation without rational weights. The existing method for the rational-weight TLG identification is an integer linear programming (ILP)-based method, which could suffer from inefficiency for a Boolean function with a large number of inputs. This paper presents a heuristic for rational-weight TLG identification. We observe that in the ILP formulation, many variables related to the rational weights are redundant according to the ILP solutions. Additionally, a rational-weight TLG could be transformed from a conventional TLG. Thus, the proposed method aims to identify the conventional TLG that can be transformed to a rational-weight TLG with lower implementation cost. We conducted the experiments on a set of TLGs with 4 ∼ 15 inputs. The results show that the proposed method has a competitive quality and is much more efficient, compared to the ILP-based method.
00:39 CET		FAST STA GRAPH PARTITIONING FRAMEWORK FOR MULTI-GPU ACCELERATION Authors: Guannan Guo¹, Tsung-Wei Huang² and Martin Wong³ ¹UIUC, US; ²University of Utah, US; ³The Chinese University of Hong Kong, HK Abstract Path-based Analysis (PBA) is a key process in Static Timing Analysis (STA) to reduce excessive slack pessimism. However, PBA can easily become the major performance bottleneck due to its extremely long execution time. To overcome this bottleneck, recent STA researches have proposed to accelerate PBA algorithms with manycore CPU and GPU parallelisms. However, GPU memory is rather limited when we compute PBA on large industrial designs with millions of gates. In this work, we introduce a new endpoint-oriented partitioning framework that can separate STA graphs and dispatch the PBA workload onto multiple GPUs. Our framework can quickly identify logic overlaps among endpoints and group endpoints based on the size of shared logic. We then recover graph partitions from the endpoint groups and offload independent PBA workloads to multiple GPUs. Experiments show that our framework can greatly accelerate the PBA process on designs with over 10M gates.
00:39 CET		TOFU: A TWO-STEP FLOORPLAN REFINEMENT FRAMEWORK FOR WHITESPACE REDUCTION Authors: Shixiong Kai¹, Chak-Wa Pui², Fangzhou Wang³, Jiang Shougao⁴, Bin Wang¹, Yu Huang⁵ and Jianye Hao⁶ ¹Huawei Noah's Ark Lab, CN; ²UniVista, CN; ³The Chinese University of Hong Kong, HK; ⁴Hisilicon, CN; ⁵HiSilicon, CN; ⁶Tianjin University, CN Abstract Floorplanning, as an early step in physical design, will greatly affect the PPA of the later stages. To achieve better performance while maintaining relatively the same chip size, the utilization of the generated floorplan needs to be high and constraints related to design rules, routability, power should be honored. In this paper, we propose a two-step framework, called TOFU, for floorplan whitespace reduction with fixed-outline and soft/pre-placed/hard modules modeled. Whitespace is first reduced by iteratively refining the locations of modules. Then the modules near whitespace will be changed into rectilinear shapes to further improve the utilization. To ensure the legality and quality of the intermediate floorplan during the refinement process, a constraint graph-based legalizer with a novel constraint graph construction method is proposed. Experimental results show that the whitespace of the initial floorplans generated by Corblivar can be reduced by about 70% on average and up to 90% in several cases. Moreover, the resulting wirelength is also 3% shorter due to a higher utilization.
00:39 CET		ROUTABILITY PREDICTION USING DEEP HIERARCHICAL CLASSIFICATION AND REGRESSION Authors: Daeyeon Kim¹, Jakang Lee² and Seokhyeong Kang² ¹POSTECH, KR; ²Pohang University of Science and Technology, KR Abstract In physical design, routability indicates whether the routing is feasible or not, and it can be evaluated after the post-route. Routability prediction can forecast the locations where design rule violations occur without routing and thus can speed up the design iterations by skipping the time-consuming routing tasks. In this paper, we define tile-level routability prediction as a pixel-wise regression problem. We then propose a deep hierarchical classification and regression (HCR) model that can detect hotspots and evaluate tile-level routability as a continuous value, rather than a binary classification (as in previous studies). The hierarchical inference flow can prevent bias toward predicting the majority samples in the data-imbalance problem. Furthermore, we introduce a training method for the proposed HCR model that uses Bayesian optimization to quickly find the ideal modeling parameters and incorporates transfer learning for the regression model. We achieved an R2 score of 0.71 for the regression and increased the F1 score in the binary classification by 94\% compared to that presented in the state-of-the-art. We also obtained a 0.890 Pearson correlation between the ground-truth and prediction values in the layout-level routability.
00:39 CET		ENABLING EFFICIENT DESIGN RULE CHECKING WITH GPU ACCELERATION Authors: Wei Zhong¹, Zhenhua Feng¹, Zhuolun He², Weimin Wang¹, Yuzhe Ma³ and Bei Yu² ¹Dalian University of Technology, CN; ²The Chinese University of Hong Kong, HK; ³The Hong Kong University of Science and Technology (Guangzhou), CN Abstract Design Rule Checking (DRC) is an essential part of the chip design flow, which ensures that manufacturing requirements are conformed to avoid a chip failure. With the rapid increase of design scales, DRC has been suffering from runtime overhead. To overcome this challenge, we propose to accelerate DRC algorithms by harnessing the power of graphics processing units (GPUs). Specifically, we first explore an efficient data transfer approach for geometry information of a layout. Then we investigate GPU-based scanline algorithms to accommodate both intra-polygon checking and intre-polygon checking based on the characteristics of the design rules. Experimental results show that the proposed GPU-accelerated method can substantially outperform a multi-threaded DRC algorithm using CPU. Compared with the baseline with 24 threads, we can achieve an average speedup of 36 times and 201 times for spacing rule checks and enclosing rule checks on a metal layer, respectively.
00:39 CET		MITIGATING LAYOUT DEPENDENT EFFECT-INDUCED TIMING RISK IN MULTI-ROW-HEIGHT DETAILED PLACEMENT Authors: Li-Chen Wang and Shao-Yun Fang, National Taiwan University of Science and Technology, TW Abstract With the development of advanced process technology, the electrical characteristic variation of MOSFET transistors has been seriously influenced by layout dependent effect (LDEs), such as the length of oxide diffusion (LOD) and the oxide-to-oxide spacing effect (OSE). Due to these LDEs, two cells of specific cell types may suffer from timing degradation when they are adjacently and closely placed with specific orientations. To mitigate the timing risk of critical paths and thus optimize the performance of a target design, this work focuses on multi-row-height detailed placement with cell flipping and cell shifting. We first develop an integer linear programming (ILP) formulation that can optimally solve the problem in terms of risky cell abutments and cell displacements. After that, a dynamic programming (DP)-based method is proposed that is much more efficient and can also derive near-optimal solutions. In addition, in contrast with ILP that can only derive solutions within acceptable runtimes by partitioning a design into sub-problems, the DP-based method is able to simultaneously consider the risky abutments on the critical paths of the entire circuit at a time. Experimental results shows the efficiency and effectiveness of the proposed DP-based approach.
00:39 CET		A TWO-STAGE PCB ROUTING ALGORITHM USING POLYGON-BASED DYNAMIC PARTITIONING AND MCTS Authors: Youbiao He¹, Hebi Li², Ge Luo² and Forrest Sheng Bao³ ¹Iowa state university, US; ²Iowa State University, US; ³Iowa State Univerity, US Abstract Routing is a vital step in printed circuit board (PCB) designs. With the rapid increase of design scales, manual routing has become very time-consuming. Previous works typically divide the problem into escape routing and area routing. However, existing escape routing approaches usually do not consider the quality of area routing among the chip components. As a result, the solutions to two subproblems do not always couple well. In addition, traditional escape routing mainly focuses on the connections between the regular ball grid array (BGA) of chip packages. However, real PCB designs usually contain non-BGA packages, making the PCB routing very challenging when applying the previous methods to solve it. To address the above problems, we propose a net-by-net two-stage PCB routing approach, including a Monte Carlo tree search (MCTS)-based global routing and an A*-based detailed routing approach. Furthermore, a polygon-based dynamic routable region partitioning mechanism is designed to minimize the gap between the global and detailed routing and to route for PCB designs with non-BGA packages. Experimental results show that our approach outperforms the state-of-the-art routers. Specifically, our algorithm successfully routes all the given test cases with shorter wirelengths while other state-of-the-art routers either fail to complete the routing or generate longer wires for each test case.
00:39 CET		DEEPTH: CHIP PLACEMENT WITH DEEP REINFORCEMENT LEARNING USING A THREE-HEAD POLICY NETWORK Authors: Dengwei Zhao, Shuai Yuan, Yanan Sun, Shikui Tu and Lei Xu, Shanghai Jiao Tong University, CN Abstract Modern very-large-scale integrated (VLSI) circuit placement with huge state space is a critical task for achieving layouts with high performance. Recently, reinforcement learning (RL) algorithms have made a promising breakthrough to dramatically save design time than human effort. However, the previous RL-based works either require a large dataset of chip placements for pre-training or produce illegal final placement solutions. In this paper, DeepTH, a three-head policy gradient placer, is proposed to learn from scratch without the need of pre-training, and generate superior chip floorplans. Graph neural network is initially adopted to extract the features from nodes and nets of chips for estimating the policy and value. To efficiently improve the quality of floorplans, a reconstruction head is employed in the RL network to recover the visual representation of the current placement, by enriching the extracted features of placement embedding. Besides, the reconstruction error is used as a bonus during training to encourage exploration while alleviating the sparse reward problem. Furthermore, the expert knowledge of floorplanning preference is embedded into the decision process to narrow down the potential action space. Experiment results on the ISPD2005 benchmark have shown that our method achieves $19.02\%$ HPWL improvement than the analytic placer DREAMPlace and 19.89\% improvement at least than the state-of-the-art RL algorithms.

S_S1 Pitches - Security of emerging technologies and machine learning

Date: Monday, 17 April 2023
Time: 16:30 - 16:57 CET

Time	Label	Presentation Title Authors
16:30 CET		PRIVACY-PRESERVING NEURAL REPRESENTATION FOR BRAIN-INSPIRED LEARNING Authors: Javier Roberto Rubalcava-Cortes¹, Alejandro , Hernandez Cano¹, Alejandra Citlalli Pacheco Tovarm¹, Farhad Imani², Rosario Cammarota³ and Mohsen Imani⁴ ¹Universidad Nacional Autonoma de Mexico, MX; ²University of Connecticut, US; ³Intel Labs, US; ⁴University of California Irvine, US Abstract In this paper, we propose BIPOD, a brain-inspired privacy-oriented machine learning. Our method rethinks privacypreserving mechanisms by looking at how the human brain provides effective privacy with minimal cost. BIPOD exploits hyperdimensional computing (HDC) as a neurally-inspired computational model. HDC is motivated by the observation that the human brain operates on high-dimensional data representations. In HDC, objects are thereby encoded with high-dimensional vectors, called hypervectors, which have thousands of elements. BIPOD exploits this encoding as a holographic projection with both cryptographic and randomization-based features. BIPOD encoding is performed using a set of brain keys that are generated randomly. Therefore, attackers cannot get encoded data without accessing the encoding keys. In addition, revealing the encoding keys does not directly translate to information loss. We enhance BIPOD encoding method to mathematically create perturbation on encoded neural patterns to ensure a limited amount of information can be extracted from the encoded data. Since BIPOD encoding is a part of the learning process, thus can be optimized together to provide the best trade-off between accuracy, privacy, and efficiency. Our evaluation on a wide range of applications shows that BIPOD privacy-preserving techniques result in 11.3× higher information privacy with no loss in classification accuracy. In addition, at the same quality of learning, BIPOD provides significantly higher information privacy compared to state-of state-of-the-art privacy-preserving techniques
16:33 CET		EXPLOITING SHORT APPLICATION LIFETIMES FOR LOW COST HARDWARE ENCRYPTION IN FLEXIBLE ELECTRONICS Authors: Nathaniel Bleier¹, Muhammad Mubarik¹, Suman Balaji², Francisco Rodriguez², Antony Sou², Scott White² and Rakesh Kumar¹ ¹UIUC, US; ²PragmatIC Semiconductor, GB Abstract Many emerging flexible electronics applications require hardware based encryption, but it is unclear if practical hardware-based encryption is possible for flexible applications due to stringent power requirements of these applications and higher area and power over heads of flexible technologies. In this work, we observe that the lifetime of many flexible applications is so small that often one key suffices for the entire lifetime. This means that, instead of generating keys and round keys in hardware, we can generate the round keys offline, and instead store these round keys directly in the engine. This eliminates the need for hardware for dynamic generation of round keys, which significantly reduces encryption overhead. This significant reduction in encryption overhead allows us to demonstrate the first practical flexible encryption engines. To prevent an adversary from reading out the stored round keys, we scramble the round keys before storing them in the ROM; camouflage cells are used to unscramble the keys before feeding them to logic. In spite of the unscrambling overhead, our encryption engines consume 27.4% lower power than the already heavily area and power-optimized baselines, while being 21.9% smaller on average.
16:36 CET		ATTACKING RERAM-BASED ARCHITECTURES USING REPEATED WRITES Authors: Biresh Kumar Joardar¹ and Krishnendu Chakrabarty² ¹University of Houston, US; ²Duke University, US Abstract Resistive random-access memory (ReRAM) have is a promising technology for both memory and for in-memory computing. However, these devices have security vulnerabilities that are yet to be adequately investigated. In this work, we identify one such vulnerability that exploits the write mechanism in ReRAMs. Whenever a cell/row is written, a constant bias is automatically applied to the remaining cells/rows to reduce sneak current. We develop a new attack (referred as WriteHammer) that exploits this process. By repeatedly exposing a subset of cells to this bias, WriteHammer can cause noticeable resistance drift in the victim ReRAM cells. Experimental results indicate that WriteHammer can cause up to 3.5X change in cell resistance by simply writing to the ReRAM cells
16:39 CET		SECURITY EVALUATION OF A HYBRID CMOS/MRAM ASCON HARDWARE IMPLEMENTATION Authors: Nathan Roussel, Olivier Potin, Jean-Max Dutertre and Jean-Baptiste Rigaud, Mines Saint-Etienne, CEA, Leti, Centre CMP F-13541 Gardanne, France, FR Abstract As the number of IoT objects is growing fast, power consumption and security become a major concern in the design of integrated circuits. Lightweight Cryptography (LWC) algorithms aim to secure the communications of these connected objects at the lowest energy impact. To reduce the energy footprint of cryptographic primitive, several LWC hardware implementations embedding hybrid CMOS/MRAM-based cells have been investi- gated. These architectures use the non-volatile characteristic of MRAM to store data manipulated in the algorithm computation. We provide in this work a security evaluation of a hybrid CMOS/MRAM hardware implementation of the A SCON cipher, a finalist of the National Institute of Standards and Technology LWC contest. We focus on a simulation flow using the current EDA tools capable of carrying out power analysis for side-channel attacks, for the purpose of assessing potential weaknesses of MRAM hybridization. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) are conducted on the post- route and parasitic annoted netlist of the design. The results show that the hybrid implementation does not significantly lower the security feature compared to a reference CMOS implementation.
16:42 CET		MANTIS: MACHINE LEARNING-BASED APPROXIMATE MODELING OF REDACTED INTEGRATED CIRCUITS Authors: Chaitali Sathe, Yiorgos Makris and Benjamin Carrion Schaefer, University of Texas at Dallas, US Abstract With most VLSI design companies now being fabless it is imperative to develop methods to protect their Intellectual Property (IP). One approach that has become very popular due to its relative simplicity and practicality is logic locking. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the VLSI design company delivers to the foundry which has now access to the entire design including the locking mechanism. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. One relatively new approach that has been coined as hardware redaction is to map a portion of the design to an embedded FPGA (eFPGA). The bitstream of the eFPGA now acts as the locking key. The fab now receives the design without the bitstream and hence, cannot reverse engineer the functionality of the design. The obvious drawbacks are the increase in design complexity and the area and performance overheads associated with the eFPGA. In this work we propose, to the best of our knowledge, the first attack on these type of new locking mechanisms by substituting the exact logic mapped onto the eFPGA by a synthesizable predictive model that replicates the behavior of the exact logic. We show that this approach is especially applicable in the context of approximate computing where hardware accelerators tolerate certain degree of errors at their outputs. Some examples include Digital Signal Processing (DSP) or image processing applications Experimental results show that our proposed approach is very effective finding suitable predictive models.
16:45 CET		LONG RANGE DETECTION OF EMANATION FROM HDMI CABLES USING CNN AND TRANSFER LEARNING Authors: Md Faizul Bari¹, Meghna Roy Chowdhury¹ and Shreyas Sen² ¹Purdue University, US; ²ECE, Purdue University, US Abstract The transition of data and clock signals between high and low states in electronic devices creates electromagnetic radiation according to Maxwell's equations. These unintentional emissions, called emanation, may have a significant correlation with the original information-carrying signal and form an information leakage source, bypassing secure cryptographic methods at both hardware and software levels. Information extraction exploiting compromising emanations poses a major threat to information security. Shielding the devices and cables along with setting a control perimeter for a sensitive facility are the most commonly used preventive measures. These countermeasures raise the research need for the longest detection range of exploitable emanation and the efficacy of commercial shielding. In this work, using data collected from 3 types of commercial HDMI cables (unshielded, single-shielded, and double-shielded) in an office environment, we have shown that the CNN-based detection method outperforms the traditional threshold-based detection method and improves the detection range from 4 m to 22.5 m for an iso-accuracy of ~95%. Also, for an iso-distance of 16 m, the CNN-based method provides ~100% accuracy, compared to ~88.5% using the threshold-based method. The significant performance boost is achieved by treating the FFT plots as images and training a residual neural network (ResNet) with the data so that it learns to identify the impulse-like emanation peaks even in the presence of other interfering signals. A comparison has been made among the emanation power from the 3 types of HDMI cables to judge the efficacy of multi-layer shielding. Finally, a distinction has been made between monitor contents, i.e., still image vs video, with an accuracy of 91.7% at a distance of 16 m. This distinction bridges the gap between emanation-based image and video reconstruction algorithms.
16:48 CET		ADVERSARIAL ATTACK ON HYPERDIMENSIONAL COMPUTING-BASED NLP APPLICATIONS Authors: Sizhe Zhang¹, Zhao Wang² and Xun Jiao¹ ¹Villanova University, US; ²University of Chicago, US Abstract The security and robustness of machine learning algorithms have become increasingly important as they are used in critical applications such as natural language processing (NLP), e.g., text-based spam detection. Recently, the emerging brain-inspired hyperdimensional computing (HDC), compared to deep learning methods, has shown advantages such as compact model size, energy efficiency, and capability of few-shot learning in various NLP applications. While HDC has been demonstrated to be vulnerable to adversarial attacks in image and audio input, there is currently no study on its adversarial security to NLP tasks, which is arguable one of the most suitable applications for HDC. In this paper, we present the first study on the adversarial attack of HDC-based NLP applications. By leveraging the unique properties in HDC, the similarity-based inference, we propose similarity-guided approaches to automatically generate adversarial text samples for HDC. Our approach is able to achieve up to 89% attack success rate. More importantly, by comparing with unguided brute-force approach, similarity-guided attack achieves a speedup of 2.4X in generating adversarial samples. Our work opens up new directions and challenges for future adversarially-robust HDC model design and optimization.
16:51 CET		A PRACTICAL REMOTE POWER ATTACK ON MACHINE LEARNING ACCELERATORS IN CLOUD FPGAS Authors: Shanquan Tian¹, Shayan Moini², Daniel Holcomb³, Russell Tessier⁴ and Jakub Szefer¹ ¹Yale University, US; ²School of Electrical and Computer Engineering, University of Massachusetts Amherst, US; ³UMass Amherst, US; ⁴University of Massachusetts, US Abstract The security and performance of FPGA-based accelerators play vital roles in today's cloud services. In addition to supporting convenient access to high-end FPGAs, cloud vendors and third-party developers now provide numerous FPGA accelerators for machine learning models. However, the security of accelerators developed for state-of-the-art Cloud FPGA environments has not been fully explored, since most remote accelerator attacks have been prototyped on local FPGA boards in lab settings, rather than in Cloud FPGA environments. To address existing research gaps, this work analyzes three existing machine learning accelerators developed in Xilinx Vitis to assess the potential threats of power attacks on accelerators in Amazon Web Services (AWS) F1 Cloud FPGA platforms, in a multi-tenant setting. The experiments show that malicious co-tenants in a multi-tenant setting can instantiate voltage sensing circuits as register-transfer level (RTL) kernels within the Vitis design environment to spy on co-tenant modules. A practical methodology for launching a practical remote power attack on Cloud FPGAs is also presented, which uses an enhanced time-to-digital (TDC) based voltage sensor.The TDC is used to capture power signatures, which are then used to identify power consumption spikes and observe activity patterns involving the FPGA shell, DRAM on the FPGA board, or the other co-tenant victim's accelerators. Voltage change patterns related to shell use and accelerators are then used to create a practical auto-triggered attack that can automatically detect when to capture voltage traces without the need for a hard-wired synchronization signal between victim and attacker. To address the novel threats presented in this work, this paper also discusses defenses that could be leveraged to secure multi-tenant Cloud FPGAs from power-based attacks.
16:54 CET		SCALABLE SCAN-CHAIN-BASED EXTRACTION OF NEURAL NETWORK MODELS Authors: Shui Jiang¹, Seetal Potluri² and Tsung-Yi Ho¹ ¹The Chinese University of Hong Kong, HK; ²North Carolina State University, US Abstract can chains have greatly improved hardware testability while introducing security breaches for confidential data. Scan-chain attacks have extended their scope from cryptoprocessors to AI edge devices. The recently proposed scan-chain-based neural network (NN) model extraction attack (ICCAD 2021) made it possible to achieve fine-grained extraction and is multiple orders of magnitude more efficient both in queries and accuracy than its coarse-grained mathematical counterparts. However, both query formulation complexity and constraint solver failures increase drastically with network depth/size. We demonstrate a more powerful adversary, who is capable of improving scalability while maintaining accuracy, by relaxing high-fidelity constraints to formulate an approximate-fidelity-based layer-constrained least-squares extraction using random queries. We conduct our extraction attack on neural network inference topologies of different depths and sizes, targeting the MNIST digit recognition task. The results show that our method outperforms the scan-chain attack proposed in ICCAD 2021 by an average increase in the extracted neural network's functional accuracy of ≈ 31% and 2−3 orders of reduction in queries. Furthermore, we demonstrated that our attack is highly effective even in the presence of countermeasures against adversarial samples.

BPA_1 Testing

Date: Tuesday, 18 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		DEVICE-AWARE TEST FOR BACK-HOPPING DEFECTS IN STT-MRAMS Authors: Sicong Yuan¹, Mottaqiallah Taouil², Moritz Fieback¹, Hanzhi Xun¹, Erik Marinissen³, Gouri Kar³, Siddharth Rao³, Sebastien Couet³ and Said Hamdioui² ¹TUDelft, Delft, The Netherlands, NL; ²Delft University of Technology, NL; ³IMEC, Leuven, Belgium, BE Abstract The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modeled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, the dedicated march test and Design-for-Test solutions are proposed.
00:39 CET		CORRECTNET: ROBUSTNESS ENHANCEMENT OF ANALOG IN-MEMORY COMPUTING FOR NEURAL NETWORKS BY ERROR SUPPRESSION AND COMPENSATION Authors: Amro Eldebiky¹, Grace Li Zhang², Georg Bocherer³, Bing Li¹ and Ulf Schlichtmann¹ ¹TU Munich, DE; ²TU Darmstadt, DE; ³Huawei Munich Research Center, DE Abstract The last decade has witnessed the breakthrough of deep neural networks (DNNs) in many fields. With the increasing depth of DNNs, hundreds of millions of multiply-and-accumulate (MAC) operations need to be executed. To accelerate such operations efficiently, analog in-memory computing platforms based on emerging devices, e.g., resistive RAM (RRAM), have been introduced. These acceleration platforms rely on analog properties of the devices and thus suffer from process variations and noise. Consequently, weights in neural networks configured into these platforms can deviate from the expected values, which may lead to feature errors and a significant degradation of inference accuracy. To address this issue, in this paper, we propose a framework to enhance the robustness of neural networks under variations and noise. First, a modified Lipschitz constant regularization is proposed during neural network training to suppress the amplification of errors propagated through network layers. Afterwards, error compensation is introduced at necessary locations determined by reinforcement learning to rescue the feature maps with remaining errors. Experimental results demonstrate that inference accuracy of neural networks can be recovered from as low as 1.69% under variations and noise back to more than 95% of their original accuracy, while the training and hardware cost are negligible.
00:39 CET		ASSESSING CONVOLUTIONAL NEURAL NETWORKS RELIABILITY THROUGH STATISTICAL FAULT INJECTIONS Authors: Annachiara Ruospo¹, Gabrile Gavarini¹, Corrado De Sio¹, Juan Guerrero Balaguera¹, Luca Sterpone¹, Matteo Sonza Reorda², Ernesto Sanchez¹, Riccardo Mariani³, Joseph Aribido⁴ and Jyotika Athavale⁴ ¹Politecnico di Torino, IT; ²Politecnico di Torino - DAUIN, IT; ³NVIDIA, IT; ⁴nvidia, US Abstract Assessing the reliability of modern devices running CNN algorithms is a very difficult task. Actually, the complexity of the state-of-the-art devices makes exhaustive Fault Injection (FI) campaigns impractical and typically out of the computational capabilities. A possible solution to this problem consists on resorting to statistical FI campaigns that allow to reduce the number of needed experiments by injecting only a significant part of it. Under specific hypothesis, statistical FIs guarantee an accurate picture of the problem, albeit selecting a reduced sample size. The main problems today are related to the choice of the sample size, the location of the faults, and the correct understanding of the assumptions with respect to the target system. The intent of this paper is twofold: first, we describe how to correctly specify statistical FIs for Convolutional Neural Networks; second, we propose a data analysis on the CNN param- eters that drastically reduces the number FIs needed to achieve statistically significant results without compromising the validity of the proposed method. The methodology is experimentally validated on two CNNs, ResNet-20 and MobileNetV2, and the results show that a statistical FI campaign on about 1.50% of the possible faults, provides a very precise information on the CNN reliability. The statistical results have been confirmed by the exhaustive FI campaigns on the same cases of study.

BPA_2 From Synthesis to application

Date: Tuesday, 18 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		EFFICIENT PARALLELIZATION OF 5G-PUSCH ON A SCALABLE RISC-V MANY-CORE PROCESSOR Authors: Marco Bertuletti¹, Yichao Zhang¹, Alessandro Vanelli-Coralli² and Luca Benini³ ¹ETH Zurich, CH; ²Universita' di Bologna and ETH Zurich, IT; ³Università di Bologna and ETH Zurich, IT Abstract 5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typically offloaded to specialized hardware accelerators. However, the trend toward software-defined radio-access networks demands flexible, programmable architectures. In this paper, we explore the software design, parallelization and optimization of the key kernels of the lower physical layer (PHY) for physical uplink shared channel (PUSCH) reception on MemPool and TeraPool, two manycore systems having respectively 256 and 1024 small and efficient RISC-V cores with a large shared L1 data memory. PUSCH processing is demanding and strictly time-constrained, it represents a challenge for the baseband processors, and it is also common to most of the uplink channels. Our analysis thus generalizes to the entire lower PHY of the uplink receiver at gNodeB (gNB). Based on the evaluation of the computational effort (in multiply-accumulate operations) required by the PUSCH algorithmic stages, we focus on the parallel implementation of the dominant kernels, namely fast Fourier transform, matrix-matrix multiplication, and matrix decomposition kernels for the solution of linear systems. Our optimized parallel kernels achieve respectively on MemPool and TeraPool speedups of 211, 225, 158, and 762, 880, 722, at high utilization (0.81, 0.89, 0.71, and 0.74, 0.88, 0.71), comparable a single-core serial execution, moving a step closer toward a full-software PUSCH implementation.
00:39 CET		NARROWING THE SYNTHESIS GAP: ACADEMIC FPGA SYNTHESIS IS CATCHING UP WITH THE INDUSTRY Authors: Benjamin Barzen¹, Arya Reais-Parsi¹, Eddie Hung², Minwoo Kang¹, Alan Mishchenko¹, Jonathan Greene¹ and John Wawrzynek¹ ¹UC Berkeley, US; ²FPG-eh Research and University of British Columbia, CA Abstract Historically, open-source FPGA synthesis and technology mapping tools have been considered far inferior to industry-standard tools. We show that this is no longer true. Improvements in recent years to Yosys (Verilog elaborator) and ABC (technology mapper) have resulted in substantially better performance, evident in both the reduction of area utilization and the increase in the maximum achievable clock frequency. More specifically, we describe how Yosys and ABC9 --- a set of feature additions to ABC --- were integrated such that technology mapping now has a complete view of the circuit, including support for hard blocks (e.g. carry chains) and multiple clock domains for timing-aware mapping. We demonstrate how these improvements accumulate in dramatically better synthesis results, with Yosys-ABC9 reducing the delay gap from 30\% to 0\% on our small FPGA target for the commonly used VTR Benchmark, thus matching Vivado's performance in terms of maximum clock frequency. We also measured the performance on a selection of circuits from OpenCores as well as literature, comparing the results produced by Yosys-ABC, Yosys-ABC9 and Vivado.
00:39 CET		SAGEROUTE: SYNERGISTIC ANALOG ROUTING CONSIDERING GEOMETRIC AND ELECTRICAL CONSTRAINTS WITH MANUAL DESIGN COMPATIBILITY Authors: Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang and Ru Huang, Peking University, CN Abstract Routing is critical to the post-layout performance of analog circuits. As modern analog layouts need to consider both geometric constraints (e.g., design rules and low bending constraints) and electrical constraints (e.g., electromigration (EM), IR drop, symmetry, etc.), analog routing becomes increasingly challenging to investigate the complicated design space. Most previous work has focused only on geometric constraints or basic electrical constraints, lacking holistic and systematic investigation. Such an approach is far from typical manual design practice and can not guarantee post-layout performance on real-world designs. In this work, we propose SAGERoute, a synergistic routing framework taking both geometric and electrical constraints into consideration. Through Steiner tree based wire sizing and guided detailed routing, the framework can generate high-quality routing solutions efficiently under versatile constraints on real-world analog designs.

BPA_5 Benchmarking and Verification

Date: Tuesday, 18 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		BENCHMARKING LARGE LANGUAGE MODELS FOR AUTOMATED VERILOG RTL CODE GENERATION Authors: Shailja Thakur¹, Baleegh Ahmad¹, Zhenxing Fan¹, Hammond Pearce¹, Benjamin Tan², Ramesh Karri³, Brendan Dolan-Gavitt¹ and Siddharth Garg¹ ¹New York University, US; ²University of Calgary, CA; ³NYU, US Abstract Automating the hardware design process could obviate a significant amount of human error from design engineering and lead to fewer design errors. Verilog is a popular hardware description language (HDL) to model digital systems. Thus, automatically generating Verilog models is an appealing option and the focus of this paper. We explore and characterize the ability of emerging open-source large language models (LLMs) for use with Verilog given their ability to write coherent and functionally correct code across other programming languages. We fine-tune pre-trained LLMs on Verilog dataset collected from various sources such as GitHub and Verilog textbooks. We constructed an evaluation framework comprising test benches, design prompts of varying difficulties, and a flow to test the generated Verilog code. Our findings show that fine-tuned LLMs outperform a commercial LLM on basic hardware designs and can complete a variety of intermediate- and advanced-level hardware designs. We release training and evaluation scripts and model checkpoints available as open-source contributions: [blind for review].
00:39 CET		PROCESSOR VERIFICATION USING SYMBOLIC EXECUTION: A RISC-V CASE-STUDY Authors: Niklas Bruns¹, Vladimir Herdt² and Rolf Drechsler³ ¹University of Bremen, DE; ²DFKI, DE; ³University of Bremen/DFKI, DE Abstract We propose to leverage state-of-the-art symbolic execution techniques from the Software (SW) domain for processor verification at the Register-Transfer Level (RTL). In particular, we utilize an Instruction Set Simulator (ISS) as a reference model and integrate it with the RTL processor under test in a co-simulation setting. We then leverage the symbolic execution engine KLEE to perform a symbolic exploration that searches for functional mismatches between the ISS and RTL processor. To ensure a comprehensive verification process, symbolic values are used to represent the instructions and also to initialize the register values of the ISS and processor. As a case study, we present results on the verification of the open source RISC-V based MicroRV32 processor, using the ISS of the open source RISC-V VP as a reference model. Our results demonstrate that modern symbolic execution techniques are applicable to a full scale processor co-simulation in the embedded domain and are very effective in finding bugs in the RTL core.
00:39 CET		PERSPECTOR: BENCHMARKING BENCHMARK SUITES Authors: Sandeep Kumar¹, Abhisek Panda² and Smruti R. Sarangi¹ ¹IIT Delhi, IN; ²Indian Institute of Technology, IN Abstract Estimating the quality of a benchmark suite is a non-trivial task. A poorly selected or improperly configured benchmark suite can present a distorted picture of the performance capabilities of the evaluated framework. With computing venturing into new domains, the total number of benchmark suites available is increasing by the day. Researchers must evaluate these suites quickly and decisively for their effective use. We present Perspector, a novel tool to quantify the performance of a benchmark suite. Perspector comprises novel metrics to characterize the quality of a benchmark suite. It provides a mathematical framework for capturing some qualitative suggestions and observations made in prior work. The metrics are generic and domain agnostic. Furthermore, our tool can be used to compare the efficacy of one suite vis-a-vis other benchmark suites, systematically and rigorously create a suite of workloads, and appropriately tune them for a target system.

BPA_8 Machine Learning techniques for embedded systems

Date: Tuesday, 18 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		PRADA: POINT CLOUD RECOGNITION ACCELERATION VIA DYNAMIC APPROXIMATION Authors: Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing and Xiaoyao Liang, Shanghai Jiao Tong University, CN Abstract Recent point cloud recognition (PCR) tasks tend to utilize deep neural network (DNN) for better accuracy. Still, the computational intensity of DNN makes them far from real-time processing, given the fast-increasing number of points that need to be processed. Because the point cloud represents 3D-shaped discrete objects in the physical world using a mass of points, the points tend for an uneven distribution in the view space that exposes strong clustering possibility and local pairs' similarities. Based on this observation, this paper proposes PRADA, an algorithm-architecture co-design that can accelerate PCR while reserving its accuracy. We propose dynamic approximation, which can approximate and eliminate the similar local pairs' computations and recover their results by copying key local pairs' features for PCR speedup without losing accuracy. For accuracy good, we further propose an advanced re-clustering technique to maximize the similarity between local pairs. For performance good, we then propose a PRADA architecture that can be built on any conventional DNN accelerator to dynamically approximate the similarity and skip the redundant DNN computation with memory accesses at the same time. Our experiments on a wide variety of datasets show that PRADA averagely achieves 4.2x, 4.9x, 7.1x, and 12.2x speedup over Mesorasi, V100 GPU, 1080TI GPU, and Xeon CPU with negligible accuracy loss.
00:39 CET		FEDERATED LEARNING WITH HETEROGENEOUS MODELS FOR ON-DEVICE MALWARE DETECTION IN IOT NETWORKS Authors: sanket shukla¹, Setareh Rafatirad², Houman Homayoun³ and Sai Manoj Pudukotai Dinakarrao⁴ ¹George mason university, US; ²University of California, Davis, US; ³University of California Davis, US; ⁴George Mason University, US Abstract IoT devices have been widely deployed in a vast number of applications to facilitate smart technology, increased portability, and seamless connectivity. Despite being widely adopted, security in IoT devices is often considered an afterthought due to resource and cost constraints. Among multiple security threats, malware attacks are observed to be a pivotal threat to IoT devices. Considering the spread of IoT devices and the threats they experience over time, deploying a static malware detector that is trained offline seems to be an ineffective solution. On the other hand, on-device learning is an expensive or infeasible option due to the limited available resources on IoT devices. To overcome these challenges, this work employs ‘Federated Learning' (FL) which enables timely updates to the malware detection models for increased security while mitigating the high communication or data storage overhead of centralized cloud approaches. Federated learning allows training machine learning models with decentralized data while preserving its privacy by design. However, one of the challenges with the FL is that the ondevice models are required to be homogeneous, which may not be true in the case of networked IoT systems. As a panacea, we introduce a methodology to unify the models in the cloud with minimal overheads and an impact on on-device malware detection. We evaluate the proposed technique against homogeneous models in networked IoT systems encompassing Raspberry Pi devices. The experimental results and system efficiency analysis indicate that end-to-end training time is just 1.12× higher than traditional FL, testing latency is 1.63× faster, and malware detection performance is improved by 7% to 13% for resource-constrained IoT devices.
00:39 CET		GENETIC ALGORITHM-BASED FRAMEWORK FOR LAYER-FUSED SCHEDULING OF MULTIPLE DNNS ON MULTI-CORE SYSTEMS Authors: Sebastian Karl¹, Arne Symons², Nael Fasfous³ and Marian Verhelst² ¹TU Munich, DE; ²KU Leuven, BE; ³BMW AG, DE Abstract Heterogeneous multi-core architectures are becoming a popular design choice to accelerate the inference of modern deep neural networks (DNNs). This trend allows for more flexible mappings onto the cores, but shifts the challenge to keeping all cores busy due to limited network parallelism. To this extent, layer-fused processing, where several layers are mapped simultaneously to an architecture and executed in a depth-first fashion, has shown promising opportunities to maximize core utilization. However, SotA mapping frameworks fail to efficiently map layer-fused DNNs onto heterogeneous multi-core architectures due to ignoring 1.) on-chip weight traffic and 2.) inter-core communication congestion. This work tackles these shortcomings by introducing a weight memory manager (WMM), which manages the weights present in a core and models the cost of re-fetching weights. Secondly, the inter-core communication (ICC) of feature data is modelled through a limited-bandwidth bus, and optimized through a contention-aware scheduler (CAS). Relying on these models, a genetic algorithm is developed to optimally schedule different DNN layers across the different cores. The impact of our enhanced modelling, core allocation and scheduling capabilities is shown in several experiments and demonstrates a decrease of 52% resp. 38% in latency, resp. energy when mapping a multi-DNN inference, consisting of ResNet-18, MobileNet-V2 and Tiny YOLO V2, on a heterogeneous multi-core platform compared to iso-area homogeneous architectures.

S_A3 Applications of Emerging Technologies and Computing Paradigms

Date: Tuesday, 18 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		HDGIM: HYPERDIMENSIONAL GENOME SEQUENCE MATCHING ON UNRELIABLE HIGHLY-SCALED FEFET Authors: Hamza Errahmouni Barkam¹, Sanggeon Yun², Paul Genssler³, Zhuowen Zou⁴, Che-Kai Liu⁵, Hussam Amrouch³ and Mohsen Imani⁶ ¹University Of California Irvine, US; ²Kookmin University, KR; ³University of Stuttgart, DE; ⁴UCI, US; ⁵Zhejiang Univsersity, CN; ⁶University of California Irvine, US Abstract This is the first work to i) define theoretically the memorization capacity of Hyperdimensional (HDC) hyperparameters and ii) present a reliable application for highly-scaled (down to merely 3nm), multi-bit Ferroelectric FET (FeFET) technology. FeFET is one of the up-and-coming emerging technologies that is not only fully compatible with the existing CMOS but does hold the promise to realize ultra-efficient and compact Compute-in-Memory (CiM) architectures. Nevertheless, FeFETs struggle with the 10nm thickness of the Ferroelectric (FE) layer. This makes scaling profoundly challenging if not impossible because thinner FE significantly shrinks the memory window leading to large error probabilities that cannot be tolerated. To overcome these challenges, we propose HDGIM, a hyperdimensional computing framework catered to FeFET in the context of genome sequence matching. Genome Sequence Matching is known to have high computational costs, primarily due to huge data movement that substantially overwhelms von-Neuman architectures. On the one hand, our cross-layer FeFET reliability modeling (starting from device physics to circuits) accurately captures the impact of FE scaling on errors induced by process variation and inherent stochasticity in multi-bit FeFETs. On the other hand, our HDC learning framework iteratively adapts by using two models, a full-precision, ideal model for training and a quantized, noisy version for validation and inference. Our results demonstrate that highly-scaled FeFET realizing 3-bit and even 4-bit can withstand any noise given high dimensionality during inference. If we consider the noise during model adjustment, we can improve the inherent robustness compared to adding noise during the matching process.
00:39 CET		QUANTUM MEASUREMENT DISCRIMINATION USING CUMULATIVE DISTRIBUTION FUNCTIONS Authors: Zachery Utt, Daniel Volya and Prabhat Mishra, University of Florida, US Abstract Quantum computing can efficiently solve many hard problems significantly faster than its classical counterpart. Quantum measurement is one of the critical steps in quantum computing that determines the probabilities associated with qubit states after conducting several circuit executions and measurements. As a mesoscopic quantum system, real quantum computers are prone to noise. Therefore, a major challenge in quantum measurement is how to correctly interpret the noisy results of a quantum computer. While there are promising classification based solutions, they either produce incorrect results (misclassify) or require many measurements (expensive). In this paper, we present an efficient technique to estimate a qubit's state through analysis of probability distributions of post-measurement data. Specifically, it estimates the state of a qubit using cumulative distribution functions to compare the measured distribution of a sample with the distributions of basis states. Our experimental results demonstrate a drastic reduction (78%) in single qubit readout error. It also provides significant reduction (12%) when used to boost existing multi-qubit discriminator models.
00:39 CET		EXTENDING THE DESIGN SPACE OF DYNAMIC QUANTUM CIRCUITS FOR TOFFOLI BASED NETWORK Authors: Abhoy Kole¹, Arighna Deb², Kamalika Datta¹ and Rolf Drechsler³ ¹German Research Centre for Artificial Intelligence (DFKI), DE; ²School of Electronics Engineering KIIT DU, IN; ³University of Bremen/DFKI, DE Abstract Recent advances in fault tolerant quantum systems allow to perform non-unitary operations like mid-circuit measurement, active reset and classically controlled gate operations in addition to the existing unitary gate operations. Real quantum devices that support these non-unitary operations enable us to execute a new class of quantum circuits, known as Dynamic Quantum Circuits (DQC). This helps to enhance the scalability, thereby allowing execution of quantum circuits comprising of many qubits by using at least two qubits. Recently DQC realizations of multi-qubit Quantum Phase Estimation and Bernstein–Vazirani algorithms have been demonstrated in two separate experiments. However the dynamic transformation of complex quantum circuits consisting of Toffoli gate operations have not been explored yet. This motivates us to: (a) explore the dynamic realization of Toffoli gates by extending the design space of DQC for Toffoli networks, and (b) propose a general dynamic transformation algorithm for the first time to the best of our knowledge. More precisely we introduce two dynamic transformation schemes (dynamic-1 and dynamic-2) for Toffoli gates, that differ with respect to the required number of classically controlled gate operations. For evaluation, we consider the Deutsch-Jozsa (DJ) algorithm composed of one or more Toffoli gates. Experimental results demonstrate that dynamic DJ circuits based on dynamic-2 Toffoli realization scheme provides better computational accuracy over the dynamic-1 scheme. Further the proposed dynamic transformation scheme is general and can also be applied to non-Toffoli quantum circuits.
00:39 CET		AI-BASED DETECTION OF DROPLETS AND BUBBLES IN DIGITAL MICROFLUIDIC BIOCHIPS Authors: Jianan Xu, Wenjie Fan, Georgi Plamenov Tanev, Jan Madsen and Luca Pezzarossa, TU Denmark, DK Abstract Digital microfluidic biochips exploit the electrowetting on dielectric effect to move and manipulate microliter-sized liquid droplets on a planar surface. This technology has the potential to automate and miniaturize biochemical processes, but reliability is often an issue. The droplets may get temporarily stuck or gas bubbles may impede their movement leading to a disruption of the process being executed. However, if the position and size of the droplets and bubbles are known at run-time, these undesired effects can be easily mitigated by the biochip control system. This paper presents an AI-based computer vision solution for real-time detection of droplets and bubbles in DMF biochips and its implementation that supports cloud-based deployment. The detection is based on the YOLOv5 framework in combination with custom pre and post-processing techniques. The YOLOv5 neural network is trained using our own data set consisting of 5115 images. The solution is able to detect droplets and bubbles with real-time speed and high accuracy and to differentiate between them even in the extreme case where bubbles coexist with transparent droplets.
00:39 CET		SPLIT ADDITIVE MANUFACTURING FOR PRINTED NEUROMORPHIC CIRCUITS Authors: Haibin Zhao¹, Michael Hefenbrock², Michael Beigl¹ and Mehdi Tahoori¹ ¹Karlsruhe Institute of Technology, DE; ²RevoAI, DE Abstract Printed and flexible electronics promises smart devices for application domains, such as smart fast moving consumer goods and medical wearables, which are generally untouchable by conventional rigid silicon technologies. This is due to their remarkable properties such as flexibility, non-toxic materials, and having low-cost per area. Combined with neuromorphic computing, printed neuromorphic circuits pose an attractive solution for these application domains. Particularly, the additive printing technologies can reduce large amount of fabrication complexities and costs. On the one hand, high-throughput additive printing processes, such as roll-to-roll printing, can reduce the per-device fabrication time and cost. On the other hand, jet-printing can provide point-of-use customization at the expense of lower fabrication throughput. In this work, we propose a machine learning based design framework, that respects the objective and physical constraints of split additive manufacturing for printed neuromorphic circuits. With the proposed framework, multiple printed neural networks are trained jointly with the aim to sensibly combine multiple fabrication techniques (e.g., roll-to-roll and jet-printing). This should lead to a cost-effective fabrication of multiple different printed neuromorphic circuits and achieve high fabrication throughput, lower cost, and point-of-use customization.
00:39 CET		PIMPR: PIM-BASED PERSONALIZED RECOMMENDATION WITH HETEROGENEOUS MEMORY HIERARCHY Authors: Tao Yang¹, Hui Ma¹, Yilong Zhao¹, Fangxin Liu², Zhezhi He³, Xiaoli Sun⁴ and Li Jiang¹ ¹Shanghai Jiao Tong University, CN; ²Shanghai Jiaotong University, CN; ³School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, CN; ⁴Institute of Scientific and Technical Information of Zhejiang Province, CN Abstract Deep learning-based personalized recommendation models (DLRMs) are dominating AI tasks in data centers. The performance bottleneck of typical DLRMs mainly lies in the memory-bounded embedding layers. Resistive Random Access Memory (ReRAM)-based Processing-in-memory (PIM) architecture is a natural fit for DLRMs thanks to its in-situ computation and high computational density. However, it remains two challenges before DLRMs fully embrace PIM architectures: 1) The size of DLRM's embedding tables can reach tens of GBs, far beyond the memory capacity of typical ReRAM chips. 2) The irregular sparsity conveyed in the embedding layers is difficult to exploit in PIM architecture. In this paper, we present the first PIM-based DLRM accelerator named PIMPR. PIMPR has a heterogeneous memory hierarchy—ReRAM crossbar-based PIM modules serve as the computing caches with high computing parallelism, while DIMM modules are able to hold the entire embedding table—leveraging the data locality of DLRM's embedding layers. Moreover, we propose a runtime strategy to skip the useless calculation induced by the sparsity and an offline strategy to balance the workload of each ReRAM crossbar. Compared to the state-of-the-art DLRM accelerator SPACE and TRiM, PIMPR achieves on average 2.02× and 1.79× speedup, 5.6×, and 5.1× energy reduction, respectively
00:39 CET		FSL-HD: ACCELERATING FEW-SHOT LEARNING ON RERAM USING HYPERDIMENSIONAL COMPUTING Authors: Weihong Xu¹, Jaeyoung Kang¹ and Tajana Rosing² ¹University of California San Diego, US; ²UCSD, US Abstract Few-shot learning (FSL) is a promising meta-learning paradigm that trains classification models on the fly with a few training sam- ples. However, existing FSL classifiers are either computationally expensive, or are not accurate enough. In this work, we propose an efficient in-memory FSL classifier, FSL-HD, based on hyper- dimensional computing (HDC) that achieves state-of-the-art FSL accuracy and efficiency. We devise an HDC-based FSL framework with efficient HDC encoding and search to reduce high complexity caused by the large HDC dimensionality. Also, we design a scal- able in-memory architecture to accelerate FSL-HD on ReRAM with distributed dataflow and organization that maximizes the data paral- lelism and hardware utilization. The evaluation shows that FSL-HD achieves 4.2% higher accuracy compared to other FSL classifiers. FSL-HD achieves 100 − 1000× better energy efficiency and 9 − 66× speedup over the CPU and GPU baselines. Moreover, FSL-HD is more accurate, scalable and 2.5× faster than the state-of-the-art ReRAM-based FSL design, SAPIENS, while requiring 85% less area.
00:39 CET		HD-I-IOT: HYPERDIMENSIONAL COMPUTING FOR RESILIENT INDUSTRIAL INTERNET OF THINGS ANALYTICS Authors: Onat Gungor¹, Tajana Rosing² and Baris Aksanli³ ¹UCSD & SDSU, US; ²UCSD, US; ³San Diego State University, US Abstract Industrial Internet of Things (I-IoT) enables fully automated production systems by continuously monitoring devices and analyzing collected data. Machine learning (ML) methods are commonly utilized for data analytics in such systems. Cyberattacks are a grave threat to I-IoT as they can manipulate legitimate inputs, corrupting ML predictions and causing disruptions in the production systems. Hyperdimensional (HD) computing is a brain-inspired ML method that has been shown to be sufficiently accurate while being extremely robust, fast, and energy-efficient. In this work, we use non-linear encoding-based HD for intelligent fault diagnosis against different adversarial attacks. Our black-box adversarial attacks first train a substitute model and create perturbed test instances using this trained model. These examples are then transferred to the target models. The change in the classification accuracy is measured as the difference before and after the attacks. This change measures the resiliency of a learning method. Our experiments show that HD leads to a more resilient and lightweight learning solution than the state-of-the-art deep learning methods. HD has up to 67.5% higher resiliency compared to the state-of-the-art methods while being up to 25.1× faster to train.
00:39 CET		SARA: AN EFFICIENT AND CONFIGURABLE SOFTMAX ENGINE FOR ATTENTION MODEL WITH VERSATILE RRAM CROSSBAR Authors: Yifeng Zhai¹, Bing Li¹ and Bonan Yan² ¹Capital Normal University, CN; ²Peking University, CN Abstract RRAM has been exploited to accelerate the vector-matrix multiplication (VMM)-dominated neural network applications as the most promising in-memory computing technology. However, the state-of-the-art neural network models widely adopt the stacked attention mechanism, which has intensive softmax operations that pose the execution efficiency bottleneck. In this work, we propose SARA, which conists of an efficient RRAM-based softmax engine by exploiting the versatility of RRAM crossbar and a fine-grained pipeline to realize the high-efficiency RRAM-based accelerator for the attention neural networks. Moreover, SARA is precision configurable to achieve the high-accuracy inference performance. The experimental results evaluated on several attention models show SARA achieves up to 30.63× and 1.31× computing efficiency improvement over the GPU and the state-of-the-art RRAM-based Attention Accelerators, respectively.
00:39 CET		VALUE-BASED REINFORCEMENT LEARNING USING EFFICIENT HYPERDIMENSIONAL COMPUTING Authors: Yang Ni¹, Danny Abraham¹, Mariam Issa¹, Yeseong Kim², Pietro Mercati³ and Mohsen Imani⁴ ¹University of California, Irvine, US; ²DGIST, KR; ³Intel Labs, US; ⁴University of California Irvine, US Abstract Reinforcement Learning (RL) has opened up new opportunities to solve a wide range of complex decision-making tasks. However, modern RL algorithms, e.g., Deep Q-Learning, are based on deep neural networks, resulting in high computational costs. In this paper, we propose QHD, an off-policy value-based Hyperdimensional Reinforcement Learning, that mimics brain properties toward robust and real-time learning. QHD relies on a lightweight brain-inspired model to learn an optimal policy in an unknown environment. We first develop a novel mathematical foundation and encoding module that maps state-action space into high-dimensional space. We accordingly develop a hyperdimensional regression model to approximate the Q-value function. The QHD-powered agent makes decisions by comparing the Q-values of each possible action. We evaluate the effect of the different RL training batch sizes and local memory capacity on the QHD quality of learning. Our QHD is also capable of online learning with tiny local memory capacity, which can be as small as the training batch size. QHD provides real-time learning by further decreasing the memory capacity and batch size. This makes QHD suitable for highly-efficient reinforcement learning with great potential for online and real-time learning. Our solution also supports a small experience replay batch size that provides a 12.3X speedup compared to DQN while ensuring minimal quality loss. Our evaluation shows QHD capability for real-time learning, providing a 34.6X speedup and significantly better quality of learning than state-of-the-art deep RL algorithms.
00:39 CET		DROPDIM: INCORPORATING EFFICIENT UNCERTAINTY ESTIMATION INTO HYPERDIMENSIONAL COMPUTING Authors: Yang Ni¹, Hanning Chen¹, Prathyush Poduval², Pietro Mercati³ and Mohsen Imani⁴ ¹University of California, Irvine, US; ²CMTC, Department of Physics, University of Maryland, US; ³Intel Labs, US; ⁴University of California Irvine, US Abstract Recent advancement in emerging brain-inspired computing has pointed out a promising path to Machine Learning (ML) algorithms with high efficiency. Particularly, research in the field of HyperDimensional Computing (HDC) brings orders of magnitude speedup to both ML model training and inference compared to their deep learning counterparts. However, current HDC-based ML algorithms generally lack uncertainty estimation, despite having shown good results in various practical applications and outstanding energy efficiency. On the other hand, existing solutions such as the Bayesian Neural Networks (BNN) are generally much slower than the regular neural networks and lead to high energy consumption. In this paper, we propose a hyperdimensional Bayesian framework called DropDim, which enables uncertainty estimation for the HDC-based regression algorithm. The core of our framework is a specially designed HDC encoder that maps input features to the high dimensional space with an extra layer of randomness, i.e., a small number of dimensions are randomly dropped for each input. Our key insight is that by using this encoder, DropDim implements Bayesian inference while maintaining the efficiency advantage of HDC. We verify our framework with both toy regression tasks and real-world datasets. The results on CPU show that DropDim provides comparable uncertainty estimations while also achieving significant speedup compared to the BNN baseline. Our implementation on FPGA shows that DropDim provides 84X (3740X) better energy efficiency for training (inference).

S_D3 Hardware accelerators and memory subsystems

Date: Tuesday, 18 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		UVMMU: HARDWARE-OFFLOADED PAGE MIGRATION FOR HETEROGENEOUS COMPUTING Authors: Jihun Park¹, Donghun Jeong² and Jungrae Kim² ¹dept. of Artificial Intelligence, Sungkyunkwan University, KR; ²Sungkyunkwan University, KR Abstract In a heterogeneous computing system with multiple memories, placing data near its current processing unit and migrating data over time can significantly improve performance. GPU vendors have introduced Unified Memory (UM) to automate data migrations between CPU and GPU memories and support memory over-subscription. Although UM improves software programmability, it can incur high costs due to its software-based migration. We propose a novel architecture to offload the migration to hardware and minimize UM overheads. Unified Virtual Memory Management Unit (UVMMU) detects access to remote memories and migrates pages without software intervention. By replacing page faults and software handling with hardware offloading, UVMMU can reduce the page migration latency to a few μs. Our evaluation shows that UVMMU can achieve 1.59× and 2.40× speed-ups over the state-of-the-art UM solutions for no over-subscription and 150% over-subscription, respectively.
00:39 CET		ARRAYFLEX: A SYSTOLIC ARRAY ARCHITECTURE WITH CONFIGURABLE TRANSPARENT PIPELINING Authors: Christodoulos Peltekis¹, Dionysios Filippas¹, Giorgos Dimitrakopoulos¹, Chrysostomos Nicopoulos² and Dionisios Pnevmatikatos³ ¹Democritus University of Thrace, GR; ²University of Cyprus, CY; ³National TU Athens & ICCS, GR Abstract Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performance and energy efficiency. In practice, the convolutions of each CNN layer are mapped to a matrix multiplication that includes all input features and kernels of each layer and is computed using a systolic array. In this work, we focus on the design of a systolic array with configurable pipeline with the goal to select an optimal pipeline configuration for each CNN layer. The proposed systolic array, called ArrayFlex, can operate in normal, or in shallow pipeline mode, thus balancing the execution time in cycles and the operating clock frequency. By selecting the appropriate pipeline configuration per CNN layer, ArrayFlex reduces the inference latency of state-of-the-art CNNs by 11%, on average, as compared to a traditional fixed-pipeline systolic array. Most importantly, this result is achieved while using 13%-23% less power, for the same applications, thus offering a combined energy-delay-product efficiency between 1.4x and 1.8x.
00:39 CET		FASTRW: A DATAFLOW-EFFICIENT AND MEMORY-AWARE ACCELERATOR FOR GRAPH RANDOM WALK ON FPGAS Authors: Yingxue Gao, teng wang, Lei Gong, Chao Wang, Xi Li and Xuehai Zhou, University of Science and Technology of China, CN Abstract Graph random walk (GRW) sampling is becoming increasingly important with the widespread popularity of graph applications. It involves some walkers that wander through the graph to capture the desirable properties and reduce the size of the original graph. However, previous research suffers long sampling latency and severe memory access bottlenecks due to intrinsic data dependency and irregular vertex distribution. This paper proposes FastRW, a dedicated accelerator to fully release GRW acceleration on FPGAs. FastRW first schedules walkers' execution to address data dependency and mask long sampling latency. Then, FastRW leverages pipeline specialization and bit-level optimization to customize a processing engine with five modules and achieve a pipelining dataflow. Finally, to alleviate the differential access caused by irregular vertex distribution, FastRW implements a hybrid memory architecture to provide parallel access ports according to the vertex's degree. We evaluate FastRW with two classic GRW algorithms on a wide range of real-world graph datasets. The experimental results show that FastRW achieves a speedup of 14.13x on average over the system running on a 2x8-core Intel CPU. FastRW also achieves 3.28x~198.24x energy efficiency over the architecture implemented on V100 GPU.
00:39 CET		TWIN ECC: A DATA DUPLICATION BASED ECC FOR STRONG DRAM ERROR RESILIENCE Authors: Hyeong Kon Bae¹, Myung Jae Chung¹, Young-Ho Gong² and Sung Woo Chung¹ ¹Korea University, KR; ²Kwangwoon University, KR Abstract With the continuous scaling of process technology, DRAM reliability has become a critical challenge in modern memory systems. Currently, DRAM memory systems for servers have employed ECC DIMMs with a single error correction and double error detection (SECDED) code. However, the SECDED code is insufficient to ensure DRAM reliability since memory systems become more susceptible to errors. Though various studies have proposed multi-bit correctable ECC schemes, such ECC schemes cause performance and/or storage overhead. To minimize performance degradation while providing strong error resilience, in this paper, we propose Twin ECC, a low-cost memory protection scheme through data duplication. In a 512-bit data, Twin ECC duplicates meaningful data into meaningless zeros. Since ‘1'→‘0' error pattern is dominant in DRAM cells, Twin ECC provides strong error resilience by performing bitwise OR operations between the original meaningful data and duplicated data. After the bitwise OR operations, Twin ECC adopts the SECDED code for further enhancing data protection. Our evaluations show that Twin ECC reduces the system failure probability by average 64.8%, 56.9%, and 49.6%, when the portion of ‘1'→‘0' error is 100%, 90%, and 80%, respectively, while causing only 0.7% performance overhead and no storage overhead compared to the baseline ECC DIMM with SECDED code.
00:39 CET		AIDING TO MULTIMEDIA ACCELERATORS: A HARDWARE DESIGN FOR EFFICIENT ROUNDING OF BINARY FLOATING POINT NUMBERS Authors: MAHENDRA RATHOR, Vishesh Mishra and Urbi Chatterjee, Indian Institute of Technology Kanpur, IN Abstract Hardware accelerators for multimedia applications such as JPEG image compression and video compression are quite popular due to their capability of enhancing overall performance and system throughput. The core of essentially all lossy compression techniques is the quantization process. In the quantization process, rounding is performed to obtain integer values for the compressed images and video frames. The recent studies in the photo forensic research has revealed that the direct rounding e.g. round up or round down of floating point numbers results into some compression artifacts such as 'JPEG dimples'. Therefore in the compression process, performing rounding to the nearest integer value is important especially for High Dynamic Range (HDR) photography and videography. Since rounding to the nearest integer is a data-intensive process, hence its realization as a dedicated hardware is imperative to enhance overall performance. This paper presents a novel high performance hardware architecture for performing rounding of binary floating point numbers to the nearest integer. Additionally, an optimized version of the basic hardware design is also proposed. The proposed optimized version provides 6.7% reduction in area and 7.4% reduction in power consumption in comparison to the proposed basic architecture. Furthermore, the integration of the proposed floating point rounding hardware with the design flow of the computing kernel of the compression processor is also discussed in the paper. The proposed rounding hardware architecture and the integrated design with the computing kernel of compression process have been implemented on an Intel FPGA. The average resource overhead due to this integration is reported to be less than 1%.
00:39 CET		CRSPU: EXPLOIT COMMONALITY OF REGULAR SPARSITY TO SUPPORT VARIOUS CONVOLUTIONS ON SYSTOLIC ARRAYS Authors: Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Xin Ju and Chunyuan Zhang, Colledge of Computer, National University of Defense Technology, CN Abstract Dilated convolution (DCONV) and transposed convolution (TCONV) are involved in the training of GANs and CNNs and introduces numerous regular zero-spaces into the feature maps or kernels. Existing accelerators typically pre-reorganize the zero-spaces, and then perform sparse computation to accelerate them, resulting in huge hardware resource overhead and control complexity. While the systolic array has proven advantages when it comes to accelerating convolutions, countermeasures for deploying DCONV and TCONV on systolic arrays are rarely proposed. Therefore, we opt to improve the traditional im2col algorithm to make full use of the regular sparsity and avoid data reorganization, thereby facilitating the use of systolic arrays in this context. Public Dimension Compression and Similar Sparsity Merging mechanisms are also designed to implement sparse computing, eliminating unnecessary computing caused by zero-spaces. We propose a systolic array-based processing unit, named CRSPU, that achieves 7736 GOPS peak throughput, with an area efficiency of 2046.56 GOPS/mm² and a PE efficiency of 30.22 GOPS/PE. Experiments show that compared with the dense and sparse versions of the state-of-the-art baseline accelerator GANPU, CRSPU achieves 11.20× and 8.43× speedup in the training performance of CycleGAN, improves PE efficiency by 58.80× and 44.23×, and reduces the on-chip bandwidth of DCONV and TCONV by up to 31.66% and 54.63% respectively. The average PE utilization of CRSPU on various GAN models can reach 93.27%. Furthermore, CRSPU's ability to avoid zero-space data reorganization represents a huge advantage for bandwidth-unfriendly accelerators.
00:39 CET		CLAP: LOCALITY AWARE AND PARALLEL TRIANGLE COUNTING WITH CONTENT ADDRESSABLE MEMORY Authors: Tianyu Fu¹, Chiyue Wei², Zhenhua Zhu², Shang Yang², Zhongming Yu³, Guohao Dai², Huazhong Yang² and Yu Wang² ¹Ph. D. Tsinghua University, CN; ²Tsinghua University, CN; ³University of California, San Diego, US Abstract Triangle counting (TC) is one of the most fundamental graph analysis tools with a wide range of applications. Modern triangle counting algorithms traverse the graph and perform set intersections of neighbor sets to find triangles. However, existing triangle counting approaches suffer from the heavy off-chip memory access and set intersection overhead. Thus, we propose CLAP, the first content addressable memory (CAM) based triangle counting architecture with the software and hardware co-optimizations. To reduce off-chip memory access and the number of set intersections, we propose the first force-based node index reorder method. It is a universal reorder framework that simultaneously optimizes both data locality and the computation amount. Compared with random node indices, the reorder method reduces the off-chip memory access and the set intersections by 61% and 64%, respectively, while providing 2.19x end-to-end speedup. To improve the set intersection parallelism, we propose the first CAM-based triangle counting architecture under chip area constraints. We enable high parallel set by translating it into content search on CAM with full parallelism. Thus the time complexity of the set intersection reduces from O(m + n) or O(n log m) to O(n). Extensive experiments on real-world graphs show that CLAP achieves 39x, 27x, and 78x speedup over state-of-the-art CPU, GPU, and processing-in-memory baselines, respectively.
00:39 CET		ATOMIC BUT LAZY UPDATING WITH MEMORY-MAPPED FILES FOR PERSISTENT MEMORY Authors: Qisheng Jiang, Lei Jia and Chundong Wang, ShanghaiTech University, CN Abstract Applications memory-map file data stored in the persistent memory and expect both high performance and failure atomicity. State-of-the-art NOVA and Libnvmmio guarantee failure atomicity but yield inferior performance. They enforce data staying fresh and intact at the mapped addresses by continually updating the data there, thereby incurring severe write amplifications. They also lack the adaptability to dynamic workloads and entail housekeeping overheads with complex designs. We hence propose Acumen with a group of reflection pages managed for a mapped file. Using a simplistic bitmap to track fine-grained data slices, Acumen makes a reflection page and a mapped file page pair to alternately carry updates to achieve failure atomicity. Only on receiving a read request will it deploy valid data from reflection pages into target mapped file pages. The cost of deployment is amortized over subsequent read requests. Experiments show that Acumen significantly outperforms NOVA and Libnvmmio with consistently higher performance in serving a variety of workloads.
00:39 CET		OUT-OF-STEP PIPELINE FOR GATHER/SCATTER INSTRUCTIONS Authors: Yi Ge¹, Katsuhiro Yoda¹, Makiko Ito¹, Toshiyuki Ichiba¹, Takahide Yoshikawa¹, Ryota Shioya² and Masahiro Goshima³ ¹Fujitsu Limited, JP; ²University of Tokyo, JP; ³National Institute of Informatics, JP Abstract Recently, demand for large sparse matrix calculation has been increasing as symbolized by the HPCG benchmark. However, wider SIMD units suffer from low scalability of gather/ scatter instructions that inevitably appear in sparse matrix calculations. The scalability of gather/scatter instruction is low because a v elements wide gather/scatter instruction takes O(v) cycles to access L1D with O(1) ports. We address this problem with a multibank L1D (MBL1D) and a newly proposed out-of-step pipeline. Though MBL1D with O(v) banks potentially enables access to non-contiguous v elements in O(1) cycles, it causes bank conflicts and resultant instruction rescheduling diminishes the gain. The out-of-step pipeline avoids this instruction rescheduling by allowing element operations of SIMD instructions to proceed out of step with each other with small FIFO buffers. We evaluate our pipeline on a fully cycle-accurate simulator with a sparse matrix-vector product kernel for various sparse matrices from the HPCG benchmark and the SuiteSparse Matrix Collection in the SELL-C-σ format. The results show that, for the SIMD width of 1024 bit, it achieves 76.8% efficiency to an ideal model with fullport L1D free from bank conflicts, and 1.87 times improvement over a model of a conventional pipeline with MBL1D.
00:39 CET		MEMPOOL MEETS SYSTOLIC: FLEXIBLE SYSTOLIC COMPUTATION IN A LARGE SHARED-MEMORY PROCESSOR CLUSTER Authors: Samuel Riedel¹, Gua Hao Khov¹, Sergio Mazzola², Matheus Cavalcante¹, Renzo Andri³ and Luca Benini⁴ ¹ETH Zurich, CH; ²ETH Zürich, CH; ³Huawei Zurich Research Center, CH; ⁴Università di Bologna and ETH Zurich, IT Abstract Systolic arrays and shared-memory manycore clusters are two widely used architectural templates to accelerate highly parallel workloads. Yet, they offer vastly different trade-offs. Systolic arrays achieve exceptional performance for workloads with regular dataflow at the cost of an extremely rigid architecture and programming model. On the other hand, shared-memory manycore systems are well suited for a wide range of workloads and easy to program. However, dataflow has to be managed explicitly, incurring a runtime overhead. This work combines the best of both worlds by extending a general-purpose shared-memory manycore cluster with a systolic overlay. The combination allows for efficient execution for systolically computable kernels while keeping the flexibility of the programmable shared-memory system for irregular kernels. In our hybrid architecture, the small and efficient RISC-V processor cores act as the systolic array's processing elements (PEs). The cluster's shared memory is used to implement a memory-mapped queue network capable of establishing any systolic topology among all PEs. We propose two instruction set architecture extensions enabling native and autonomous queue communication and implement them in MemPool, an open-source manycore architecture featuring 256 cores and 1 MiB of shared L1 memory. Namely, the Xqueue extension enables single-instruction access to any shared memory queue, while the queue-linked register extension enables autonomous access to the queues, relieving the cores of communication instructions and letting them focus on computation. Our hybrid approach allows configuring different systolic topologies at execution time. We analyze the trade-offs between systolic and shared-memory implementations and run hybrid systolic-shared-memory computations. Through the hardware extensions and hybrid execution scheme, the hybrid architecture achieves up to 194 GOPS or 132 GOPS/W on a 2D convolution, outperforming the highly-optimized shared-memory implementation by 17%.
00:39 CET		NOVEL EFFICIENT SYNONYM HANDLING MECHANISM FOR VIRTUAL-REAL CACHE HIERARCHY Authors: Varun Venkitaraman¹, Ashok Sathyan¹, Shrihari Deshmukh¹ and Virendra Singh² ¹Indian Institute of Technology, Bombay, IN; ²IIT Bombay, IN Abstract Optimizing L1 caches for latency is critical to improving the system's performance. Servicing a memory request involves address translation, set indexing, tag comparisons and data access. Generally, virtually indexed physically tagged (VIPT) caches are used as L1 caches since we can perform TLB lookups and set indexing parallelly, resulting in reduced L1 cache access latency. However, a TLB lookup precedes every L1 cache access. The TLB lookups significantly contribute to the system's total power consumption. Implementing virtually indexed virtually tagged (VIVT) caches appears to be an attractive option for reducing energy consumption due to TLB lookups. Though the solution seems attractive, VIVT caches are plagued with the issue of synonyms. Previous research has proposed several approaches for resolving synonyms to facilitate the implementation of VIVT L1 caches. However, the proposed techniques introduce new hardware structures in the cache hierarchy to detect and resolve synonyms. Instead of adding another hardware structure to the cache hierarchy, we propose a new cache hierarchy design that modifies the last-level cache's tag array to detect and resolve synonyms. Doing so eliminates the need for a new hardware structure to handle synonyms, thereby not adding to the already existing critical path length. Our proposed synonym handling mechanism is speculation-free and eliminates the need for tag comparisons for a synonym L1 cache re-access. Overall, our proposed scheme significantly reduces the dynamic energy consumption of the cache hierarchy, making it energy-efficient. Furthermore, our proposed cache hierarchy design can directly replace existing ones without requiring modifications to the core or software end.
00:39 CET		TURBULENCE: COMPLEXITY-EFFECTIVE OUT-OF-ORDER EXECUTION ON GPU WITH DISTANCE-BASED ISA Authors: Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai and Ryota Shioya, University of Tokyo, JP Abstract A graphic processing unit (GPU) is a processor that achieves high throughput by exploiting data parallelism. One key feature that enables high throughput is multithreaded execution, in which a GPU generally executes many threads simultaneously to hide various latencies. As a result, GPUs generally do not perform expensive out-of-order execution to hide latency within threads. However, We found that many GPU workloads also contain instruction-level parallelism, which can be extracted through outof-order execution to provide additional performance improvement opportunities. We propose the TURBULENCE architecture for very low-cost out-of-order execution on GPUs. TURBULENCE consists of a novel ISA that introduces the concept of referencing operands by inter-instruction distance instead of register numbers, and a novel microarchitecture that executes the novel ISA. This distance-based operand has the property that it does not cause any false dependencies. Using this property, we achieve costeffective out-of-order execution on GPUs without introducing expensive hardware such as a rename logic and a load-store queue. The simulation results show that TURBULENCE improves performance by 17.6% without an increase in energy consumption compared to an existing GPU.

S_E2 Modelling, verification and timing analysis of cyber-physical systems

Date: Tuesday, 18 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		IMPACTTRACER: ROOT CAUSE LOCALIZATION IN MICROSERVICES BASED ON FAULT PROPAGATION MODELING Authors: Ru Xie¹, Jing Yang², Jingying Li² and Liming Wang² ¹Institute of Information Engineering,CAS;Unversity of Chinese Academy of Sciences, CN; ²Institute of Information Engineering,CAS, CN Abstract Microservice architecture is embraced by a growing number of enterprises due to the benefits of modularity and flexibility. However, being composed of numerous interdependent microservices, it is prone to cascading failures and is afflicted by the arising problem of troubleshooting, which entails arduous efforts to identify the root cause node and ensure service availability. Previous works use call graph to characterize causality relationships of microservices but not completely and comprehensively, leading to an insufficient search of potential root cause nodes and consequently poor accuracy in culprit localization. In this paper, we propose ImpactTracer to address the above problems. ImpactTracer builds impact graph to provide a complete view of fault propagation in microservices and uses a novel backward tracing algorithm that exhaustively traverses the impact graph to identify the root cause node accurately. Extensive experiments on a real-world dataset demonstrate that ImpactTracer is effective in identifying the root cause node and outperforms the state-of-the-art methods by at least 73%, significantly facilitating troubleshooting in microservices.
00:39 CET		PUMPCHANNEL: AN EFFICIENT AND SECURE COMMUNICATION CHANNEL FOR TRUSTED EXECUTION ENVIRONMENT ON ARM-FPGA EMBEDDED SOC Authors: Jingquan Ge, Yuekang Li, Yang Liu, Yaowen Zheng, Yi Liu and Lida Zhao, Nanyang Technological University, SG Abstract ARM TrustZone separates the system into the rich execution environment (REE) and the trusted execution environment (TEE). Data can be exchanged between REE and TEE through the communication channel, which is based on shared memory and can be accessed by both REE and TEE. Therefore, when the REE OS kernel is untrusted, the security of the communication channel cannot be guaranteed. The proposed schemes to protect the communication channel have high performance overhead and are not secure enough. In this paper, we propose PumpChannel, an efficient and secure communication channel implemented on ARM-FPGA embedded SoC. PumpChannel avoids the use of secret keys, but utilizes a hardware and software collaborative pump to enhance the security and performance of the communication channel. Besides, PumpChannel implements a hardware-based hook integrity monitor to ensure the integrity of all hook codes. Security and performance evaluation results show that PumpChannel is more secure than the encrypted channel countermeasures and has better performance than all other schemes.
00:39 CET		ON THE DEGREE OF PARALLELISM IN REAL-TIME SCHEDULING OF DAG TASKS Authors: Qingqiang He¹, Nan Guan², Mingsong Lv¹ and Zonghua Gu³ ¹The Hong Kong Polytechnic University, HK; ²City University of Hong Kong, HK; ³Zhejiang Univ, CN Abstract Real-time scheduling and analysis of parallel tasks modeled as directed acyclic graphs (DAG) have been intensively studied in recent years. The degree of parallelism of DAG tasks is an important characterization in scheduling. This paper revisits the definition and the computing algorithms for the degree of parallelism of DAG tasks, and clarifies some misunderstandings regarding the degree of parallelism which exist in real-time literature. Based on the degree of the parallelism, we propose a real-time scheduling approach for DAG tasks, which is quite simple but rather effective and outperforms the state-of-the-art by a considerable margin.
00:39 CET		TIMING PREDICTABILITY FOR SOME/IP-BASED SERVICE-ORIENTED AUTOMOTIVE IN-VEHICLE NETWORKS Authors: Enrico Fraccaroli¹, Prachi Joshi², Shengjie Xu¹, Khaja Shazzad², Markus Jochim² and Samarjit Chakraborty³ ¹University of North Carolina at Chapel Hill, US; ²General Motors, R&D, US; ³UNC Chapel Hill, US Abstract In-vehicle network architectures are evolving from a typical signal-based client-server paradigm to a service-oriented one, introducing flexibility for software updates and upgrades. While signal-based networks are static by nature, service-oriented ones can more easily evolve during and after the design phase. As a result, service-oriented protocols are spreading through several layers of in-vehicle networks. While applications like infotainment are less sensitive to delays, others like sensing and control have more stringent timing and reliability requirements. Hence, wider adoption of service-oriented protocols requires timing analyzability and predictability problems to be addressed, which are more challenging than in their signal-oriented counterparts. In service-oriented architectures, the discovery phase defines how clients find their required services. The time required to complete the discovery phase is an important parameter since it determines the readiness of a sub-system or even the vehicle. In this paper, we develop a formal timing analysis of the discovery phase of SOME/IP, an emerging service-oriented protocol considered for adoption by automotive OEMs and suppliers.
00:39 CET		ANALYSIS AND OPTIMIZATION OF WORST-CASE TIME DISPARITY IN CAUSE-EFFECT CHAINS Authors: Xu Jiang¹, xiantong Luo¹, Nan Guan², Zheng Dong³, Shao-Shan Liu⁴ and Wang Yi⁵ ¹Northeastern University, CN; ²City University of Hong Kong, HK; ³Wayne State University, US; ⁴BeyonCa, CN; ⁵Uppsala University, SE Abstract An important and common timing requirement in autonomous system is that when some component receives data originated from different sensors, the time difference among the timestamps of the corresponding raw data must be in a certain range, so that information from different sensors can be correctly synchronized and fused. In this paper, we present analysis techniques to bound the worst-case time disparity (maximum difference among the timestamps of all stimulus of an output) in cause-effect chains. In particular, we take the fork-join structures into consideration, and show that the worst-case time disparity could also be significant even for data tokens produced by the same sensor. This result suggests that data fusion after long processing pipelines should be avoided to meet such requirements. Moreover, we present a solution to reduce the worst-case time disparity by designing buffers with proper size. Experiments are conducted to show the correctness and effectiveness of both our analysis techniques and design.
00:39 CET		DATA FRESHNESS OPTIMIZATION ON NETWORKED INTERMITTENT SYSTEMS Authors: Hao-Jan Huang¹, Wen Sheng Lim², Chia-Heng Tu¹, Chun-Feng Wu³ and Yuan-Hao Chang⁴ ¹National Cheng Kung University, TW; ²National Taiwan University (NTU), TW; ³National Yang Ming Chiao Tung University, TW; ⁴Academia Sinica, TW Abstract A networked intermittent system (NIS) is often deployed in the field for environmental monitoring, where sink nodes are responsible for relaying the data captured by sensors to a central system. To evaluate the quality of the captured monitoring data, Age of Information (AoI) is adopted to quantify the freshness of the data received by the central server. As the sink nodes are powered by ambient energy sources (e.g., solar and wind), the energy-efficient design of the sink nodes is crucial in order to improve the system-wide AoI. This work proposes the energy-efficient sink node design to save energy and extend system uptime. We devise an AoI-aware data forwarding algorithm based on the branch-and-bound (B&B) paradigm for deriving the optimal solution offline. In addition, an AoI-aware data forwarding algorithm is developed to approximate the optimal solution during runtime. The experimental results show that our solution can greatly improve the average data freshness for 148% against existing well-known strategies and achieves 91% performance of the optimal solution. Compared with the state-of-the-art algorithm, our energy-efficient design can deliver better A^3oI results by up to 9.6%.
00:39 CET		A SAFETY-GUARANTEED FRAMEWORK FOR NEURAL-NETWORK-BASED PLANNERS IN CONNECTED VEHICLES UNDER COMMUNICATION DISTURBANCE Authors: Kevin Kai-Chun Chang¹, Xiangguo Liu², Chung-Wei Lin¹, Chao Huang³ and Qi Zhu² ¹National Taiwan University, TW; ²Northwestern University, US; ³University of Liverpool, GB Abstract Neural-network-based (NN-based) planners have been increasingly used to enhance the performance of planning for autonomous vehicles. However, it is often difficult for NN-based planners to balance efficiency and safety in complicated scenarios, especially under real-world communication disturbance. To tackle this challenge, we present a safety-guaranteed framework for NN-based planners in connected vehicle environments with communication disturbance. Given an NN-based planner with no safety-guarantee, the framework generates a robust compound planner embedding the NN-based planner to ensure the overall system safety. Moreover, with the aid of an information filter for imperfect communication and an aggressive approach for the estimation of the unsafe set, the compound planner could achieve similar or better efficiency than the given NN-based planner. A comprehensive case study of unprotected left-turn and extensive simulations demonstrate the effectiveness of our framework.
00:39 CET		CO-DESIGN OF TOPOLOGY, SCHEDULING, AND PATH PLANNING IN AUTOMATED WAREHOUSES Authors: Christopher Leet¹, Chanwook Oh¹, Michele Lora², Sven Koenig¹ and Pierluigi Nuzzo¹ ¹University of Southern California, US; ²University of Verona, IT Abstract We address the warehouse servicing problem (WSP) in automated warehouses, which use teams of mobile agents to bring products from shelves to packing stations. Given a list of products, the WSP amounts to finding a plan for a team of agents which brings every product on the list to a station within a given timeframe. The WSP consists of four subproblems, concerning what tasks to perform (task formulation), who will perform them (task allocation), and when (scheduling) and how (path planning) to perform them. These subproblems are NP-hard individually and more complex in combination. The difficulty of the WSP is compounded by the scale of automated warehouses, which frequently use teams of hundreds of agents. In this paper, we present a methodology that can solve the WSP at such scales. We introduce a novel, contract-based design framework which decomposes an automated warehouse into traffic system components. By assigning each of these components a contract describing the traffic flows it can support, we can synthesize a traffic flow satisfying a given WSP instance. Component-wise search-based path planning is then used to transform this traffic flow into a plan for discrete agents in a modular way. Evaluation shows that this methodology can solve WSP instances on real automated warehouses.
00:39 CET		POLYGLOT MODAL MODELS THROUGH LINGUA FRANCA Authors: Alexander Schulz-Rosengarten¹, Reinhard von Hanxleden¹, Marten Lohstroh², Soroush Bateni³ and Edward Lee⁴ ¹Dept. of Computer Science, Kiel University, DE; ²University of California, Berkeley, US; ³University of Texas at Dallas, US; ⁴UC Berkeley, US Abstract Complex software systems often feature distinct modes of operation, each designed to handle a particular scenario that may require the system to respond in a certain way. Breaking down system behavior into mutually exclusive modes and discrete transitions between modes is a commonly used strategy to reduce implementation complexity and promote code readability. However, such capabilities often come in the form of self-contained domain specific languages or language-specific frameworks. The work in this paper aims to bring the advantages of modal models to mainstream programming languages, by following the polyglot coordination approach of Lingua Franca ( LF ), in which verbatim target code (e. g., C, C++, Python, Typescript, or Rust) is encapsulated in composable reactive components called reactors. Reactors can form a dataflow networks, be triggered by timed as well as sporadic events, execute concurrently, and be distributed across nodes on a network. With modal models in LF , we introduce a lean extension to the concept of reactors that enables the coordination of reactive tasks based on modes of operation. The implementation of modal reactors outlined in this paper generalizes to any LF-supported language with only modest modifications to the generic runtime system.
00:39 CET		DEL: DYNAMIC SYMBOLIC EXECUTION-BASED LIFTER FOR ENHANCED LOW-LEVEL INTERMEDIATE REPRESENTATION Authors: Hany Abdelmaksoud¹, Zain A. H. Hammadeh¹, Goerschwin Fey² and Daniel Luedtke¹ ¹German Aerospace Center (DLR), DE; ²TU Hamburg, DE Abstract Analyzing safety and timing on Low-Level Intermediate Representation (LLIR) is preferable over source-code and binary-code levels. However, the expressiveness of the generated LLIR challenges the efficiency of the applied analysis. This work develops an approach that lifts binaries into an enhanced LLVM IR including indirect jumps. The proposed lifter combines both static and dynamic methods and strives to fully recover the Control-Flow Graph (CFG) of the program. Using Satisfiability Modulo Theories (SMT) supported by memory and register models, our lifter dynamically symbolically executes IR instructions after translating them into SMT expressions. Accuracy and scalability of the lifter are studied on a benchmark from the literature. The proposed lifter resolves all indirect jumps and fully recovers the CFG of a case study that static lifters like RetDec and Angr failed. Also, our lifter achieves100% code coverage of the benchmark, unlike purely Dynamic lifters. Even when scaling up the code, the lifter effectively recovers the CFG.
00:39 CET		WCET ANALYSIS OF SHARED CACHES IN MULTI-CORE ARCHITECTURES USING EVENT-ARRIVAL CURVES Authors: Thilo Fischer and Heiko Falk, Hamburg University of Technology, DE Abstract The worst-case behavior of shared caches in multi-core systems is difficult to predict due to the effects of inter-core interference. This uncertainty can lead to large over-estimations of the worst-case execution time (WCET). In this paper, we propose a novel analysis approach for shared caches using the LRU replacement policy. We quantify inter-core cache interference by modelling cache accesses as event streams and show how an event-arrival curve can be derived from a low-level representation of the program code. Thus, inter-core cache interference may be expressed as a function of time. By analyzing the duration between accesses to a cache block, it is possible to bound the inter-core interference and classify accesses as cache hits or potential misses. We implemented this classification approach in a WCET analyzer and evaluated its performance for dual-core and quad-core systems using several cache configurations. The proposed analysis yielded similar WCET performance to a partitioned cache, with a median WCET increase of only 4% to 11%. Furthermore, the proposed analysis was able to outperform a partitioned cache by up to 26% in some cases. The analysis overhead of the proposed techniques was just 6 minutes on average for quad-core systems.
00:39 CET		RESOURCE OPTIMIZATION WITH 5G CONFIGURED GRANT SCHEDULING FOR REAL-TIME APPLICATIONS Authors: Yungang Pan¹, Rouhollah Mahfouzi¹, Soheil Samii², Petru Eles² and Zebo Peng² ¹Linköping University, SE; ²Linkoping University, SE Abstract 5G is expected to support ultra-reliable low latency communication (URLLC) to enable real-time applications such as industrial automation and control. 5G configured grant (CG) scheduling features a pre-allocated periodicity-based scheduling approach which reduces control signaling time and guarantees service quality. Although this enables 5G to support hard real-time periodic traffics, efficiently synthesizing the schedule and achieving high resource efficiency while serving multiple traffics is still an open problem. To address this problem, we first formulate it using satisfiability modulo theories (SMT) so that an SMT-solver can be used to generate the optimal solution. For enhancing scalability, two efficient heuristic approaches are proposed. We conduct extensive experiments to evaluate the scalability and performance of our proposed algorithms. The experiments demonstrate the effectiveness of the proposed technique.
00:39 CET		ADAPTIVE: AGENT-BASED LEARNING FOR BOUNDING TIME IN MIXED-CRITICALITY SYSTEMS Authors: Behnaz Ranjbar, Ali Hosseinghorban and Akash Kumar, TU Dresden, DE Abstract In Mixed-Criticality (MC) systems, the high Worst-Case Execution Time (WCET) of a task is a pessimistic bound, the maximum execution time of the task under all circumstances, while the low WCET should be close to the actual execution time of most instances of the task to improve utilization and Quality-of-Service (QoS). Most MC systems consider a static low WCET for each task which cannot adapt to dynamism at run-time. In this regard, we consider the run-time behavior of tasks and propose a learning-based approach that dynamically monitors the tasks' execution times and adapts the low WCETs to determine the ideal trade-off between mode-switches, utilization, and QoS. Based on our observations on running embedded real-time benchmarks on a real platform, the proposed scheme improves the QoS by 16.4% on average, while reducing the utilization waste by 17.7%, on average, compared to state-of-the-art works.

S_T2 Test methods and dependability

Date: Tuesday, 18 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		IMPROVING RELIABILITY OF SPIKING NEURAL NETWORKS THROUGH FAULT AWARE THRESHOLD VOLTAGE OPTIMIZATION Authors: Ayesha Siddique and Khaza Anuarul Hoque, University of Missouri, US Abstract Spiking neural networks have made breakthroughs in computer vision by lending themselves to neuromorphic hardware. However, the neuromorphic hardware lacks parallelism and hence, limits the throughput and hardware acceleration of SNNs on edge devices. To address this problem, many systolic-array SNN accelerators (systolicSNNs) have been proposed recently, but their reliability is still a major concern. In this paper, we first extensively analyze the impact of permanent faults on the SystolicSNNs. Then, we present a novel fault mitigation method, i.e., fault-aware threshold voltage optimization in retraining (FalVolt). FalVolt optimizes the threshold voltage for each layer in retraining to achieve the classification accuracy close to the baseline in the presence of faults. To demonstrate the effectiveness of our proposed mitigation, we classify both static (i.e., MNIST) and neuromorphic datasets (i.e., N-MNIST and DVS Gesture) on a 256x256 systolicSNN with stuck-at faults. We empirically show that the classification accuracy of a systolicSNN drops significantly even at extremely low fault rates (as low as 0.012%). Our proposed FalVolt mitigation method improves the performance of systolicSNNs by enabling them to operate at fault rates of up to 60%, with a negligible drop in classification accuracy (as low as 0.1%). Our results show that FalVolt is 2x faster compared to other state-of-the-art techniques common in artificial neural networks (ANNs), such as fault-aware pruning and retraining without threshold voltage optimization.
00:39 CET		AUTOMATED AND AGILE DESIGN OF LAYOUT HOTSPOT DETECTOR VIA NEURAL ARCHITECTURE SEARCH Authors: Zihao Chen¹, Fan Yang¹, Li Shang² and Xuan Zeng¹ ¹Fudan University, CN; ²fudan university, CN Abstract This paper presents a neural architecture search scheme for chip layout hotspot detection. In this work, hotspot detectors, in the form of neural networks, are modeled as weighted directed acyclic graphs. A variational autoencoder maps the discrete graph topological space into a continuous embedding space. Bayesian Optimization performs neural architecture search in this embedding space, where an architecture performance predictor is employed to accelerate the search process. Experimental studies on ICCAD 2012 and ICCAD 2019 Contest benchmarks demonstrate that, the proposed scheme significantly improves the agility of previous neural architecture search schemes, and generates hotspot detectors with competitive detection accuracy, false alarm rate, and inference time.
00:39 CET		UPHEAVING SELF-HEATING EFFECTS FROM TRANSISTOR TO CIRCUIT LEVEL USING CONVENTIONAL EDA TOOL FLOWS Authors: Florian Klemme¹, Sami Salamin² and Hussam Amrouch¹ ¹University of Stuttgart, DE; ²Hyperstone, DE Abstract In this work, we are the first to demonstrate how well-established EDA tool flows can be employed to upheave Self-Heating Effects (SHE) from individual devices at the transistor level all the way up to complete large circuits at the final layout (i.e., GDS-II) level. Transistor SHE imposes an ever-growing reliability challenge due to the continuous shrinking of geometries alongside the non-ideal voltage scaling in advanced technology nodes. The challenge is largely exacerbated when more confined 3D structures are adopted to build transistors such as upcoming Nanosheet FETs and Ribbon FETs. By employing increasingly-confined structures and materials of poorer thermal conductance, heat arising within the transistor's channel is trapped inside and cannot escape. This leads to accelerated defect generation and, if not considered carefully, a profound risk to IC reliability. Due to the lack of EDA tool flows that can consider SHE, circuit designers are forced to take pessimistic worst-case assumptions (obtained at the transistor level) to ensure reliability of the complete chip for the entire projected lifetime - at the cost of sub-optimal circuit designs and considerable efficiency losses. Our work paves the way for designers to estimate less pessimistic (i.e., small yet sufficient) safety margins for their circuits leading to higher efficiency without compromising reliability. Further, it provides new perspectives and opens new doors to estimate and optimize reliability correctly in the presence of emerging SHE challenge through identifying early the weak spots and failure sources across the design.
00:39 CET		BUILT-IN SELF-TEST AND BUILT-IN SELF-REPAIR STRATEGIES WITHOUT GOLDEN SIGNATURE FOR COMPUTING IN-MEMORY Authors: Yu-Chih Tsai¹, Wen-chien Ting², Chia-Chun Wang¹, chia-cheng chang¹ and Ren-Shuo Liu¹ ¹EE, National Tsing Hua University, TW; ²National Tsing Hua University, TW Abstract This paper proposes built-in self-test (BIST) and built-in self-repair (BISR) strategies for computing in-memory (CIM), including a novel testing method, CIM output range adjusting, and CIM bitline reordering. They all focus on mitigating the impacts of inherent and inevitable CIM inaccuracy on convolution neural networks (CNNs). Regarding the proposed BIST strategy, it exploits the distributive law to achieve at-speed CIM tests without storing testing vectors or golden results. Besides, it can assess the severity of the inherent inaccuracies among CIM bitlines instead of only offering a pass/fail outcome. In addition to BIST, we propose two BISR strategies. First, we propose to slightly offset the dynamic range of CIM outputs toward the negative side to create a margin for negative noises. By not cutting CIM outputs off at zero, negative noises are preserved to cancel positive noises statistically, and accuracy impacts are mitigated. Second, we propose to remap the bitlines of CIM according to our BIST outcomes. Briefly speaking, we propose to map the least noisy bitlines to be the MSBs. This remapping can be done in the digital domain without touching the CIM internals. Experiments show that our proposed BIST and BISR strategies can restore CIM to less than 1% Top-1 accuracy loss with slight hardware overhead.
00:39 CET		BITSTREAM-LEVEL INTERCONNECT FAULT CHARACTERIZATION FOR SRAM-BASED FPGAS Authors: Christian Fibich¹, Martin Horauer¹ and Roman Obermaisser² ¹University of Applied Sciences Technikum Wien, AT; ²University of Siegen, DE Abstract The configurable interconnect of SRAM-based FPGAs makes up a significant portion of their configuration, and thus exposes a large attack surface to single-event upsets. Time-consuming fault injection experiments as well as reliability estimation techniques benefit from a better understanding of the behavior of FPGA interconnects under the presence of these faults, allowing to treat some interconnect faults as more serious than others. This work proposes an approach to (1) analyze the interconnect configuration of a given FPGA technology to deduce the logical effects caused by single-bit flips and (2) to characterize the effects of a subcategory of such faults – faults that create device-internal short circuits – on routes implemented on a given FPGA technology. These approaches are illustrated in case studies on two FPGA technologies: Xilinx 7 Series and Lattice iCE40. Characterization of interconnect faults on Xilinx 7 Series revealed that in a particular subcategory – short circuits with previously unused wires – only a fraction of these faults impact a signal critically. Applying this knowledge to three benchmark designs shows that the number of tested bits in this category can be reduced by more than 85%. Assuming that all other bits are tested exhaustively, the total number of injections is reduced by at least 19%. This prediction has subsequently been validated using fault injection experiments.
00:39 CET		COMPACT TEST PATTERN GENERATION FOR MULTIPLE FAULTS IN DEEP NEURAL NETWORKS Authors: Dina Moussa¹, Michael Hefenbrock² and Mehdi Tahoori¹ ¹Karlsruhe Institute of Technology, DE; ²RevoAI, DE Abstract Deep neural networks (DNNs) have achieved record-breaking performance in various applications. However, this often comes at significant computational costs. To reduce the energy footprint and increase performance, DNNs are often implemented on specific hardware accelerators, such as Tensor Processing Units (TPU) or emerging Memristive technologies. Unfortunately, the presence of various hardware faults can threaten these accelerators' performance and degrade the inference accuracy. This necessitates the development of efficient testing methodologies to unveil hardware faults in DNN accelerators. In this work, we propose a test pattern generation approach to detect fault patterns in DNNs for a common type of hardware fault, namely, faulty (weight) value representation on the bit level. Opposed to most related works which reveal faults via output deviations, our test patterns are constructed to reveal faults via misclassification which is more realistic for black-box testing. The experimental results show that the generated test patterns provide 100% fault coverage for targeted fault patterns. Besides, a high compaction ratio was achieved over different datasets and model architectures (up to 50x), and high fault coverage (up to 99.9%) for unseen fault patterns during the test generation phase.
00:39 CET		READ: RELIABILITY-ENHANCED ACCELERATOR DATAFLOW OPTIMIZATION USING CRITICAL INPUT PATTERN REDUCTION Authors: Zuodong Zhang¹, Meng Li², Yibo Lin³, Runsheng Wang³ and Ru Huang³ ¹School of Integrated Circuits, Peking University, CN; ²Institute for Artificial Intelligence and School of Integrated Circuits, Peking University, CN; ³Peking University, CN Abstract With the rapid advancements of deep learning in recent years, hardware accelerators are continuously deployed in more and more safety-critical applications such as autonomous driving and robotics. While the accelerators are usually fabricated with advanced technology nodes for higher performance and energy efficiency, which are more prone to timing errors under process, voltage, temperature, and aging (PVTA) variations. By revisiting the physical sources of timing errors, we show that most of the timing errors in the accelerator are caused by several specific input patterns, defined as critical input patterns. To improve the robustness of the accelerator, in this paper, we propose READ, a reliability-enhanced accelerator dataflow optimization method that can effectively reduce timing errors. READ can reduce the critical input patterns by exploring the optimal computing sequence when mapping a trained deep neural network to the accelerator. READ only changes the order of MAC operations in a convolution, and it does not introduce any additional hardware overhead to the computing array. The experimental results on VGG-16 and ResNet-18 demonstrate on average 6.3× timing error reduction and up to 24.25× timing error reduction for certain layers. The results also show that READ enables the accelerator to maintain accuracy over a wide range of PVTA variations, making it a promising approach for robust deep learning design.
00:39 CET		ROBUST RESISTIVE OPEN DEFECT IDENTIFICATION USING MACHINE LEARNING WITH EFFICIENT FEATURE SELECTION Authors: Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch and Hans-Joachim Wunderlich, University of Stuttgart, DE Abstract Resistive open defects of circuits in FinFET technology cause small delay faults, which may increase over the lifetime and should be ruled out before deployment. In order not to sacrifice yield, these defects have to be distinguished from the effects of process variation, which are mostly benign. Recently, it has been shown that machine learning schemes are able to classify defective circuits with high accuracy based on the maximum frequencies Fmax(Vdd) obtained under multiple supply voltages Vdd ∈ Vop. In the paper at hand, it is shown that the machine learning-based technique can work efficiently with a drastically reduced number of Fmax(Vdd) measurements while retaining still a high accuracy. Each supply voltage Vdd defines a feature Fmax(Vdd), and state-of-the-art feature selection techniques reduce the measurement efforts significantly. In systems with Adaptive Voltage Frequency Scaling (AVFS), Fmax measurements are available for minimum, maximum, and nominal supply voltages. Therefore, often the conventional speed-binning report allows already a highly accurate defect classification.
00:39 CET		SECURITY-AWARE APPROXIMATE SPIKING NEURAL NETWORK Authors: Syed Tihaam Ahmad, Ayesha Siddique and Khaza Anuarul Hoque, University of Missouri, US Abstract Deep Neural Networks (DNNs) and Spiking Neural Networks (SNNs) are both known for their susceptibility to adversarial attacks. Therefore, researchers in the recent past have extensively studied the robustness and defense of DNNs and SNNs under adversarial attacks. Compared to accurate SNNs (AccSNN), approximate SNNs (AxSNNs) are known to be up to 4X more energy-efficient for ultra-low power applications. Unfortunately, the robustness of AxSNNs under adversarial attacks is yet unexplored. In this paper, we first extensively analyze the robustness of AxSNNs under different structural parameters and approximation levels against two gradient-based and two neuromorphic attacks. Our study revealed that AxSNNs are more prone to adversarial attacks than AccSNNs. Then we propose a novel design approach for designing robust AxSNNs using two novel defense methods: precision scaling and approximation- and quantization-aware filtering (AQF). The effectiveness of these two defense methods was evaluated using one static and one neuromorphic dataset. Our results demonstrate that precision scaling and AQF can significantly improve the robustness of AxSNNs. For instance, a PGD attack on AxSNN results in 72\% accuracy loss, whereas the same attack on the precision-scaled AxSNN leads to only 17\% accuracy loss in the static MNIST dataset (4X robustness improvement). Similarly, for the neuromorphic DVS128 Gesture dataset, we observe that Sparse Attack on AxSNN leads to 77\% accuracy loss compared to AccSNN without any attack. However, with AQF, the accuracy loss is only 2\% (38X robustness improvement).
00:39 CET		BAFFI: A BIT-ACCURATE FAULT INJECTOR FOR IMPROVED DEPENDABILITY ASSESSMENT OF FPGA PROTOTYPES Authors: Ilya Tuzov¹, David de Andres², Juan-Carlos Ruiz² and Carles Hernandez² ¹Universidad Politécnica de Valencia, ES; ²Universidad Politecnica de Valencia, ES Abstract FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs. Existing FFI tools make use of Xilinx essential bits technology to locate the relevant fault targets in FPGA configuration memory (CM). Most FFI tools treat essential bits as black-box, while few of them are able to filter essential bits on the area basis (grid coordinates) in order to selectively target design components contained within the predefined Pblocks. This approach, however, not only alters the timing properties of the circuit with respect to original (unconstrained) placement, but also remains insufficiently precise since the granularity of Pblocks in practice doesn't reach the smallest design (netlist) components. This paper proposes an open-source FFI tool that enables much more fine-grained FFI experiments for Xilinx 7-series and Ultrascale+ FPGAs. By mapping the essential bits with the hierarchical netlist, it allows to precisely target any component in the design tree (up to an individual LUT or register), without the need for defining Pblocks (floorplanning). With minimal experimental effort it estimates the contribution of each DUT component into the resulting dependability features, and discovers weak points of the DUT. Through case studies this paper exemplifies how the proposed tool can be exploited to setup FFI experiments, controlled from the host or from the FPGA itself, for different kinds of DUTs: from small-footprint microcontrollers, up to multicore RISC-V SoC. The correctness of FFI results is validated by means of RT-level and gate-level simulation-based fault injection.
00:39 CET		A NOVEL FAULT-TOLERANT ARCHITECTURE FOR TILED MATRIX MULTIPLICATION Authors: Sandeep Bal¹, Chandra Sekhar Mummidi¹, Victor da Cruz Ferreira², Sudarshan Srinivasan³ and Sandip Kundu⁴ ¹University of Massachusetts, Amherst, US; ²Federal University of Rio de Janeiro, BR; ³Intel Labs, IN; ⁴University of Massachusetts Amherst, US Abstract General matrix multiplication (GEMM) is common to many scientific and machine-learning applications. Convolution, the dominant computation in Convolutional Neural Networks (CNNs), can be formulated as a GEMM problem. Due to its widespread use, new generation of processors feature GEMM acceleration in hardware. Intel recently announced an Advanced Matrix Multiplication (AMX®) instruction set for GEMM, which is supported by 1kb AMX registers and a Tile Multiplication unit (TMUL) for multiplying tiles (sub matrices) in hardware. Silent Data Corruption (SDC) is a well-known problem that occurs when hardware generates corrupt output. Google and Meta recently reported findings of SDC in GEMM in their data centers. Algorithm-Based Fault Tolerance (ABFT) is an efficient mechanism for detecting and correcting errors in GEMM, but classic ABFT solutions are not optimized for hardware acceleration. In this paper, we present a novel ABFT implementation directly on hardware. Though the exact implementation of Intel TMUL is not known, we propose two different TMUL architectures representing two design points in the area-power-performance spectrum and illustrate how ABFT can be directly incorporated into the TMUL hardware. This approach has two advantages: (i) an error can be concurrently detected at the tile level, which is an improvement over finding such errors only after performing the full matrix multiplication; and (ii) we further demonstrate that performing ABFT at the hardware level has no performance impact and only a small area, latency and power overhead.
00:39 CET		REDUCE: A FRAMEWORK FOR REDUCING THE OVERHEADS OF FAULT-AWARE RETRAINING Authors: Muhammad Abdullah Hanif¹ and Muhammad Shafique² ¹New York University Abu Dhabi, AE; ²New York University Abu Dhabi (NYUAD), AE Abstract Fault-aware retraining has emerged as the foremost technique for mitigating permanent faults in DNN hardware. However, retraining leads to huge overheads, specifically when used for fine-tuning large DNNs designed for complex AI problems. Moreover, as each fabricated chip can have a distinct fault pattern, fault-aware retraining is required to be performed for each chip individually considering its unique fault map, which further amplifies the problem. To reduce the overall/average retraining cost, in this work, we introduce the concepts of resilience-driven retraining amount selection and fusion of multiple fault maps belonging to different chips. To realize these concepts, we propose a framework, Reduce, that, at first, computes the resilience of a given DNN to faults at different fault rates and with different amounts of retraining. Then, based on the resilience, it computes the amount of retraining required for each chip considering its unique fault map. At the end, it performs resilience-driven grouping and fusion of fault maps to further reduce the number of retraining iterations required for tuning the given DNN for the given set of faulty chips. We demonstrate the effectiveness of our proposed methodology for a systolic array-based DNN accelerator experiencing permanent faults in the computational array of the design. The results show that the proposed technique significantly reduces the retraining cost when used for tuning a DNN for a set of faulty chips.

BPA_11 Supply chain attacks

Date: Tuesday, 18 April 2023
Time: 14:00 - 16:00 CET

Time	Label	Presentation Title Authors
00:39 CET		HARDWARE TROJANS IN ENVM NEUROMORPHIC DEVICES Authors: Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Stan Mircea and Ashish Venkat, University of Virginia, US Abstract Fast and energy-efficient execution of a DNN on traditional CPU- and GPU-based architectures is challenging due to excessive data movement and inefficient computation. Emerging non-volatile memory (eNVM)-based accelerators that mimic biological neuron computations in the analog domain have shown significant performance improvements. However, the potential security threats in the supply chain of such systems have been largely understudied. This work describes a hardware supply chain attack against analog eNVM neural accelerators by identifying potential Trojan insertion points and proposes a hardware Trojan design that stealthily leaks model parameters while evading detection. Our evaluation shows that such a hardware Trojan can recover over 90% of the synaptic weights.
00:39 CET		EVOLUTE: EVALUATION OF LOOK-UP-TABLE-BASED FINE-GRAINED IP REDACTION Authors: Rui Guo¹, Mohammad Rahman¹, Hadi Mardani Kamali¹, Fahim Rahman¹, Farimah Farahmandi¹ and Mark Tehranipoor² ¹University of Florida, US; ²Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity, Associate Chair for Research and Strategic Initiatives, ECE Department, University of Florida, US Abstract Recent studies on intellectual property (IP) protection techniques demonstrate that engaging embedded reconfigurable components (e.g., eFPGA redaction) would be a promising approach to concealing the functional and structural information of the security-critical design. However, detailed investigation reveals that such techniques suffer from almost prohibited overhead in terms of area, power, delay, and testability. In this paper, we introduce "EvoLUTe", a distinct and significantly more fine-grained redaction methodology using smaller reconfigurable components (such as look-up-tables (LUTs)). In "EvoLUTe", we examine both eFPGA-based and LUT-based design spaces, demonstrating that a novel cone-based and fine-grained universal function modeling approach using LUTs is capable of providing the same degree of resiliency at a much lower area, power, delay, and testability costs.
00:39 CET		RTLOCK: IP PROTECTION USING SCAN-AWARE LOGIC LOCKING AT RTL Authors: Md Rafid Muttaki¹, Shuvagata Saha¹, Hadi Mardani Kamali¹, Fahim Rahman¹, Mark Tehranipoor² and Farimah Farahmandi¹ ¹University of Florida, US; ²Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity, Associate Chair for Research and Strategic Initiatives, ECE Department, University of Florida, US Abstract Conventional logic locking techniques mainly focus on gate-level netlists to combat IP piracy and IC overproduction. However, this is generally not sufficient for protecting semantics and behaviors of the design. Further, these techniques are even more objectionable when the IC supply chain is at risk of insider threats. This paper proposes RTLock, a robust logic locking framework at the RTL abstraction. RTLock provides a detailed formal analysis of the design specs at the RTL that determines the locking candidate points w.r.t. attacks resiliency (SAT/BMC), locking key size, and overhead. RTLock incorporates (partial) DFT infrastructure (scan chain) at the RTL, enabled with a scan locking mechanism. It allows us to push all the necessary security-driven actions to the highest abstraction level, thus making the flow EDA tool agnostic. Additionally, RTLock demonstrates why RTL-based locking must be coupled with encryption and management protocols (e.g., IEEE 1735), to be effective against insider threats. Our experimental results show that, vs. other techniques, RTLock protects the design against broader threats at low overhead and without compromising testability.

BPA_7 Improving Heterogenous hardware utilization

Date: Tuesday, 18 April 2023
Time: 14:00 - 16:00 CET

Time	Label	Presentation Title Authors
00:39 CET		DITTY: DIRECTORY-BASED CACHE COHERENCE FOR MULTICORE SAFETY-CRITICAL SYSTEMS Authors: Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre and Hiren Patel, University of Waterloo, CA Abstract Ditty is a predictable directory-based cache coherence mechanism for multicore safety-critical systems that guarantees a worst-case latency (WCL) on data accesses. All prior approaches for predictable cache coherence use a shared snooping bus approach to interconnect cores. This restricts the number of cores in the multicore to typically four or eight due to practical scalability concerns. Ditty takes a first step towards a scalable cache coherence mechanism that is predictable and one that can support a larger number of cores. In designing Ditty, we propose coherence protocol and micro-architecture additions to deliver a WCL bound that is significantly lower than a naive approach. Our WCL analysis reveals that the resulting bounds are comparable to state-of-the-art bus-based predictable coherence approaches. We prototype Ditty in hardware and empirically evaluate it on an FPGA. Our evaluation shows the observed WCL is within computed WCL bounds for both the synthetic and SPLASH-3 benchmarks. We release our implementation to the public domain.
00:39 CET		LIGHT FLASH WRITE FOR EFFICIENT FIRMWARE UPDATE ON ENERGY-HARVESTING IOT DEVICES Authors: Songran Liu¹, Mingsong Lv², Wei Zhang³, Xu Jiang¹, Chuancai Gu⁴, Tao Yang⁴, Wang Yi⁵ and Nan Guan⁶ ¹Northeastern University, CN; ²The Hong Kong Polytechnic University, HK; ³School of Cyber Science and Technology, Shandong University, CN; ⁴Huawei Technologies Company, CN; ⁵Uppsala University, SE; ⁶City University of Hong Kong, HK Abstract Firmware update is an essential service on Internet-of-Things (IoT) devices to fix vulnerabilities and add new functionalities. Firmware update is energy-consuming since it involves intensive flash erase/write operations. Nowadays, IoT devices are increasingly powered by energy harvesting. As the energy output of the harvesters on IoT devices is typically tiny and unstable, a firmware update will likely experience power failures during its progress and fail to complete. This paper presents an approach to increase the success rate of firmware update on energy-harvesting IoT devices. The main idea is to first conduct a lightweight flash write with reduced erase/write time (and thus less energy consumed) to quickly save the new firmware image to flash memory before a power failure occurs. To ensure a long data retention time, a reinforcement step follows to re-write the new firmware image on the flash with default erase/write configuration when the system is not busy and has free energy. Experiments conducted with different energy scenarios show that our approach can significantly increase the success rate and the efficiency of firmware update on energy-harvesting IoT devices.
00:39 CET		HADAS: HARDWARE-AWARE DYNAMIC NEURAL ARCHITECTURE SEARCH FOR EDGE PERFORMANCE SCALING Authors: Halima Bouzidi¹, Mohanad Odema², Hamza Ouarnoughi³, Mohammad Al Faruque² and Smail Niar⁴ ¹University Polytechnique Hauts-de-France, LAMIH, CNRS, UMR 8201, F-59313 Valenciennes, France, FR; ²University of California Irvine, US; ³INSA Hauts-de-France, FR; ⁴INSA Hauts-de-France and CNRS, FR Abstract Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its underlying backbone architecture being developed at the design stage independent of both: (i) the dynamic computing features, e.g. early exiting, and (ii) the resource efficiency features of the underlying hardware, e.g., dynamic voltage and frequency scaling (DVFS). Addressing this, we present HADAS, a novel Hardware-Aware Dynamic Neural Architecture Search framework that realizes DyNN architectures whose backbone, early exiting features, and DVFS settings have been jointly optimized to maximize performance and resource efficiency. Our experiments using the CIFAR-100 dataset and a diverse set of edge computing platforms have seen HADAS dynamic models achieve up to 57\% energy efficiency gains compared to the conventional dynamic ones while maintaining the desired level of accuracy scores.

S_E4 Hardware accelerators serving efficient machine learning software architectures

Date: Tuesday, 18 April 2023
Time: 16:30 - 18:00 CET

Time	Label	Presentation Title Authors
00:39 CET		PIPE-BD: PIPELINED PARALLEL BLOCKWISE DISTILLATION Authors: Hongsun Jang¹, Jaewon Jung², Jaeyong Song¹, Joonsang Yu³, Youngsok Kim¹ and Jinho Lee⁴ ¹Yonsei University, KR; ²Yonsei university, KR; ³NAVER CLOVA, KR; ⁴Seoul National University, KR Abstract Training or searching of large deep neural network models have been challenged by its tremendous amount of computation and memory requirement. Blockwise distillation is one promising method to mitigate the problem by ensuring faster convergence; a large model is effectively split into multiple smaller models. The training of latter student blocks requires the results of the earlier teacher blocks. Therefore, the state-of-the-art blockwise distillation method distributes a batch to multiple GPUs, and makes each GPU train its student block by executing all the earlier teacher blocks. However, this results in a high overhead of redundant teacher execution, low GPU utilization and extra data loading. To address the problems, we propose PipeBD, a novel parallelization method for blockwise distillation. PipeBD comprises three main components. First, teacher relaying lets each device only process its own teacher block by relaying the activation values. Second, decoupled parameter update removes synchronization barriers by performing unaligned updates on each student block. Last, automatic hybrid distribution enhances load balancing by further splitting the stages along the batch dimension. We implement PipeBD on PyTorch, where all the decisions are seamlessly made automatically. Experiments reveal that PipeBD achieves significant speedups.
00:39 CET		LAYER-PUZZLE: ALLOCATING AND SCHEDULING MULTI-TASK ON MULTI-CORE NPUS BY USING LAYER HETEROGENEITY Authors: Chengsi Gao¹, Ying Wang², Cheng Liu¹, Mengdi Wang¹, Weiwei Chen¹, yinhe han³ and Lei Zhang³ ¹Institute of Computing Technology, Chinese Academy of Sciences, CN; ²State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, CN; ³Institute of Computing Technology,Chinese Academy of Sciences, CN Abstract To support the efficient execution of multi-task DNNs on multi-core NPUs, intensive research has been proposed. However, prior works will lead to low hardware utilization since they ignore the inter-layer heterogeneity within the DNN models. Thus, to fully exploit such characteristics, we propose Layer-Puzzle, a multi-task allocation and scheduling framework for multi-core NPUs. Based on the proposed latency-prediction model and dynamic parallelization scheme, Layer-Puzzle can generate optimal or near-optimal results for each layer under given hardware resources and traffic congestion levels. As an online scheduler, Layer-Puzzle performs a QoS-aware and dynamic scheduling method that picks the superior version from the previous compiled results and co-runs the selected tasks to improve system performance. Our experiments on MLPerf show that Layer-Puzzle can achieve an average of 1.61X, 1.53X, and 1.95X improvement in ANTT, STP, and PE utilization, respectively.
00:39 CET		DYNAMIC TASK REMAPPING FOR RELIABLE CNN TRAINING ON RERAM CROSSBARS Authors: Chung-Hsuan Tung¹, Biresh Kumar Joardar², Partha Pratim Pande³, Jana Doppa³, Hai (Helen) Li¹ and Krishnendu Chakrabarty¹ ¹Duke University, US; ²University of Houston, US; ³Washington State University, US Abstract A ReRAM crossbar-based computing system (RCS) can accelerate CNN training. However, hardware faults due to manufacturing defects and limited endurance impede the widespread adoption of RCS. We propose a dynamic task remapping-based technique for reliable CNN training on faulty RCS. Experimental results demonstrate that the proposed low-overhead method incurs only 0.85% accuracy loss on average while training popular CNNs such as VGGs, ResNets, and SqueezeNet with the CIFAR-10, CIFAR-100, and SVHN datasets in the presence of faults.
00:39 CET		MOBILE ACCELERATOR EXPLOITING SPARSITY OF MULTI-HEADS, LINES AND BLOCKS IN TRANSFORMERS IN COMPUTER VISION Authors: Eunji Kwon¹, Haena Song², Jihye Park² and Seokhyeong Kang² ¹Postech, KR; ²POSTECH, KR Abstract It is difficult to employ transformer models for computer vision in mobile devices due to their memory- and computation-intensive properties. Accordingly, there is ongoing research on various methods for compressing transformer models, such as pruning. However, general computing platforms such as central processing units (CPUs) and graphics processing units (GPUs) are not energy-efficient to accelerate the pruned model due to their structured sparsity. This paper proposes a low-power accelerator for transformers in computer vision with various sizes of structured sparsity induced by pruning with different granularity. In this study, we can accelerate a transformer that has been pruned in a head-wise, line-wise, or block-wise manner. We developed a head scheduling algorithm to support head-wise skip operations and resolve the processing engine (PE) load imbalance problem caused by different amounts of computations in one head. Moreover, we implemented a sparse general matrix-to-matrix multiplication (sparse GEMM) that supports line-wise and block-wise skipping. As a result, when compared with a mobile GPU and mobile CPU respectively, our proposed accelerator achieved 6.1x and 13.6x improvements in energy efficiency for the detection transformer (DETR) model and achieved approximately 2.6x and 7.9x improvements in the energy efficiency on average for the vision transformer (ViT) models.
00:39 CET		RAWATTEN: RECONFIGURABLE ACCELERATOR FOR WINDOW ATTENTION IN HIERARCHICAL VISION TRANSFORMERS Authors: Wantong Li, Yandong Luo and Shimeng Yu, Georgia Institute of Technology, US Abstract After the success of the transformer networks on natural language processing (NLP), the application of transformers to computer vision has followed suit to deliver unprecedented performance gains on vision tasks including image recognition and object detection. The multi-head self-attention (MSA) is the key component in transformers, allowing the models to learn the amount of attention paid to each input position. In particular, hierarchical vision transformers (HVTs) utilize window-based MSA to capture the benefits of the attention mechanism at various scales for further accuracy enhancements. Despite its strong modeling capability, MSA involves complex operations that make transformers prohibitively costly for hardware deployment. Existing hardware accelerators have mainly focused on the MSA workloads in NLP applications, but HVTs involve different parameter dimensions, input sizes, and data reuse opportunities. Therefore, we design the RAWAtten architecture to target the window-based MSA workloads in HVT models. Each w-core in RAWAtten contains near-memory compute engines for linear layers, MAC arrays for intermediate matrix multiplications, and a lightweight reconfigurable softmax. The w-cores can be combined at runtime to perform hierarchical processing to accommodate varying model parameters. Compared to the baseline GPU, RAWAtten at 40nm provides 2.4× average speedup for running the window-MSA workloads in Swin transformer models while consuming only a fraction of GPU power. In addition, RAWAtten achieves 2× area efficiency compared to prior ASIC accelerator for window-MSA.
00:39 CET		M5: MULTI-MODAL MULTI-TASK MODEL MAPPING ON MULTI-FPGA WITH ACCELERATOR CONFIGURATION SEARCH Authors: Akshay Kamath, Stefan Abi-Karam, Ashwin Bhat and Cong "Callie" Hao, Georgia Institute of Technology, US Abstract Recent machine learning (ML) models have advanced from single-modality single-task to multi-modality multi-task (MMMT). MMMT models typically have multiple backbones of different sizes and complicated connections, exposing great challenges for hardware deployment. For scalable and energy-efficient implementations, multi- FPGA systems are emerging as the ideal design choice. However, finding the optimal solutions for mapping MMMT models onto multiple FPGAs is non-trivial. Existing mapping algorithms focus either on streamlined linear deep neural network architectures or only the critical path of simple heterogeneous models. Direct extensions of these algorithms for MMMT models lead to sub-optimal solutions. To address these shortcomings, we propose M5, a novel MMMT model Mapping framework for Multi- FPGA platforms. In addition to handling multiple modalities present in the models, M5 can flexibly explore accelerator configurations and possible resource sharing opportunities to significantly improve the system performance. For various computation-heavy MMMT models, experiment results demonstrate that M5 can remarkably outperform existing mapping methods and lead to an average reduction of 35%, 62%, and 70% in the number of low-end, mid-end, and high-end FPGAs required to achieve the same throughput, respectively. Code is available publicly.
00:39 CET		STEPPINGNET: A STEPPING NEURAL NETWORK WITH INCREMENTAL ACCURACY ENHANCEMENT Authors: Wenhao Sun¹, Grace Li Zhang², Xunzhao Yin³, Cheng Zhuo³, Huaxi Gu⁴, Bing Li¹ and Ulf Schlichtmann¹ ¹TU Munich, DE; ²TU Darmstadt, DE; ³Zhejiang University, CN; ⁴Xidian University, CN Abstract Deep neural networks (DNNs) have successfully been applied in many fields in the past decades. However, the increasing number of multiply-and-accumulate (MAC) operations in DNNs prevents their application in resource-constrained and resource-varying platforms, e.g., mobile phones and autonomous vehicles. In such platforms, neural networks need to provide acceptable results quickly and the accuracy of the results should be able to be enhanced dynamically according to the computational resources available in the computing system. To address these challenges, we propose a design framework called SteppingNet. SteppingNet constructs a series of subnets whose accuracy is incrementally enhanced with more MAC operations. Therefore, this design allows a trade-off between accuracy and latency. In addition, the larger subnets in SteppingNet are built upon smaller subnets, so that the results of the latter can directly be reused in the former without recomputation. This property allows SteppingNet to decide on-the-fly whether to enhance the inference accuracy by executing further MAC operations. Experimental results demonstrate that SteppingNet provides an effective incremental accuracy improvement and its inference accuracy consistently outperforms the state-of-the-art work under the same limit of computational resources.
00:39 CET		AIRCHITECT: AUTOMATING HARDWARE ARCHITECTURE AND MAPPING OPTIMIZATION Authors: Ananda Samajdar¹, Jan Moritz Joseph² and Tushar Krishna¹ ¹Georgia Institute of Technology, US; ²RWTH Aachen University, DE Abstract Design space exploration and optimization is an essential but iterative step in custom accelerator design involving costly search based method to extract maximum performance and energy efficiency. State-of-the-art methods employ data centric approaches to reduce the cost of each iteration but still rely on search algorithms to obtain the optima. This work proposes a learned, constant time optimizer that uses a custom recommendation network called AIRCHITECT, which is capable of learning the architecture design and mapping space with a 94.3% test accuracy, and predicting optimal configurations, which achieve on an average (GeoMean) 99.9% of the best possible performance on a test dataset with 105 GEMM (GEneral Matrix- matrix Multiplication) workloads.
00:39 CET		ACCELERATING INFERENCE OF 3D-CNN ON ARM MANY-CORE CPU VIA HIERARCHICAL MODEL PARTITION Authors: Jiazhi Jiang, ZiJian Huang, Dan Huang, Jiangsu Du and Yutong Lu, Sun Yat-sen University, CN Abstract Many applications such as biomedical analysis and scientific data analysis involve analyzing volumetric data. This spawns huge demand for 3D CNN. Although accelerators such as GPU may provide higher throughput on deep learning applications, they may not be available in all scenarios. CPU, especially many-core CPU, remains an attractive choice for deep learning in many scenarios. In this paper, we propose a inference solution that targets on the emerging ARM many-core CPU platform. A hierarchical partition approach is claimed to accelerate 3D-CNN inference by exploiting characteristics of memory and cache on ARM many-core CPU. Based on the hierarchical model partition approach, other optimization techniques such as NUMA-aware thread scheduling is designed to exploit the potential of ARM many-core CPU for 3D-CNN. We evaluate our proposed inference solution with several classic 3D-CNNs: C3D, 3D-resnet34 and 3D-resnet50. Our experimental results show that our solution can boost the performance of the 3D-CNN inference, and achieve much better scalability.
00:39 CET		CEST: COMPUTATION-EFFICIENT N:M SPARSE TRAINING FOR DEEP NEURAL NETWORKS Authors: Chao Fang¹, Wei Sun², Aojun Zhou³ and Zhongfeng Wang¹ ¹Nanjing University, CN; ²Eindhoven University of Technology, NL; ³The Chinese University of Hongkong, HK Abstract Sparse training is one of the promising techniques to reduce the computational cost and retain the high accuracy of DNNs, but prior works mainly focus on leveraging structured or unstructured sparsity patterns. Structured sparsity has limitations in reducing computational complexity, while unstructured sparsity is difficult to accelerate on hardware. Recently, N:M fine-grained structured sparsity, where only N out of consecutive M elements can be nonzero, has attracted attention due to its practical sparsity ratio and hardware-friendly pattern. However, the potential to accelerate N:M sparse DNN training has not been fully exploited, and there is a lack of efficient hardware supporting N:M sparse training. To tackle these challenges, this paper presents an algorithm-hardware co-design scheme - Computation-Efficient N:M Sparse Training (CEST) for DNNs. At the algorithmic level, a bidirectional weight pruning method, dubbed BDWP, is proposed to leverage the N:M sparsity of weights during both forward and backward passes of DNN training, which can significantly reduce the computational cost while maintaining model accuracy. At the architectural level, a sparse accelerator for DNN training, namely SAT, is developed to neatly support both the regular dense operations and the computation-efficient N:M sparse operations. Finally, the effectiveness of CEST is evaluated on a Xilinx Virtex UltraScale+ VCU1525 FPGA card using various DNN models and datasets. Experimental results show that CEST significantly improves the training throughput by 1.89-12.49x and the energy efficiency by 2.19-3.26x over prior FPGA-based training accelerators, and incurs merely 0.45% accuracy loss on average compared to the dense training scheme.
00:39 CET		BOMP-NAS: BAYESIAN OPTIMIZATION MIXED PRECISION NAS Authors: David van Son¹, Floran de Putter¹, Sebastian Vogel² and Henk Corporaal³ ¹Eindhoven University of Technology, NL; ²NXP Semiconductors, NL; ³TU/e (Eindhoven University of Technology), NL Abstract Bayesian Optimization Mixed-Precision Neural Architecture Search (BOMP-NAS) is an approach to quantization-aware neural architecture search (QA-NAS) that leverages both Bayesian optimization (BO) and mixed-precision quantization (MP) to efficiently search for compact, high performance deep neural networks. The results show that integrating quantization-aware fine-tuning (QAFT) into the NAS loop is a necessary step to find networks that perform well under low-precision quantization: integrating it allows a model size reduction of nearly 50% on the CIFAR-10 dataset. BOMP-NAS is able to find neural networks that achieve state-of-the-art performance at much lower design costs. This study shows that BOMP-NAS can find these neural networks at a 6× shorter search time compared to the closest related work.
00:39 CET		HARDNNING: A MACHINE-LEARNING-BASED FRAMEWORK FOR FAULT TOLERANCE ASSESSMENT AND PROTECTION OF DEEP NEURAL NETWORKS. Authors: Marcello Traiola¹, Angeliki Kritikakou² and Olivier Sentieys³ ¹Inria / IRISA, FR; ²Univ Rennes, Inria, CNRS, IRISA, FR; ³INRIA, FR Abstract Deep Neural Networks (DNNs) show promising performance in several application domains, such as robotics, aerospace, smart healthcare, and autonomous driving. Nevertheless, DNN results may be incorrect, not only because of the network intrinsic inaccuracy, but also due to faults affecting the hardware. Indeed, hardware faults may impact the DNN inference process and lead to prediction failures. Therefore, ensuring the fault tolerance of DNN is crucial. However, common fault tolerance approaches are not cost-effective for DNNs protection, because of the prohibitive overheads due to the large size of DNNs and of required memory for parameter storage. In this work, we propose a comprehensive framework to assess the fault tolerance of DNNs and cost-effectively protect them. As a first step, the proposed framework performs datatype-and-layer-based fault injection, driven by the DNN characteristics. As a second step, it uses classification-based machine learning methods in order to predict the criticality, not only of network parameters, but also of their bits. Last, dedicated Error Correction Codes (ECCs) are selectively inserted to protect the critical parameters and bits, hence protecting the DNNs with low cost. Thanks to the proposed framework, we explored and protected eight Convolutional Neural Networks (CNNs). The results show that it is possible to protect the critical network parameters with selective ECCs while saving up to 82% memory w.r.t. conventional ECC approaches.

S_S3 Secure circuits and architectures

Date: Tuesday, 18 April 2023
Time: 16:30 - 18:00 CET

Time	Label	Presentation Title Authors
00:39 CET		ESTABLISHING DYNAMIC SECURE SESSIONS FOR ECQV IMPLICIT CERTIFICATES IN EMBEDDED SYSTEMS Authors: Fikret Basic¹, Christian Steger¹ and Robert Kofler² ¹Graz University of Technology, AT; ²NXP Semiconductors Austria GmbH Co & KG, AT Abstract Implicit certificates are gaining ever more prominence in constrained embedded devices, in both the internet of things (IoT) and automotive domains. They present a resource-efficient security solution against common threat concerns. The computational requirements are not the main issue anymore, with the focus now shifting to determining a good balance between the provided security level and the derived threat model. A security aspect that often gets overlooked is the establishment of secure communication sessions, as most design solutions are based only on the use of static key derivation, and therefore lack the perfect forward secrecy. This leaves the transmitted data open for potential future exposures as keys are tied to the certificates rather than the communication sessions. We aim to close this gap and present a design that utilizes the Station to Station (STS) protocol with implicit certificates. In addition, we propose potential protocol optimization implementation steps and run a comprehensive study on the performance and security level between the proposed design and the state-of-the-art key derivation protocols. In our comparative study, we show that we are able to mitigate many session-related security vulnerabilities that would otherwise remain open with only a slight computational increase of 20% compared to a static elliptic curve digital signature algorithm (ECDSA) key derivation.
00:39 CET		CACHE SIDE-CHANNEL ATTACKS AND DEFENSES OF THE SLIDING WINDOW ALGORITHM IN TEES Authors: Zili KOU¹, Sharad Sinha², Wenjian HE¹ and Wei ZHANG¹ ¹Hong Kong University of Science and Technology, HK; ²Indian Institute of Technology Goa, IN Abstract Trusted execution environments (TEEs) such as SGX on x86 and TrustZone on ARM are announced to protect trusted programs against even a malicious operation system (OS), however, they are still vulnerable to cache side-channel attacks. In the new threat model of TEEs, kernel-privileged attackers are more capable, thus the effectiveness of previous defenses need to be carefully reevaluated. Aimed at the sliding window algorithm of RSA, this work analyzes the latest defenses from the TEE attacker's point of view and pinpoints their attack surfaces and vulnerabilities. The mainstream cryptography libraries are scrutinized, within which we attack and evaluate the implementations of Libgcrypt and MbedTLS on a real-world ARM processor with TrustZone. Our attack successfully recovers the key of RSA in the latest MbedTLS design when it adopts a small window size, despite MbedTLS being the reference implementation of ARM TrustZone. The possible countermeasures are finally presented together with the corresponding costs.
00:39 CET		THE FIRST CONCEPT AND REAL-WORLD DEPLOYMENT OF A GPU-BASED THERMAL COVERT CHANNEL: ATTACK AND COUNTERMEASURES Authors: Jeferson Gonzalez-Gomez¹, Kevin Cordero-Zuniga², Lars Bauer³ and Joerg Henkel¹ ¹KIT, DE; ²ITCR, CR; ³Karlsruhe Institute of Technology, DE Abstract Thermal covert channel (TCC) attacks have been studied as a threat to CPU-based systems over recent years. In this paper, we propose a new type of TCC attack that for the first time leverages the Graphics Processing Unit (GPU) of a system to create a stealthy communication channel between two malicious applications. We evaluate our new attack on two different real-world platforms: a GPU-dedicated general computing platform and a GPU-integrated embedded platform. Our results are the first to show that a GPU-based thermal covert channel attack is possible. From our experiments, we obtain a transmission rate of up to 8.75 bps with a very low error rate of less than 2% for a 12-bit packet size, which is comparable to CPU-based TCCs in the state of the art. Moreover, we show how existing state-of-the-art countermeasures for TCCs need to be extended to tackle the new GPU-based attack, at the cost of added overhead. To reduce this overhead, we propose our own DVFS-based countermeasure which mitigates the attack, while causing 2x less performance loss than the state-of-the-art countermeasure on a set of compute-intensive GPU benchmark applications.
00:39 CET		SIGFUZZ: A FRAMEWORK FOR DISCOVERING MICROARCHITECTURAL TIMING SIDE CHANNELS Authors: Chathura Rajapaksha, Leila Delshadtehrani, Manuel Egele and Ajay Joshi, Boston University, US Abstract Timing side channels can be inadvertently introduced into processor microarchitecture during the design process, mainly due to optimizations carried out to improve processor performance. These timing side channels have been used in various attacks including transient execution attacks on recent commodity processors. Hence, we need a tool to detect timing side channels during the design process. This paper presents SIGFuzz, a fuzzing-based framework for detecting microarchitectural timing side channels. A designer can use SIGFuzz to detect side channels early in the design flow and mitigate potential vulnerabilities associated with them. SIGFuzz generates a cycle-accurate microarchitectural trace for a program that executes on the target processor, it then uses two trace properties to identify side channels that would have formed by the program. These two trace properties evaluate the effect of each instruction in the program on the timing of its prior and later instructions, respectively. SIGFuzz also uses a statistical distribution of execution delays of instructions with the same mnemonic to flag potential side channels that manifest with different operands of an instruction. Furthermore, SIGFuzz automatically groups the detected side channels based on the microarchitectural activity trace (i.e. signature) of the instruction that triggered it. We evaluated SIGFuzz on two real-world open-source processor designs: Rocket and BOOM, and found three new side channels and two known side channels. We present a novel Spectre-style attack on BOOM based on a newly detected side channel.
00:39 CET		RUN-TIME INTEGRITY MONITORING OF UNTRUSTWORTHY ANALOG FRONT-ENDS Authors: Heba Salem and Nigel Topham, University of Edinburgh, GB Abstract Recent advances in hardware attacks, such as cross talk and covert channel based attacks, expose the structural and operational vulnerability of analog and mixed-signal circuit elements to the introduction of malicious and untrustworthy behaviour at run-time, potentially leading to adverse physical, personal, and environmental consequences. One untrustworthy behaviour of concern, is the introduction of abnormal/unexpected frequencies to the signals at the analog/ digital interface of a SoC, realised through intermittent bit-flipping or stuck-at-faults in the middle and lower bits of these signals. In this paper, we study the impact of these actions and propose integrity monitoring of signals of concern based on analysing the temporal and arithmetic relations between their samples. This paper presents a hybrid software/ hardware machine-learning based framework that consists of two phases; a run-time monitoring phase, and a trustworthiness assessment phase. The framework is evaluated with three different applications and its effectiveness in detecting the untrustworthy behaviour of concern is verified. This framework is device, application, and architecture agnostic, and relies only on analysing the output of the analog front-end, allowing its implementation in SoCs with on-chip and custom analog front-ends as well as those with outsourced and commercial off-the-shelf (COTS) analog front-ends.
00:39 CET		SPOILER-ALERT: DETECTING SPOILER ATTACK USING CUCKOO FILTER Authors: Jinhua Cui, Yiyun Yin, Congcong Chen and Jiliang Zhang, Hunan University, CN Abstract SPOILER exploits the dependency resolution logic serving the speculative load to leak information about phys- ical page mappings, which can accelerate reverse engineering of virtual-to-physical address mapping, thus greatly advancing Rowhammer and cache attacks. However, unlike attacks that attempt to leak secret data directly, the focus of SPOILER is address information. Further, existing approaches mainly are developed for detection and defense of the data leakage, which hence cannot be used for the SPOILER attack. This paper proposes the first hardware-level mechanism named SPOILER- ALERT, which can detect SPOILER violations via a cuckoo filter module. The cuckoo filter is embedded into the Memory Order Buffer component to screen buffer addresses on-the-fly and alert human users when a threshold of the number of buffer addresses is reached. We further inspect the internal filtering algorithm and optimise it to reduce false positives on SPOILER-ALERT. We assess SPOILER-ALERT based on prototype implementations on gem5. The results show a detection rate of 99.9% and only negligible performance loss. Finally, we discuss potential mitigation and long-term defenses against SPOILER.
00:39 CET		HUNTER: HARDWARE UNDERNEATH TRIGGER FOR EXPLOITING SOC-LEVEL VULNERABILITIES Authors: Sree Ranjani Rajendran¹, Shams Tarek¹, Benjamin Myers Hicks¹, Hadi Mardani Kamali¹, Farimah Farahmandi¹ and Mark Tehranipoor² ¹University of Florida, US; ²Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity, Associate Chair for Research and Strategic Initiatives, ECE Department, University of Florida, US Abstract Systems-on-chip (SoCs) have become increasingly large and complex, resulting in new threats and vulnerabilities, mainly related to system-level flaws. However, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively due to the lack of decisive (security) requirements and properties from the SoC designer's perspective. To enable a more comprehensive verification for system-level properties, this paper presents HUnTer (Hardware Underneath Trigger), a framework for identifying sets (sequences) of instructions at the processor unit (PU) that unveils the underneath hardware vulnerabilities. The HUnTer framework automates (i) threat modeling, (ii) threat-based formal verification, (iii) generation of counterexamples, and (iv) generation of snippet code for exploiting the vulnerability. The HUnTer framework also defines a security coverage metric (HUnT_Coverage) to measure the performance and efficacy of the proposed approach. Using the HUnTer framework on a RISC-V-based open-source SoC architecture, we conduct a wide variety of case studies of Trust-HUB vulnerabilities to demonstrate the high effectiveness of the proposed framework.
00:39 CET		MAXIMIZING THE POTENTIAL OF CUSTOM RISC-V VECTOR EXTENSIONS FOR SPEEDING UP SHA-3 HASH FUNCTIONS Authors: Huimin Li¹, Nele Mentens² and Stjepan Picek³ ¹Delft University of Technology, NL; ²KU Leuven, BE; ³Radboud University, NL Abstract SHA-3 is considered to be one of the most secure standardized hash functions. It relies on the Keccak-f[1,600] permutation, which operates on an internal state of 1,600 bits, mostly represented as a 5×5×64-bit matrix. While existing implementations process the state sequentially in chunks of typically 32 or 64 bits, the Keccak-f[1,600] permutation can benefit a lot from speedup through parallelization. This paper is the first to explore the full potential of parallelization of Keccak-f[1,600] in RISC-V based processors through custom vector extensions on 32-bit and 64-bit architectures. We analyze the Keccak-f[1,600] permutation, composed of five different step mappings, and propose ten custom vector instructions to speed up the computation. We realize these extensions in a SIMD processor described in SystemVerilog. We compare the performance of our designs to existing architectures based on vectorized application-specific instruction set processors (ASIP). We show that our designs outperform all related work thanks to our carefully selected custom vector instructions.
00:39 CET		PRIVACY-BY-SENSING WITH TIME-DOMAIN DIFFERENTIALLY-PRIVATE COMPRESSED SENSING Authors: Jianbo Liu, Boyang Cheng, Pengyu Zeng, Steven Davis, Muya Chang and Ningyuan Cao, University of Notre Dame, US Abstract With the ubiquitous IoT sensors and enormous real-time data generation, data privacy is becoming a critical societal concern. State-of-the-art privacy protection methods all demand significant hardware overhead due to computation-insensitive algorithm and divided sensor/security architecture. In this paper, we propose a generic time-domain circuit architecture that protects raw data by enabling a differentially-private compressed sensing (DP-CS) algorithm secured by physical unclonable functions (PUF). To address privacy concerns and hardware overhead at the same time, a robust unified PUF and time-domain mixed-signal (TD-MS) module is designed, where PUF enables private and secure entropy generation. To evaluate the proposed design against digital baseline, we performed experiments based on synthesized circuits and SPICE simulation, and measured a 2.9x area reduction and 3.2x energy gains. We also measured high-quality PUF generation with TD-MS circuit with a inter-die Hamming distance of 52% and a low intra-die Hamming distance of 2.8%. Furthermore, we performed attack and algorithm performance measurement demonstrating the proposed design preserves data privacy even under attack and the machine learning performance has minimal degradation (within 2%) compared to digital baseline.
00:39 CET		YOU CAN READ MY CODE, BUT YOU CAN'T EXECUTE IT Authors: YongGang Li¹, Yu Bao¹, Guoyuan Lin¹, Yaowen Ma¹ and Yeh-Ching Chung² ¹China University of Mining and Technology, CN; ²the Chinese University of Hong Kong (ShenZhen), CN Abstract Due to the Address Space Layout Randomization (ASLR), especially fine-grained ASLR, Code Reuse Attacks (CRAs) require memory probing to get available gadgets. Code reading is the most commonly used probing method. In theory, setting the code pages to be unreadable can prevent code reading. However, since the code pages are loaded dynamically, the existing methods cannot set all code pages as unreadable at one time. While we can change code page permissions on a page-by-page basis relying on dynamically page tracking, it is expensive. In addition, some special applications (such as debuggers) need to read the code page, and turning off the reading permission will affect their running. To solve these problems, this paper proposes a method ReadGate. It rebuilds the buddy system for memory allocation. This method allocates code pages in a specific memory pool to manage their read permissions. When the code reading is perceived, ReadGate disables the execution permission of the code page that is being read, and re-give its execution permission in a new address space. Experiments and analysis show that ReadGate can prevent the code that has been read from being used as gadgets without affecting the processes with code reading needs. In addition, the performance overhead introduced by ReadGate to the CPU is about 1.8%.
00:39 CET		ENERGY-EFFICIENT NTT DESIGN WITH ONE-BANK SRAM AND 2-D PE ARRAY Authors: Jianan Mu¹, HuaJie Tan², Jiawen Wu², Haotian Lu², Chip-Hong Chang³, Shuai Chen⁴, Shengwen Liang¹, Jing Ye¹, Huawei Li¹ and Xiaowei Li¹ ¹ICT, CAS, CN; ²School of Microelectronics, Tianjin University, China, CN; ³School of Electrical and Electronic Engineering (EEE) of NTU, SG; ⁴Rock-solid Security Lab. of Binary Semiconductor Co., Ltd., CN Abstract Number Theoretic Transform (NTT) can be used to accelerate the polynomial multiplication, which is one of the main operators in the next-generation cryptographic schemes. Energy-efficient hardware design methodology for NTT computation with different polynomial degrees and coefficient word lengths is lacking to proliferate applications that require NTT computation in energy-constrained devices. In NTT operation, more than half of the active energy consumption stems from memory accesses. Here, we propose a generalized design method to improve the energy efficiency of NTT operation by considering the effect of processing element (PE) geometry and memory organization on the data flow between PEs and memory. To decrease the number of data bits that are required to be accessed from the memory, a two-dimensional (2-D) PE array architecture is used. A pair of ping-pong buffers are proposed to transposed swap the coefficients to enable a single bank of memory to be used with the 2-D PE array to reduce the average memory bit access energy without compromising the throughput. Our experimental results show that this design method can produce NTT accelerators with up to 69.8% saving in average energy consumption compared with the existing designs based on multi-bank SRAM and one-bank SRAM with one-dimensional PE array with the same number of PEs and total memory size.
00:39 CET		COFHEE: A CO-PROCESSOR FOR FULLY HOMOMORPHIC ENCRYPTION EXECUTION Authors: Mohammed Nabeel Thari Moopan¹, Deepraj Soni², Mohammed Ashraf³, Mizan Gebremichael⁴, Homer Gamil³, Eduardo Chielle⁵, Ramesh Karri⁶, Mihai Sanduleanu⁴ and Michail Maniatakos⁵ ¹New York University, AE; ²New York University Tandon School of Engineering, US; ³NYUAD, AE; ⁴Khalifa University, AE; ⁵New York University Abu Dhabi, AE; ⁶NYU, US Abstract The migration of computation to the cloud has raised privacy concerns as sensitive data becomes vulnerable to attacks since they need to be decrypted for processing. Fully Homomorphic Encryption (FHE) mitigates this issue as it enables meaningful computations to be performed directly on encrypted data. Nevertheless, FHE is orders of magnitude slower than unencrypted computation, which hinders its practicality and adoption. Therefore, improving FHE performance is essential for its real world deployment. In this paper, we present our efforts to design, implement, fabricate, and post-silicon validate a co-processor for Fully Homomorphic Encryption dubbed CoFHEE. With a small design area of 12 mm^2, CoFHEE targets the optimal ASIC implementations of fundamental polynomial operations, such as polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which are underneath all higher-level FHE primitives. CoFHEE has native support of polynomial degrees of up to n = 2^14 with a coefficient size of 128 bits, and is fabricated in 55 nm CMOS technology, with a target frequency of 250 MHz. We evaluate our chip with performance and power experiments and compare it against state-of-the-art software implementations and other ASIC designs.
00:39 CET		A RAPID RESET 8-TRANSISTOR PHYSICALLY UNCLONABLE FUNCTION UTILISING POWER GATING Authors: Yujin Zheng¹, Alex Bystrov² and Alex Yakovlev² ¹Newcastle university, GB; ²Newcastle University, GB Abstract As promising hardware security primitives, Physically Unclonable Functions (PUFs) need error correction whilst regenerating Secret Key in cryptography. The proposed 8-Transistor (8T) PUF, which is coordinated with power gating technique, can dramatically speed up the key extraction process during manufacturing. In comparison, a single evaluation cycle of the proposed 8T PUF is more than 1000 times faster than its counterpart 6T-Static Random-Access Memory (SRAM) PUF. This enables the multiple evaluation even in the key regeneration phase in field, hence greatly reducing the number of errors and hardware penalty for error correction. The 8T-PUF cell derives from the 6T-SRAM cell. It is built to swiftly eliminate data retention and maximise physical mismatch. Meanwhile, power gating modules enable rapid power-on/off cycles only for the chosen PUF arrays. In addition, these modules are designed with a two-phase power gating method for minimising EMI and crosstalk amongst PUF cells whilst controlling the in-rush current and maintaining high performance. This method aims to improve PUF stability and protect PUF from side-channel attack. An architecture and implementation of the power-gated PUF is developed to accommodate fast multiple-evaluation of PUF Responses. Post-layout Monte Carlo simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and stochastic metrics for subsequent inclusion into PUF Responses, which comprises the novelty of the approach.

S_D9 (Extra session) Emerging design technologies for future computing

Date: Wednesday, 19 April 2023
Time: 00:39 - 00:00 CET

Time	Label	Presentation Title Authors
00:39 CET		SCALABLE COHERENT OPTICAL CROSSBAR ARCHITECTURE USING PCM FOR AI ACCELERATION Authors: Dan Sturm and Sajjad Moazeni, University of Washington, US Abstract Recent advancements in artificial intelligence (AI) and machine learning (ML) have been challenging our conventional computing paradigms by demanding enormous computing power at a dramatically faster pace than Moore's law. Analog-based optical computing has been recently proposed as a new approach to achieve large compute powers (TOPS) at high energy-efficiency (TOPS/W), which makes them suitable for AI acceleration in datacenters and supercomputers. However, proposed implementations so far suffer from lack of scalability, large footprints and high power consumption, and lack of practical system-level architectures to become integrated within existing datacenter architecture for real-world applications. In this work, we present a truly scalable optical AI accelerator based on a crossbar architecture. We have considered all major roadblocks and address them in this design. Weights will be stored on chip using phase change material (PCM) that can be monolithically integrated in silicon photonic processes. This coherent crossbar architecture can be extended to large scales without the need for any multi-wavelength laser sources. All electro-optical components and circuit blocks are modeled based on measured performance metrics in monolithic silicon photonics 45nm for this work which can be co-packaged with advanced SoC and HBM memories. We also present a system-level modeling and analysis of our chip's performance for the Resnet-50 V1.5 neural network, considering all critical parameters, including memory size, array size, photonic losses, and energy consumption of peripheral electronics including ADC and DACs. Both on- chip SRAM and off-chip DRAM energy overheads have been considered in this modeling. We additionally address how using a dual-core crossbar design can eliminate programming time overhead at practical SRAM block sizes and batch sizes. Our results show that a 128 x 128 proposed architecture can achieve inference per second (IPS) similar to Nvidia A100 GPU at 15.4× lower power and 7.24× lower area.
00:39 CET		MIXED-SIGNAL MEMRISTOR-BASED ITERATIVE MONTGOMERY MODULAR MULTIPLICATION Authors: Mehdi Kamal¹ and Massoud Pedram² ¹University of Southern California, US; ²USC, US Abstract In this paper, we present a mixed-signal implementation of iterative Montgomery multiplication algorithm (called X-IMM) for using in large arithmetic word size (LAWS) computations. LAWS is mainly utilized in security applications such as lattice-based cryptography where the width of the input operands may be equal to or larger than 1,024 bits. The proposed architecture is based on the iterative implementation of Montgomery multiplication (MM) algorithm where some critical parts of the multiplication are computed in the analog domain by mapping them on the memristor crossbar. Using a memristor crossbar reduces the area usage and latency of the modular multiplication unit compared to its fully digital implementation. The devised mixed-signal MM implementation is scalable by cascading the smaller X-IMMs to support dynamically adjustable larger operand sizes at runtime. The effectiveness of the proposed MM structure is assessed in the 45nm technology and the comparative studies show that the proposed 1,024-bit Radix-4 (Radix-16) Montgomery multiplication architecture provides about 13{\%} (22{\%}) higher $GOPS/mm^2$ compared to the state-of-the-art digital implementations of the iterative Montgomery multipliers.
00:39 CET		ODLPIM: A WRITE-OPTIMIZED AND LONG-LIFETIME RERAM-BASED ACCELERATOR FOR ONLINE DEEP LEARNING Authors: Heng Zhou¹, Bing Wu², Huan Cheng¹, Wei Zhao¹, Xueliang Wei¹, Jinpeng Liu¹, Dan Feng¹ and Wei Tong³ ¹Huazhong University of Science and Technology, CN; ²Huazhong university of science and technology, CN; ³HUST, CN Abstract ReRAM-based Processing-In-Memory (PIM) architectures have demonstrated high energy efficiency and performance in deep neural network (DNN) acceleration. Most of the existing PIM accelerators for DNN focus on offline batch learning (OBL) which require the whole dataset to be available before training. However, in the real world, data instances arrive in sequential settings, and even the data pattern may change, which calls concept drift. OBL requires expensive retraining to solve concept drift, whereas ODL is evidenced to be a better solution to keep the model evolving over streaming data. Unbalanced writes degrade the lifetime of the PIM accelerator. However, when ODL optimizes models over a large-scale data stream, this issue is more severe than in OBL, due to the heavier weight updates, resulting in the amplification of unbalanced writes and lifetime deterioration. In this work, we propose ODLPIM, an online deep learning PIM accelerator that extends system lifetime through algorithm-hardware co-optimization. ODLPIM adopts a novel write-optimized parameter update (WARP) scheme that reduces the non-critical weight updates in hidden layers. Besides, a table-based inter-crossbar wear-leveling (TIWL) scheme is proposed and applied to the hardware controller to achieve wear-leveling between crossbars for lifetime improvement. Experiments show that WARP reduces weight updates on average to 15.25% and up to 24% compared to that without WARP, and eventually prolongs system lifetime on average to 9.65% and up to 26.81%, with a negligible rise in cumulative error rate (up to 0.31%). By combining WARP with TIWL, the lifetime of ODLPIM is improved by an average of 12.59X and up to 17.73X.
00:39 CET		SAT-BASED QUANTUM CIRCUIT ADAPTATION Authors: Sebastian Brandhofer¹, Jinwoong Kim², Siyuan Niu³ and Nicholas Bronn⁴ ¹University of Stuttgart, DE; ²Delft University of Technology, NL; ³University of Montpellier, FR; ⁴IBM Quantum, US Abstract As the nascent field of quantum computing develops, an increasing number of quantum hardware modalities, such as superconducting electronic circuits, semiconducting spins, ion traps, and neutral atoms, become available for performing quantum computations. These quantum hardware modalities exhibit varying characteristics and implement different universal quantum gate sets that may e.g. contain several distinct two-qubit quantum gates. Adapting a quantum circuit from a, possibly hardware-agnostic, universal quantum gate set to the quantum gate set of a target hardware modality has a crucial impact on the fidelity and duration of the intended quantum computation. However, current quantum circuit adaptation techniques only apply a specific decomposition or allow only for local improvements to the target quantum circuit possibly resulting in a quantum computation on the target hardware modality with decreased fidelity or increased qubit idle time. These issues are further aggravated by the multiple options of hardware-native quantum gates rendering multiple universal quantum gates sets accessible to a hardware modality. In this work, we developed a satisfiability modulo theories model that determines an optimized quantum circuit adaptation given a set of allowed substitutions and decompositions, a target hardware modality and the quantum circuit to be adapted. We further discuss the physics of the semiconducting spins hardware modality, show possible implementations of diverse two-qubit quantum gates, and evaluate the developed SMT model on the semiconducting spins hardware modality. Using the developed quantum circuit adaptation method, the Hellinger fidelity could be improved by up to 40% and the qubit idle time could be decreased by up to 87% compared to prior quantum circuit adaptation techniques.
00:39 CET		ULTRA-DENSE 3D PHYSICAL DESIGN ENABLES NEW ARCHITECTURAL DESIGN POINTS WITH LARGE BENEFITS Authors: Tathagata Srimani¹, Robert Radway¹, Jinwoo Kim², Kartik Prabhu¹, Dennis Rich¹, Carlo Gilardi¹, Priyanka Raina¹, Max Shulaker³, Sung Kyu Lim² and Subhasish Mitra¹ ¹Stanford University, US; ²Georgia Tech, US; ³MIT, US Abstract This paper focuses on iso-on-chip-memory-capacity and iso-footprint Energy-Delay-Product (EDP) benefits of ultra-dense 3D, e.g., monolithic 3D (M3D), computing systems vs. corresponding 2D designs. Simply folding existing 2D designs into corresponding M3D physical designs yields limited EDP benefits (~1.4×). New M3D architectural design points that exploit M3D physical design are crucial for large M3D EDP benefits. We perform comprehensive architectural exploration and detailed M3D physical design using foundry M3D process design kit and standard cell library for front-end-of-line (FEOL) Si CMOS logic, on-chip back-end-of-line (BEOL) memory, and a single layer of on-chip BEOL FETs. We find new M3D AI/ML accelerator architectural design points that have iso-footprint, iso-on-chip-memory-capacity EDP benefits ranging from 5-11.5× vs. corresponding 2D designs (containing only FEOL Si CMOS and on-chip BEOL memory). We also present an analytical framework to derive architectural insights into these benefits, showing that our principles extend to many architectural design points across various device technologies.
00:39 CET		MEMRISTOR-SPIKELEARN: A SPIKING NEURAL NETWORK SIMULATOR FOR STUDYING SYNAPTIC PLASTICITY UNDER REALISTIC MEMRISTOR BEHAVIORS Authors: Yuming Liu¹, Angel Yanguas-Gil², Sandeep Madireddy² and Yanjing Li¹ ¹University of Chicago, US; ²Argonne National Laboratory, US Abstract Memristor-based implementations of synaptic plasticity in spiking neural networks provide a promising approach towards energy-efficient online learning. However, there are no existing methods or frameworks that enable the study of synaptic plasticity in real-world workloads under realistic memristor device behaviors. To fill this important gap, we present the new Memristor-Spikelearn simulator, which is capable of incorporating memristor models with the proper levels of details, and thus simulating synaptic plasticity under realistic device behaviors. Using this simulator, we demonstrate that: 1. results obtained using a simplified memristor device model can be misleading, and a realistic device model in simulation is essential; and 2. it is also essential to fine-tune a synaptic plasticity algorithm according to the characteristics of the underlying memristor device, e.g., by controlling how weight values are mapped to conductance values, which can yield drastically different energy-accuracy trade-offs. Moreover, our simulator is extensible and scalable.
00:39 CET		EXPLOITING KERNEL COMPRESSION ON BNNS Authors: Franyell Silfa, Jose Maria Arnau and Antonio González, Polytechnic University of Catalonia, ES Abstract Binary Neural Networks (BNNs) are showing tremendous success on realistic image classification tasks. Notably, their accuracy is similar to the state-of-the-art accuracy obtained by full-precision models tailored to edge devices. In this regard, BNNs are very amenable to edge devices since they employ 1-bit to store the inputs and weights, and thus, their storage requirements are low. Moreover, BNNs computations are mainly done using xnor and pop-counts operations which are implemented very efficiently using simple hardware structures. Nonetheless, supporting BNNs efficiently on mobile CPUs is far from trivial since their benefits are hindered by frequent memory accesses to load weights and inputs. In BNNs, a weight or an input is stored using one bit, and aiming to increase storage and computation efficiency, several of them are packed together as a sequence of bits. In this work, we observe that the number of unique sequences representing a set of weights or inputs is typically low (i.e., 512). Also, we have seen that during the evaluation of a BNN layer, a small group of unique sequences is employed more frequently than others. Accordingly, we propose exploiting this observation by using Huffman Encoding to encode the bit sequences and then using an indirection table to decode them during the BNN evaluation. Also, we propose a clustering-based scheme to identify the most common sequences of bits and replace the less common ones with some similar common sequences. As a result, we decrease the storage requirements and memory accesses since the most common sequences are encoded with fewer bits. In this work, we extend a mobile CPU by adding a small hardware structure that can efficiently cache and decode the compressed sequence of bits. We evaluate our scheme using the ReAacNet model with the Imagenet dataset on an ARM CPU. Our experimental results show that our technique can reduce memory requirement by 1.32x and improve performance by 1.35x.
00:39 CET		AXI-PACK: NEAR-MEMORY BUS PACKING FOR BANDWIDTH-EFFICIENT IRREGULAR WORKLOADS Authors: Chi Zhang¹, Paul Scheffler¹, Thomas Benz¹, Matteo Perotti² and Luca Benini¹ ¹Integrated Systems Laboratory, ETH Zurich, CH; ²ETH Zürich, CH Abstract Data-intensive applications involving irregular memory streams are inefficiently handled by modern processors and memory systems highly optimized for regular, contiguous data. Recent work tackles these inefficiencies in hardware through core-side stream extensions or memory-side prefetchers and accelerators, but fails to provide end-to-end solutions which also achieve high efficiency in on-chip interconnects. We propose AXI-Pack, an extension to ARM's AXI4 protocol introducing bandwidth-efficient strided and indirect bursts to enable end-to-end irregular streams. AXI-Pack adds irregular stream semantics to memory requests and avoids inefficient narrow-bus transfers by packing multiple narrow data elements onto a wide bus. It retains full compatibility with AXI4 and does not require modifications to non-burst-reshaping interconnect IPs. To demonstrate our approach end-to-end, we extend an open-source RISC-V vector processor to leverage AXI-Pack at its memory interface for strided and indexed accesses. On the memory side, we design a banked memory controller efficiently handling AXI-Pack requests. On a system with a 256-bit-wide interconnect running FP32 workloads, AXI-Pack achieves near-ideal peak on-chip bus utilizations of 87% and 39%, speedups of 5.4x and 2.4x, and energy efficiency improvements of 5.3x and 2.1x over a baseline using an AXI4 bus on strided and indirect benchmarks, respectively.
00:39 CET		SIMSNN: A WEIGHT-AGNOSTIC RERAM-BASED SEARCH-IN-MEMORY ENGINE FOR SPIKING NEURAL NETWORK ACCELERATION Authors: Fangxin Liu¹, Xiaokang Yang¹ and Li Jiang² ¹Shanghai Jiaotong University, CN; ²Shanghai Jiao Tong University, CN Abstract Bio-plausible spiking neural networks (SNNs) have gained a great momentum due to its inherent efficiency of processing event-driven information. The dominant computation--matrix bit-wise And-Add operations--in SNN is naturally fit for process-in-memory architecture~(PIM). The long input spike train of SNN and the bit-serial processing mechanism of PIM, however, incur considerable latency and frequent analog-to-digital conversion, offsetting the performance gain and energy-efficiency. In this paper, we propose a novel Search-in-Memory~(SIM) architecture to accelerate the SNN inference, named SIMSnn. Rather than processing the input bit-by-bit over multiple time steps, SIMSnn can take in a sequence of spikes and search the result by parallel associative matches in the CAM crossbar. We explore the cascade search mechanism and the temporal pipeline design to enhance the parallelism of the search across time windows. The proposed SIMSnn can leverage the non-structured pruning mechanism, which is unusable for most PIM architecture, to further reduce the CAM overhead. As a weight-agnostic SNN accelerator, SIMSnn can adapt to various evolving SNNs without rewriting the crossbar array. Experimental results show that the proposed SIMSnn achieves $25.3 imes$ higher energy-efficiency and $13.7 imes$ speedup on average than the ISAAC-like design. Compared to the state-of-the-art PIM design, NEBULA, SIMSnn can also achieve up to $7.9 imes$ energy savings and $5.7 imes$ speedup.
00:39 CET		BOMIG: A MAJORITY LOGIC SYNTHESIS FRAMEWORK FOR AQFP LOGIC Authors: Rongliang Fu¹, Junying Huang², Mengmeng Wang³, Yoshikawa Nobuyuki³, Bei Yu⁴, Tsung-Yi Ho⁴ and Olivia Chen⁵ ¹The Chinese University of Hong Kong, CN; ²State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China, CN; ³Yokohama National University, JP; ⁴The Chinese University of Hong Kong, HK; ⁵Tokyo City University, JP Abstract As an energy-efficient superconductor logic with no static power consumption and extremely low switching energy, adiabatic quantum-flux-parametron (AQFP) logic is a promising candidate for building energy-efficient computing systems. Due to the native majority function in AQFP logic, which can represent more complex logic with the same cost as the AND/OR function, the design of AQFP circuits differs from conventional digital circuits. Compared with AND-OR-inverter (AOI) logic structure commonly used in CMOS technology, majority-inverter logic enables a smaller size and depth of a circuit and is more suitable for AQFP logic. However, AQFP logic needs buffer and splitter insertion to satisfy the clock-based synchronization requirement and fan-out limitation, making traditional majority-based logic synthesis methods not applicable. The paper combines logic optimization with buffer and splitter insertion and proposes a novel logic synthesis framework to minimize the size and depth of AQFP circuits. First, logic synthesis of AQFP circuits is regarded as a black-box problem, where AOI and majority-based transformation methods construct the feasible domain, and the objective function is the normalized energy-delay-product of AQFP circuits. Then, an Bayesian optimization method is used to explore an optimal fixed-length transformation sequence applied to AQFP logic optimization. Experimental results show that the proposed method has a significant improvement in terms of both JJ number and circuit depth compared to the state-of-the-art.

BPA_10 Hardware Security

Date: Wednesday, 19 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		SOCFUZZER: SOC VULNERABILITY DETECTION USING COST FUNCTION ENABLED FUZZ TESTING Authors: Muhammad Monir Hossain¹, Arash Vafaei¹, Kimia Zamiri Azar¹, Fahim Rahman¹, Farimah Farahmandi¹ and Mark Tehranipoor² ¹University of Florida, US; ²Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity, Associate Chair for Research and Strategic Initiatives, ECE Department, University of Florida, US Abstract The modern System-on-Chips (SoCs), with numerous complex and heterogeneous intellectual properties (IPs), and the inclusion of highly-sensitive assets, become the target of malicious attacks. However, security verification of these SoCs remains behind compared to the advances in functional verification, mostly because it is difficult to formally define the accurate threat model(s). Few recent studies have investigated the possibility of engaging fuzz testing for hardware-oriented vulnerability detection. However, they suffer from several limitations, i.e., lack of cross-layer co-verification, the need for expert knowledge, and the inability to capture detailed hardware interactions. In this paper, we propose SoCFuzzer, an automated SoC verification assisted by fuzz testing for detecting SoC security vulnerabilities. Unlike the previous HW-oriented fuzz testing studies, which mostly rely on traditional (code) coverage-based metrics, in SoCFuzzer, we develop (i) generic evaluation metrics for fuzzing the hardware domain, and (ii) security-oriented cost function. This relieves designers of making correlations between coverage metrics, test data, and possible vulnerabilities. The SoCFuzzer cost functions are defined high level, allowing us to follow the gray-box model, which requires less detailed and interactive information from the design-under-test. Our experiments on an open-source RISC-Vbased SoC show the efficiency of these metrics and cost functions on fuzzing for generating cornerstone inputs to trigger the vulnerability conditions with faster convergence.
00:39 CET		NON-PROFILED SIDE-CHANNEL ASSISTED FAULT ATTACK: A CASE STUDY ON DOMREP Authors: Sayandeep Saha, Prasanna Ravi, Dirmanto Jap and Shivam Bhasin, Nanyang Technological University, Singapore, SG Abstract Recent work has shown that Side-Channel Attacks (SCA) and Fault Attacks (FA) can be combined, forming an extremely powerful adversarial model, which can bypass even some strongest protections against both FA and SCA. However, such strongest form of combined attack comes with some practical challenges -- 1) a profiled setting with multiple fault locations is needed; 2) fault models are restricted to single-bit set-reset/flips; 3) the input needs to be repeated several times. In this paper, we propose a new combined attack strategy called SCA-NFA that works in a non-profiled setting. Assuming knowledge of plaintexts/ciphertexts and exploiting bitsliced implementations of modern ciphers, we further relax the assumptions on the fault model, and the number of fault locations -- random multi-bit fault at a single fault location is sufficient for recovering several secret bits. Furthermore, the inputs are allowed to be varied, which is required in several practical use cases. The attack is validated on a recently proposed countermeasure called DOMREP, which individually provides SCA and FA protection of arbitrary order. Practical validation for an open-source masked implementation of GIMLI with DOMREP extension on STM32F407G, using electromagnetic fault and electromagnetic SCA, shows that SCA-NFA succeeds in around 10000 measurements.
00:39 CET		EFFICIENT SOFTWARE MASKING OF AES THROUGH INSTRUCTION SET EXTENSIONS Authors: Songqiao Cui and Josep Balasch, KU Leuven, BE Abstract Masking is a well-studied countermeasure to protect software implementations against side-channel attacks. For the case of AES, incorporating masking often requires to implement internal transformations using finite field arithmetic. This results in significant performance overheads, mostly due to finite field multiplications, which are even worsened when no lookup tables are used. In this work, we extend a RISC-V core with custom instructions to accelerate AES finite field arithmetic. With a 3.4% area increase, we measure 7.27x and 5.45x speed up over software-only implementations of first-order Boolean Masking and Inner Product Masking, respectively. We also investigate vectorized instructions capable of exploiting the intra-block and inter-block parallelism in the implementation. Our implementations avoid the use of lookup tables, run in constant time, and show no evidence of first-order leakage when evaluated on an FPGA.

BPA_3 Efficient processing for NNs

Date: Wednesday, 19 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		AUTOMATED ENERGY-EFFICIENT DNN COMPRESSION UNDER FINE-GRAIN ACCURACY CONSTRAINTS Authors: Ourania Spantidi and Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US Abstract Deep Neural Networks (DNNs) are utilized in a variety of domains, and their computation intensity is stressing embedded devices that comprise limited power budgets. DNN compression has been employed to achieve gains in energy consumption on embedded devices at the cost of accuracy loss. Compression-induced accuracy degradation is addressed through fine-tuning or retraining, which can not always be feasible. Additionally, state-of-art approaches compress DNNs with respect to the average accuracy achieved during inference, which can be a misleading evaluation metric. In this work, we explore more fine-grain properties of DNN inference accuracy, and generate energy-efficient DNNs using signal temporal logic and falsification jointly through pruning and quantization. We offer the ability to control at run-time the quality of the DNN inference, and propose an automated framework that can generate compressed DNNs that satisfy tight fine-grain accuracy requirements. The conducted evaluation on the ImageNet dataset has shown over 30% in energy consumption gains when compared to baseline DNNs.
00:39 CET		A SPEED- AND ENERGY-DRIVEN HOLISTIC TRAINING FRAMEWORK FOR SPARSE CNN ACCELERATORS Authors: Yuanchen Qu, Yu Ma and Pingqiang Zhou, Shanghaitech University, CN Abstract Sparse convolution neural network (CNN) accelerators have shown to achieve high processing speed and low energy consumption by leveraging zero weights or activations, which can be further optimized by finely tuning the sparse activation maps in training process. In this paper, we propose a CNN training framework targeting at reducing energy consumption and processing cycles in sparse CNN accelerators. We first model accelerator's energy consumption and processing cycles as functions of layer-wise activation map sparsity. Then we leverage the model and propose a hybrid regularization approximation method to further sparsify activation maps in the training process. The results show that our proposed framework can reduce the energy consumption of Eyeriss by 31.33%, 20.6% and 26.6% on MobileNet-V2, SqueezeNet and Inception-V3. In addition, the processing speed can be increased by 1.96????, 1.4???? and 1.65???? respectively.
00:39 CET		HARDWARE EFFICIENT WEIGHT-BINARIZED SPIKING NEURAL NETWORKS Authors: Chengcheng Tang and Jie Han, University of Alberta, CA Abstract The advancement in spiking neural networks (SNNs) provides a promising and alternative approach to conventional artificial neural networks (ANNs) with higher energy efficiency. However, the significant requirements on memory usage presents a performance bottleneck on resource constrained devices. Inspired by the notion of binarized neural networks (BNNs), we incorporate the design principle in BNNs into that of SNNs to reduce the stringent resource requirements. Specifically, the weights are binarized to 1 and -1 to represent excitatory and inhibitory synapses, so the proposed design is referred to as a weightbinarized spiking neural network (WB-SNN). In the WB-SNN, only one bit is used for the weight or a spike; for the latter, 1 and 0 indicate a spike and no spike, respectively. A priority encoder is used to identify the index of an active neuron as the basic unit to construct the WB-SNN. A fully connected neural network is designed that consists of an input layer, an output layer, and fully connected layers of different sizes. A counter is then utilized in each neuron to complete the accumulation of weights. The WB-SNN design is validated by using a multi-layer-perceptron on the MNIST dataset. Hardware implementations on FPGAs show that the WB-SNN attains a significant saving of memory with only a limited accuracy loss compared with its SNN and BNN counterparts.

BPA_4 Hardware accelerators

Date: Wednesday, 19 April 2023
Time: 08:30 - 10:30 CET

Time	Label	Presentation Title Authors
00:39 CET		ACCELERATING GUSTAVSON-BASED SPMM ON EMBEDDED FPGAS WITH ELEMENT-WISE PARALLELISM AND ACCESS PATTERN-AWARE CACHES Authors: Shiqing Li and Weichen Liu, Nanyang Technological University, SG Abstract The Gustavson's algorithm (i.e., the row-wise product algorithm) shows its potential as the backbone algorithm for sparse matrix-matrix multiplication (SpMM) on hardware accelerators. However, it still suffers from irregular memory accesses and thus its performance is bounded by the off-chip memory traffic. Previous works mainly focus on high bandwidth memory-based architectures and are not suitable for embedded FPGAs with traditional DDR. In this work, we propose an efficient Gustavson-based SpMM accelerator on embedded FPGAs with element-wise parallelism and access pattern-aware caches. First of all, we analyze the parallelism of the Gustavson's algorithm and propose to perform the algorithm with element-wise parallelism, which reduces the idle time of processing elements caused by synchronization. Further, we show a counter-intuitive example that the traditional cache leads to worse performance. Then, we propose a novel access pattern-aware cache scheme called SpCache, which provides quick responses to reduce bank conflicts caused by irregular memory accesses and combines streaming and caching to handle requests that access ordered elements of unpredictable length. Finally, we conduct experiments on the Xilinx Zynq-UltraScale ZCU106 platform with a set of benchmarks from the SuiteSparse matrix collection. The experimental results show that the proposed design achieves an average 1.62x performance speedup compared to the baseline.
00:39 CET		GRAPHITE: ACCELERATING ITERATIVE GRAPH ALGORITHMS ON RERAM ARCHITECTURES VIA APPROXIMATE COMPUTING Authors: Dwaipayan Choudhury, Ananth Kalyanaraman and Partha Pratim Pande, Washington State University, US Abstract ReRAM-based Processing-in-Memory (PIM) offers a promising paradigm for computing near data, making it an attractive platform of choice for graph applications that suffer from sparsity and irregular memory access. However, the performance of ReRAM-based graph accelerators is limited by two key challenges – significant storage requirements (particularly due to wasted zero cell storage of a graph's adjacency matrix), and significant amount of on-chip traffic between ReRAM-based processing elements. In this paper we present, GraphIte, an approximate computing-based framework for accelerating iterative graph applications on ReRAM-based architectures. GraphIte uses sparsification and approximate updates to achieve significant reductions in ReRAM storage and data movement. Our experiments on PageRank and community detection show that our proposed architecture outperforms a state-of-the-art ReRAM-based graph accelerator by up to 83.4% reduction in execution time while consuming up to 87.9% less energy for a range of graph inputs and workloads.
00:39 CET		PEDAL: A POWER EFFICIENT GCN ACCELERATOR WITH MULTIPLE DATAFLOWS Authors: Yuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan and Trevor Mudge, University of Michigan, US Abstract Graphs are ubiquitous and used in many domains due to their ability to describe structural relations. Graph Convolutional Networks (GCNs) emerge in recent years and are rapidly developing due to their capability to analyze graph-structured data. The nature of graph-structured data leads to irregular memory accesses in the aggregation phase of GCN, making it hard for general-purpose architectures like CPUs and GPUs to utilize their computing resources. In this paper, we propose PEDAL, a power-efficient accelerator for GCN inference supporting multiple dataflows. PEDAL chooses the best-fit dataflow and phase ordering based on input graph characteristics and GCN algorithm, achieving both efficiency and flexibility. PEDAL also features a lightweight processing element design, and uses a relatively small number of processing elements for better power efficiency while achieving good performance. PEDAL achieves 144.5, 9.36, and 2.55 times speedup compared to CPU, GPU, and HyGCN respectively, and 8856, 1606, 8.4, and 1.78 times better power efficiency compared to CPU, GPU, HyGCN, and EnGN.

S_A2 Application specific circuits and systems

Date: Wednesday, 19 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		A DECENTRALIZED FRONTIER QUEUE FOR IMPROVING SCALABILITY OF BREADTH-FIRST-SEARCH ON GPUS Authors: Chou-Ying Hsieh¹, Po-Hsiu Cheng², Chia-Ming Chang³ and Sy-Yen Kuo⁴ ¹+886971285958, TW; ²r10943151ntu [dot] edu [dot] tw, TW; ³r10921101ntu [dot] edu [dot] tw, TW; ⁴sykuontu [dot] edu [dot] tw, TW Abstract Breath-first-search (BFS) algorithm is the fundamental building block of broad applications from the electronic design automation (EDA) field to social network analysis. With the targeting data set size growing considerable, researchers have turned to developing parallel BFS (PBFS) algorithms and accelerating them with graph processing units (GPUs). The frontier queue, the core idea among state-of-the-art designs of PBFS, opens the door to neighbor visiting parallelism. However, the traditional centralized frontier queue in PBFS suffers from a dramatic collision when excessive threads simultaneously operate on it. Furthermore, the growing size of the graph puts considerable pressure on memory space. Therefore, we first identify the challenges of current frontier queue implementations. To solve these challenges, we proposed the decentralized frontier queue (DFQ), which separates a centralized queue into multiple tiny sub-queues for scattering the atomic operation collision on these queues. We also developed the novel overflow-free enqueue and asynchronous sub-queue drain methods to avoid the overflow issue on the naive sub-queue design. With these two optimizations, the memory consumption of the frontier queue can be constant rather than exponentially growing along with the vertex number of the graph. In our experiments, we showed that our design could have better scalability and grain averagely 1.04x speedup on the execution in the selected benchmark suit with considerable memory space efficiency.
00:39 CET		TIMELY FUSION OF SURROUND RADAR/LIDAR FOR OBJECT DETECTION IN AUTONOMOUS DRIVING SYSTEMS Authors: Wenjing XIE¹, Tao Hu¹, Neiwen Ling², Guoliang Xing², Shao-Shan Liu³ and Nan Guan¹ ¹City University of Hong Kong, HK; ²The Chinese University of Hong Kong, HK; ³BeyonCa, CN Abstract Fusion of multiple sensor modalities, such as camera, Lidar and Radar, are commonly used in autonomous driving systems to fully utilize the complementary advantages of different sensors. Surround Radar/Lidar can provide 360-degree view sampling with the minimal cost, which are promising sensing hardware solutions for autonomous driving systems. However, due to the intrinsic physical constraints, the rotating speed (i.e., the frequency to generate data frames) of surround Radar is much lower than surround Lidar, and existing Radar/Lidar fusion methods have to work at the low frequency of surround Radar, which cannot meet the high responsiveness requirement of autonomous driving systems. This paper develops techniques to fuse surround Radar/Lidar with working frequency only limited by the faster surround Lidar instead of the slower surround Radar, based on the state-of-the-art Radar/Lidar DNN model MVDNet. The basic idea of our approach is simple: we let MVDNet work with temporally unaligned data from Radar/Lidar, so that fusion can take place at any time when a new Lidar data frame arrives, instead of waiting for the slow Radar data frame. However, directly applying MVDNet to temporally unaligned Radar/Lidar data greatly degrades its object detection accuracy. The key information revealed in this paper is that we can achieve high output frequency with little accuracy loss by enhancing the training procedure to explore the temporal redundancy in fusion procedure of MVDNet so that it can tolerate the temporal unalignment of the input data. We explore several different ways of training enhancement and compare them quantitatively with experiments.
00:39 CET		A LIGHTWEIGHT AND ADAPTIVE CACHE ALLOCATION SCHEME FOR CONTENT DELIVERY NETWORKS Authors: Ke Liu¹, Hua Wang², Ke Zhou¹ and Cong Li³ ¹Wuhan National Laboratory for Optoelectronics (WNLO) of Huazhong University of Science and Technology (HUST), CN; ²Huazhong University of Science and Technology, CN; ³Tencent, CN Abstract Content delivery networks (CDNs) caching systems use multi-tenant shared caching due to their operational simplicity. However, this approach often results in significant space waste and requires timely space allocation. On the one hand, the accuracy and reliability of the existing static allocation schemes are not high. On the other hand, due to the large number of tenants in CDNs, the dynamic allocation schemes based on miss ratio curve (MRC) for cache space allocation will cause high computational overheads and performance fluctuations. As a result, none of these existing solutions can be used directly in the CDN caching system. In this paper, we propose a lightweight and adaptive cache allocation scheme for CDNs (LACA). Rather than configuring near-optimal configurations for each tenant, LACA detects in real time whether any tenants are using cache space inefficiently, and then constructs local MRCs for those tenants. Finally, the space to be adjusted is calculated from the local MRCs. We have deployed LACA in Company-T's CDN system and LACA can reduce the miss ratio by 27.1% and reduce the average user access latency by 28.5ms. Then, in terms of the accuracy of constructing local MRCs, LACA is compared with several current more advanced schemes. Experimental results demonstrate that LACA constructs a higher-accuracy local MRC with little overhead. In addition, LACA can adjust the space as fast as once a minute.
00:39 CET		TBERT: DYNAMIC BERT INFERENCE WITH TOP-K BASED PREDICTORS Authors: Zejian Liu¹, kun zhao² and Jian Cheng² ¹National Laboratory of Pattern Recognition, Institute of Automation, Chinese Academy of Sciences, CN; ²Institute of Automation, CN Abstract Dynamic inference is a compression method that adaptively prunes unimportant components according to the input at the inference stage, which can achieve a better trade-off between computational complexity and model accuracy than static compression methods. However, there are two limitations in previous works. The first one is that they usually need to search the threshold on the evaluation dataset to achieve the target compression ratio, but the search process is non-trivial. The second one is that these methods are unstable. Their performance will be significantly degraded on some datasets, especially when the compression ratio is high. In this paper, we propose TBERT, a simple yet stable dynamic inference method. TBERT utilizes the top-k-based pruning strategy which allows accurate control of the compression ratio. To enable stable end-to-end training of the model, we carefully design the structure of the predictor. Moreover, we propose adding auxiliary classifiers to help the model's training. Experimental results on the GLUE benchmark demonstrate that our method achieves higher performance than previous state-of-the-art methods.
00:39 CET		TOKEN ADAPTIVE VISION TRANSFORMER WITH EFFICIENT DEPLOYMENT FOR FINE-GRAINED IMAGE RECOGNITION Authors: Chonghan Lee¹, Rita Brufau², Ke Ding² and Vijaykrishnan Narayanan¹ ¹Penn State University, US; ²Intel, US Abstract Fine-grained Visual Classification (FGVC) aims to distinguish object classes belonging to the same category, e.g., different bird species or models of vehicles. The task is more challenging than ordinary image classification due to the subtle inter-class differences. Recent works proposed deep learning models based on the vision transformer (ViT) architecture with its self-attention mechanism to locate important regions of the objects and derive global information. However, deploying them on resource-restricted devices is challenging due to their intensive computational cost and memory footprint. To improve inference efficiency, previous approaches require manually designing the model architecture and training a separate model for each computational budget. In this work, we propose Token Adaptive Vision Transformer (TAVT) that dynamically drops out tokens and can be used for various inference scenarios across many devices after training the model once. Our adaptive model can switch among different token drop configurations at run time, providing instant accuracy-efficiency trade-offs. We train a vision transformer with a progressive token pruning scheme, eliminating a large number of redundant tokens in the later layers. We then conduct a multi-objective evolutionary search with the overall number of floating point operations (FLOPs) as its efficiency constraint to find the token pruning schemes that maximize accuracy and efficiency under various computational budgets. Empirical results show that our proposed TAVT dramatically speeds up the inference latency by up to 10x and reduces memory requirements and FLOPs by up to 5.5 x and 13x respectively while achieving competitive accuracy compared to prior ViT-based state-of-the-art approaches.
00:39 CET		END-TO-END OPTIMIZATION OF HIGH-DENSITY E-SKIN DESIGN: FROM SPIKING TAXEL READOUT TO TEXTURE CLASSIFICATION Authors: Jiaqi Wang, Mark Daniel Alea, Jonah Van Assche and Georges Gielen, KU Leuven, BE Abstract Spiking readout architectures are a promising low- power solution for high-density e-skins. This paper proposes the end-to-end model-based optimization of a high-density neuro- morphic e-skin solution, from the taxel readout to the texture classification. Architectural explorations include the spike coding and preprocessing, and the neural network used for classification. Simple rate coding preprocessing to spiking outputs from a modeled low-resolution on-chip spike encoder is demonstrated to achieve a comparable texture classification accuracy of 90 % at lower power consumption compared to the state of art. The modeling has also been extended from single-channel sensor recording to time-shifted multi-taxel readout. Applying this optimization to an actual tactile sensor array, the classification accuracy is boosted by 63 % for a low-cost FFNN using multi-taxel data. The proposed Spike-based SNR (SSNR) and Spike Time Error (STE) metrics for the taxel readout circuitry are shown to be good predictors of the accuracy.
00:39 CET		TOWARDS DEEP LEARNING-BASED OCCUPANCY DETECTION VIA WIFI SENSING IN UNCONSTRAINED ENVIRONMENTS Authors: Cristian Turetta¹, Geri Skenderi¹, Luigi Capogrosso¹, Florenc Demrozi², Philipp H. Kindt³, Alejandro Masrur⁴, Franco Fummi¹, Marco Cristani¹ and Graziano Pravadelli¹ ¹University of Verona, IT; ²Department of Electrical Engineering and Computer Science, University of Stavanger, NO; ³Lehrstuhl für Realzeit-Computersysteme (RCS), TU München (TUM), DE; ⁴TU Chemnitz, DE Abstract In the context of smart buildings and smart cities, the design of low-cost and privacy-aware solutions for recognizing the presence of humans and their activities is becoming of great interest. Existing solutions exploiting wearables and video-based systems have several drawbacks, such as high cost, low usability, poor portability, and privacy-related issues. Consequently, more ubiquitous and accessible solutions became the focus of attention, such as WiFi sensing. However, at the current state of the art, WiFi sensing is subject to low accuracy and poor generalization, primarily affected by environmental factors, such as humidity and temperature variations and furniture position changes. Such issues are partially solved at the cost of complex data preprocessing pipelines. In this paper, we present a highly accurate, resource- efficient occupancy detection solution based on deep learning, which is resilient to variations in humidity and temperature. The approach is tested on an extensive benchmark, where people are free to move and the furniture layout does change. In addition, based on a consolidated algorithm of explainable AI, we quantify the importance of the WiFi signal w.r.t. humidity and temperature for the proposed approach. Notably, humidity and temperature can indeed be predicted based on WiFi signals; this promotes the expressivity of the WiFi signal, and at the same time the need for a non-linear model to properly deal with it.
00:39 CET		CONTENT- AND LIGHTING-AWARE ADAPTIVE BRIGHTNESS SCALING FOR IMPROVED MOBILE USER EXPERIENCE Authors: Samuel Isuwa¹, David Amos², Amit Kumar Singh³, Bashir Al-Hashimi⁴ and Geoff Merrett¹ ¹University of Southampton, GB; ²University of Maiduguri, NG; ³University of Essex, GB; ⁴, Abstract Display subsystems have become the predominant user interface on mobile devices, serving as both input and output interfaces. For a better user experience, the display subsystem is expected to provide proper resolution and brightness despite its impact on battery life. Existing brightness scaling techniques set the display brightness statically (by the user) or dynamically (by the system) in response to predefined events such as low-battery or ambient light of the environment, which are independent of the displayed content. Techniques that consider the displayed content are either limited to video content or do not account for the user's expected battery life, thereby failing to maximise the user experience. This paper proposes CLABS: Content- and ambient Lighting-aware Adaptive Brightness Scaling in mobile devices that maximises user experience while meeting battery life expectations. The approach employs a content- and ambient lighting-aware profiler that learns and classifies each sample into predefined clusters at runtime by leveraging insights on user perceptions of content and ambient luminance variations. We maximise user experience through adaptive scaling of the display's brightness using an energy prediction model that determines appropriate brightness levels while meeting expected battery life. The evaluation of the proposed approach on a commercial smartphone improves Quality of Experience (QoE) by up to 24.5% compared to existing approaches.
00:39 CET		TOWARDS SMART CATTLE FARMS: AUTOMATED INSPECTION OF CATTLE HEALTH WITH REAL-LIFE DATA Authors: Yigit Tuncel¹, Toygun Basaklar¹, Mackenzie Smithyman², Vinicius Nunes de Gouvea³, Joao Dorea¹, Younghyun Kim⁴ and Umit Ogras¹ ¹University of Wisconsin - Madison, US; ²New Mexico State University, US; ³Texas A&M University, US; ⁴University of Wisconsin-Madison, US Abstract Cattle health problems, such as Bovine Respiratory Disease (BRD), constitute a significant source of economic loss for the agriculture industry. The current management practices to diagnose and select cattle for treatment is a widespread clinical scoring system called DART (Depression, Appetite, Respiration, and Temperature). DART requires significant manual human labor since animal evaluation is done individually. We propose a novel wearable accelerometer-based IoT system that predicts the DART scores to provide real-time animal health monitoring and hence, to reduce labor and costs associated with manual animal inspection and intervention. The proposed system first processes the accelerometer data to construct features that encode cattle's daily behavior. Then, it uses a lightweight decision-tree classifier to predict the DART score. We evaluate our approach on a dataset that consists of accelerometer data and veterinarian-approved DART scores for 54 animals. According to the results, the proposed system can classify healthy and sick animals with 78% accuracy. Furthermore, our approach outperforms 13 commonly used state-of-the-art time-series classifiers in terms of both accuracy and computational complexity. With 1 KB SRAM usage and less than 29 uJ energy consumption in a day, it enables an easily deployable IoT solution for smart farms.
00:39 CET		TIME SERIES-BASED DRIVING EVENT RECOGNITION FOR TWO WHEELERS Authors: Sai Usha Goparaju¹, Lakshmanan L², Abhinav Navnit², Rahul Biju¹, Lovish Bajaj³, Deepak Gangadharan² and Dr. Aftab Hussain⁴ ¹International Institute of Information and Technology, IN; ²International Institute of Information Technology, IN; ³Manipal Acadamy of Higher education, IN; ⁴IIIT Hyderabad, IN Abstract Classification of a motorcycle's driving events can provide deep insights to detect issues related to driver safety. Safety in two wheelers is a less studied problem, and we are attempting to address this gap by providing a learning based solution to classify driving events. Firstly, we developed a hardware system with 3-D accelerometer/gyroscope sensors that can be deployed on a motorcycle. The data obtained from these sensors is used to identify various driving events. We have investigated several machine learning (ML) models to classify driving events. However, in this process, we identified that though the overall accuracy of these traditional ML models is decent enough, the class-wise accuracy of these models is poor. Hence, we have developed time-series-based classification algorithms using LSTM and Bi-LSTM to classify various driving events. We have also embedded an attention mechanism in the architecture of these models for enhanced feature learning, thus improving the accuracy of event recognition. The experiments conducted have demonstrated that the proposed models have surpassed the state-of-the-art models in the context of driving event recognition with reasonable class-wise accuracies. We have also deployed these models on the edge devices like Raspberry pi and ESP32 and successfully reproduced the prediction accuracies in the devices. The experiments demonstrated that the proposed Bi-LSTM model showed a minimum of 87\% accuracy and a maximum of 99\% accuracy in class-wise prediction on a 2-wheeler driving dataset.

S_D1 System modeling, simulation, and validation

Date: Wednesday, 19 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		SPATIO-TEMPORAL MODELING FOR FLASH MEMORY CHANNELS USING CONDITIONAL GENERATIVE NETS Authors: Simeng Zheng, Chih-Hui Ho, Wenyu Peng and Paul Siegel, University of California, San Diego, US Abstract Modeling spatio-temporal read voltages with complex distortions arising from the write and read mechanisms in flash memory devices is essential for the design of signal processing and coding algorithms. In this work, we propose a data-driven approach to modeling NAND flash memory read voltages in both space and time using conditional generative networks. This generative flash modeling (GFM) method reconstructs read voltages from an individual memory cell based on the program levels of the cell and its surrounding cells, as well as the time stamp. We evaluate the model over a range of time stamps using the cell read voltage distributions, the cell level error rates, and the relative frequency of errors for patterns most susceptible to inter-cell interference (ICI) effects. Experimental results demonstrate that the model accurately captures the complex spatial and temporal features of the flash memory channel.
00:39 CET		EFFICIENT APPROXIMATION OF PERFORMANCE SPACES FOR ANALOG CIRCUITS VIA MULTI-OBJECTIVE OPTIMIZATION Authors: Benedikt Ohse¹, David Schreiber², Juergen Kampe¹ and Christopher Schneider¹ ¹Ernst-Abbe-Hochschule Jena, DE; ²University of Applied Sciences Jena, DE Abstract This paper presents an adaptation of the well-known normal boundary intersection (NBI) method for approximating complete feasible performance spaces of analog integrated circuits. Those spaces provide accurate information about all feasible combinations of competing performance parameters in a circuit. While the NBI-method is originally designed for computing the so-called Pareto front of a multi-objective optimization problem only, it can be adapted for approximating the complete performance space with some modifications. A scalarization into single-objective optimization problems is performed within our developed tool, which can be connected to any Spice-based simulator. Besides presenting the algorithm and its adaptations, the focus lies on investigating parallelization techniques and their effect on decreasing the computational time. Numerical experiments show the computed approximations of two- and three-dimensional performance spaces of several OTAs and compare the efficiencies of different parallelization schemes.
00:39 CET		MULTIDIMENSIONAL FEATURES HELPING PREDICT FAILURES IN PRODUCTION SSD-BASED CONSUMER STORAGE SYSTEMS Authors: Xinyan Zhang¹, Zhipeng Tan¹, Dan Feng¹, Qiang He¹, Ju Wan¹, Hao Jiang², Ji Zhang², Lihua Yang¹ and Wenjie Qi³ ¹Wuhan National Laboratory for Optoelectronics, Huazhong University of Science & Technology, CN; ²Huawei Technologies, CN; ³Wuhan National Laboratory for Optoelectronics, Huazhong University of Science & Technology Country/Region: China (CN), CN Abstract As SSD failures seriously lead to data loss and service interruption, proactive failure prediction is often used to improve system availability. However, the unidimensional SMART-based prediction models hardly predict all drive failures. Some other features applied in data centers and enterprise storage systems are not readily available in consumer storage systems (CSS). To further analyze related failures in production SSD-based CSS, we study nearly 2.3 million SSDs from 12 drive models based on a dataset of SMART logs, trouble tickets, and error logs. We discover that SMART, FirmwareVersion, WindowsEvent, and BlueScreenofDeath (SFWB) are closely related to SSD failures. We further propose a multidimensional-based failure prediction approach (MFPA), which is portable in algorithms, SSD vendors, and PC manufacturers. Experiments on the datasets show that MFPA achieves a high true positive rate (98.18%) and low false positive rate (0.56%), which is 4% higher and 86% lower than the SMART-based model. It is robust and can continuously predict for 2-3 months without iteration, substantially improving the system availability.
00:39 CET		PAR-GEM5: PARALLELIZING GEM5'S ATOMIC MODE Authors: Niko Zurstraßen¹, Jose Cubero-Cascante², Jan Moritz Joseph², Rainer Leupers², Xie Xinghua³ and Li Yichao³ ¹RWTH Aachen Institute for Communication Technologies and Embedded Systems, DE; ²RWTH Aachen University, DE; ³Huawei Technologies, CN Abstract While the complexity of MPSoCs continues to grow exponentially, their often sequential simulations could only benefit from a linear performance gain since the end of Dennard scaling. As a result, each new generation of MPSoCs requires ever longer simulation times. In this paper, we propose a solution to this problem: par-gem5 - the first universally parallelized version of the Full-System Simulator (FSS) gem5. It exploits the host system's multi-threading capabilities using a modified conservative, quantum-based Parallel Discrete Event Simulation. Compared to other parallel approaches, par-gem5 uses relaxed causality constraints, allowing temporal errors to occur. Yet, we show that the system's functionality is retained, and the inaccuracy of simulation statistics, such as simulation time or cache miss rate, can be kept within a single-digit percentage. Furthermore, we extend par-gem5 by a temporal error estimation that assesses the accuracy of a simulation without a sequential reference simulation. Our experiments reached speedups of 24.7x when simulating a 128-core ARM-based MPSoC on a 128-core host system.
00:39 CET		FAST BEHAVIOURAL RTL SIMULATION OF 10B TRANSISTOR SOC DESIGNS WITH METRO-MPI Authors: Guillem López-Paradís¹, Brian Li², Adrià Armejach³, Stefan Wallentowitz⁴, Miquel Moreto⁵ and Jonathan Balkind⁶ ¹Barcelona Supercomputing Center, ES; ²University of California, Santa Barbara, US; ³BSC & UPC, ES; ⁴Munich University of Applied Sciences, DE; ⁵BSC, ES; ⁶UC Santa Barbara, US Abstract Chips with tens of billions of transistors have become today's norm. These designs are straining our electronic design automation tools throughout the design process, requiring ever more computational resources. In many tools, parallelisation has improved both latency and throughput for the designer's benefit. However, tools largely remain restricted to a single machine and in the case of RTL simulation, we believe that this leaves much potential performance on the table. We introduce Metro-MPI to improve RTL simulation for modern 10 billion transistor-scale chips. Metro-MPI exploits the natural boundaries present in chip designs to partition RTL simulations and leverage High Performance Computing (HPC) techniques to extract parallelism. For chip designs that scale in size by exploiting latency-insensitive interfaces like networks- on-chip and AXI, Metro-MPI offers a new paradigm for RTL simulation scalability. Our implementation of Metro-MPI in Open- Piton+Ariane delivers 2.7 MIPS of RTL simulation throughput for the first time on a design with more than 10 billion transistors and 1,024 Linux-capable cores, opening new avenues for distributed RTL simulation of emerging system-on-chip designs. Compared to sequential and multi-threaded RTL simulations of smaller designs, Metro-MPI achieves up to 135.9× and 9.29× speedups. Similarly, for a representative regression run, Metro-MPI reduces energy consumption by up to 2.53× and 2.91×.
00:39 CET		DYNAMIC REFINEMENT OF HARDWARE ASSERTION CHECKERS Authors: Hasini Witharana, Sahan Sanjaya and Prabhat Mishra, University of Florida, US Abstract Post-silicon validation is a vital step in System-on-Chip (SoC) design cycle. A major challenge in post-silicon validation is the limited observability of internal signal states using trace buffers. Hardware assertions are promising to improve the observability during post-silicon debug. Unfortunately, we cannot synthesize thousands (or millions) of pre-silicon assertions as hardware checkers (coverage monitors) due to hardware overhead constraints. Prior efforts considered synthesis of a small set of checkers based on design constraints. However, these design constraints can change dynamically during the device lifetime due to changes in use-case scenarios as well as input variations. In this paper, we explore dynamic refinement of hardware checkers based on changing design constraints. Specifically, we propose a cost-based assertion selection framework that utilizes non-linear optimization as well as machine learning. Experimental results demonstrate that our machine learning model can accurately predict the area (less than 5% error) and power consumption (less than 3% error) of hardware checkers at runtime. This accurate prediction enables close-to-optimal dynamic refinement of checkers based on design constraints.
00:39 CET		STSEARCH: STATE TRACING-BASED SEARCH HEURISTICS FOR RTL VALIDATION Authors: Ziyue Zheng¹ and Yangdi Lyu² ¹Hong Kong University of Science and Technology (GuangZhou), CN; ²Hong Kong University of Science and Technology (Guangzhou), CN Abstract Branch coverage is important in the functional validation of Register-Transfer-Level (RTL) models. While random tests can cover the majority of easy-to-reach branches, there are still many hard-to-activate branches in today's industrial designs. These remaining corner branches are typically the source of bugs and hardware Trojans. Directed test generation approaches using formal methods effectively activate a specific branch but are limited by the state explosion problem. Semi-formal methods, such as concolic testing, improve the scalability by exploring one path at a time. This paper presents a novel concolic testing framework to exercise the corner branches through state tracing-based search heuristics (STSearch). The proposed approach heuristically generates and evaluates input sequences based on a novel heuristic indicator that evaluates the distance between the current state and the target branch condition. The heuristic indicator is designed to utilize both the static structural property of the design and the state from dynamic simulation. Compared to the existing concolic testing approaches, where a full new path is generated in each round by solving path constraints, the cycle-based heuristic search in the proposed approach is more effective and efficient. Experimental results show that our approach significantly outperforms the state-of-the-art approaches in both running time and memory usage.
00:39 CET		SYSTEM-LEVEL SIMULATOR OF EFLASH-BASED COMPUTE-IN-MEMORY ACCELERATORS FOR CONVOLUTIONAL NEURAL NETWORKS Authors: Jooho Wang, Sunwoo Kim, Junsu Heo and Chester Park, Department of Electrical and Electronics Engineering, Konkuk University, Seoul, South Korea, KR Abstract A new system-level simulator is proposed to estimate the bit-accurate and cycle-accurate performance of eFlash compute-in-memory (CIM) accelerators for convolutional neural networks. The proposed simulator can predict the inference accuracy by considering the impact of circuit nonideality such as program disturbance. Moreover, the simulator can also evaluate the system-level performance of dataflow strategies that have a significant impact on hardware area and performance of eFlash CIM accelerators. The simulator helps to find the optimal dataflow strategy of an eFlash CIM accelerator for each convolutional layer. It is shown that the improvement of area efficiency amounts to 26.8%, 21.2% and 17.9% in the case of LeNet-5, VGG-9 and ResNet-18, respectively.
00:39 CET		STRUCTURAL GENERATION OF VIRTUAL PROTOTYPES FOR SMART SENSOR DEVELOPMENT IN SYSTEMC-AMS FROM SIMULINK MODELS Authors: Alexandra Kuester¹, Rainer Dorsch¹ and Christian Haubelt² ¹Bosch Sensortec GmbH, DE; ²University of Rostock, DE Abstract We present a flow to reuse system-level analog/mixed-signal (AMS) models developed in MATLAB/Simulink for the extension of virtual prototypes in SystemC. To prevent time-consuming co-simulation, our flow translates the Simulink model into an equivalent SystemC-AMS model. Translation is supported either by wrapping code generated by MATLAB's Embedded Coder or by instantiating previously generated models. Thus, a one-to-one mapping of the model's hierarchy is possible which allows deep insights into the architecture and good traceability. The conducted case study on an accelerometer model shows the applicability of our approach. The generated hierarchical model is half as fast as a monolithic version but allows better observability and traceability of the system. It is tens of times faster than simulation in Simulink, thus especially faster than co-simulation. The extended virtual prototype aims to support software engineers during development and validation of firmware in smart sensors.
00:39 CET		A HARDWARE-SOFTWARE COOPERATIVE INTERVAL-REPLAYING FOR FPGA-BASED ARCHITECTURE EVALUATION Authors: Hongwei Cui, Shuhao Liang, Yujie Cui, Weiqi Zhang, Honglan Zhan, Chun Yang, Xianhua Liu and Xu Cheng, The School of Computer Science, Peking University, CN Abstract Compared with the traditional software simulator, the hardware implementation can demonstrate the precise behavior of the microarchitecture and verify the feasibility of the new microarchitecture design accurately. FPGA can provide more real and accurate results, but resource limitation of FPGA boards still hinders researchers. First of all, the low frequency of FPGA leads to a long time for running large benchmarks. Secondly, the hardware resources of the FPGA (such as physical memory) cannot support the execution of some special benchmarks. In addition, researchers need to run a complete benchmark in a real operating system, which also brings great difficulties. This paper proposes a hardware-software cooperative solution for the general checkpoint scheme, which allows researchers to run the specified program interval correctly and independently in the hardware running environment. It uses the processor simulator to collect runtime information of programs and create checkpoints for arbitrary intervals. Furthermore, it provides an extensible and portable checkpoint loader to read checkpoints and re-execute program intervals. In order to select the key program intervals for checkpoint creation, this paper extends RISC-V ISA and proposes an event-based sampling design. This design enables researchers to find hot program intervals with more representative microarchitecture characteristics. Using checkpoints in hot regions, researchers can quickly verify the effectiveness of microarchitecture design on FPGA and alleviate the speed bottleneck of FPGA. In addition, this novel solution can support running intervals of some special programs that cannot be executed on the FPGA. The event-based sampling design is implemented in the BOOM processor, and the SPEC CPU2006 benchmarks are sampled. In addition, checkpoints are generated for the benchmarks, and the correctness and effectiveness of the checkpoint scheme are evaluated on the FPGA board. The experimental results show that the scheme is effective.
00:39 CET		FELOPI: A FRAMEWORK FOR SIMULATION AND EVALUATION OF POST-LAYOUT FILE AGAINST OPTICAL PROBING Authors: Sajjad Parvin¹, Mehran Goli¹, Frank Sill Torres² and Rolf Drechsler³ ¹University of Bremen, DE; ²German Aerospace Center, DE; ³University of Bremen/DFKI, DE Abstract In recent years, it has been shown that laser based side-channel analysis methods, specifically Optical Probing (OP) rose security concern against mission-critical application circuits. In reality, designing a robust circuit against OP can be time consuming because the chip needs to be designed, fabricated, and tested to see how robust it is against OP. To mitigate this problem, we propose a framework namely FELOPi, which takes the layout file format of a design as an input and then performs OP on the design in simulation. In a real scenario, i.e. OP attack on a chip to readout the data requires lots of time, however using our framework we can reduce the OP time to seconds rather than hours to days in simulation.
00:39 CET		QUO VADIS SIGNAL? AUTOMATED DIRECTIONALITY EXTRACTION FOR POST-PROGRAMMING VERIFICATION OF A TRANSISTOR-LEVEL PROGRAMMABLE FABRIC Authors: Apurva Jain, Thomas Broadfoot, Yiorgos Makris and Carl Sechen, University of Texas at Dallas, US Abstract We discuss the challenges related with developing a post-programming verification solution for a TRAnsistor-level Programmable fabric (TRAP). Toward achieving high density, the TRAP architecture employs bidirectionally-operated pass transistors in the implementation of its logic and interconnect networks. While it is possible to model such transistors through appropriate primitives of hardware description languages (HDL) to enable simulation-based validation, Logic Equivalence Checking (LEC) methods and tools do not support such primitives. As a result, formally verifying the functionality programmed by a given bit-stream on TRAP is not innately possible. To address this limitation, we introduce a method for automatically determining the signal flow direction through bidirectional pass transistors for a given bit-stream and subsequently converting the HDL describing the programmed fabric to consist only of unidirectional transistors. Thereby, commercial EDA tools can be used to check logic equivalence between the transistor-level HDL describing the programmed fabric and the post-synthesis gate-level netlist. The proposed method has been successfully applied to verify various benchmark circuits programmed on the TRAP fabric.

S_D8 Future memories

Date: Wednesday, 19 April 2023
Time: 11:00 - 12:30 CET

Time	Label	Presentation Title Authors
00:39 CET		OVERLAPIM: OVERLAP OPTIMIZATION FOR PROCESSING IN-MEMORY NEURAL NETWORK ACCELERATION Authors: Minxuan Zhou¹, Xuan Wang² and Tajana Rosing¹ ¹UCSD, US; ²University of California San Diego, US Abstract Processing in-memory (PIM) can accelerate neural networks (NNs) for its extensive parallelism and data movement minimization. The performance of NN acceleration on PIM heavily depends on software-to-hardware mapping, which indicates the order and distribution of operations across the hardware resources. Previous works optimize the mapping problem by exploring the design space of per-layer and cross-layer data layout, achieving speedup over manually designed mappings. However, previous works do not consider computation overlapping across consecutive layers. By overlapping computation, we can process a layer before its preceding layer fully completes, decreasing the execution latency of the whole network. The mapping optimization without overlap analysis can result in sub-optimal performance. In this work, we propose OverlaPIM, a new framework that integrates the overlap analysis with the DNN mapping optimization on PIM architectures. OverlaPIM adopts several techniques to enable efficient overlap analysis and optimization for the whole network mapping on PIM architectures. We test OverlaPIM on popular DNN networks and compare the results to nonoverlap optimization. Our experiments show that OverlaPIM can efficiently produce mappings that are 2.10× to 4.11× faster than the state-of-the-art mapping optimization framework.
00:39 CET		TAM: A COMPUTING IN MEMORY BASED ON TANDEM ARRAY WITHIN STT-MRAM FOR ENERGY-EFFICIENT ANALOG MAC OPERATION Authors: Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao and Yue Zhang, Beihang University, CN Abstract Computing in memory (CIM) has been demonstrated promising for energy efficient computing. However, the dramatic growth of the data scale in neural network processors has aroused a demand for CIM architecture of higher bit density, for which the spin transfer torque magnetic RAM (STT-MRAM) with high bit density and performance arises as an up-and-coming candidate solution. In this work, we propose an analog CIM scheme based on tandem array within STT-MRAM (TAM) to further improve energy efficiency while achieving high bit density. First, the resistance summation based analog MAC operation minimizes the effect of low tunnel magnetoresistance (TMR) by the serial magnetic tunnel junctions (MTJs) structure in the proposed tandem array with smaller area overhead. Moreover, a read scheme of resistive-to-binary is designed to achieve the MAC results accurately and reliably. Besides, the data-dependent error caused by MTJs in series has been eliminated with a proposed dynamic selection circuit. Simulation results of a 2Kb TAM architecture show 113.2 TOPS/W and 63.7 TOPS/W for 4-bit and 8-bit input/weight precision, respectively, and reduction by 39.3% for bit-cell area compared with existing array of MTJs in series.
00:39 CET		OUT-OF-CHANNEL DATA PLACEMENT FOR BALANCING WEAR-OUT AND I/O WORKLOADS IN RAID-ENABLED SSDS Authors: Yang Fan, Xiao qi, Li Jun, Sha bing, Cai gang and Liao wei, Southwest university, CN Abstract Channel-level RAID implementation SSDs can fight against channel failures inside SSDs, but greatly suffer from imbalanced wear-out (i.e. erase) and I/O workloads across all SSD channels, due to the nature of in-channel updates on data/parity chunks of data stripes. This paper proposes exchanging channel locations of data/parity chunks belonging to the same stripe when satisfying update (write) requests, termed as out-of-channel data placement. Consequently, it can smooth wear-out and I/O workloads across SSD channels, thus reducing I/O response time. Through a series of emulation experiments on several realistic disk traces, we show that our proposal can greatly improve I/O performance, as well as noticeably balance the wear-out and I/O workloads, in contrast to related methods.
00:39 CET		AGDM：AN ADAPTIVE GRANULARITY DATA MIGRATION STRATEGY FOR HYBRID MEMORY SYSTEMS Authors: Zhouxuan Peng, Dan Feng, Jianxi Chen, Jing Hu and Chuang Huang, Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, MOE, Huazhong University of Science and Technology, Hubei, China, CN Abstract Hybrid memory systems show strong potential to satisfy the growing memory demands of modern applications by combining different memory technologies. Due to the different performance characteristics of hybrid memories, a data migration strategy that migrates hot data to a faster memory is critical to the overall performance. Prior works have focused on identifying hot data and migration decisions. However, we find that the fix-sized global migration granularity in existing data migration schemes results in suboptimal performance on most workloads. The key observation is that the optimal migration granularity varies with access patterns. This paper proposes AGDM, an access-pattern-aware Adaptive Granularity Data Migration strategy for hybrid memory systems. AGDM tracks memory access patterns in runtime and accordingly adopts the most appropriate migration mode and granularity. The novel remapping-migration decoupled metadata organization enables AGDM to set local optimal granularities for memory regions with different access patterns. Our evaluation shows that, compared to the state-of-the-art scheme, AGDM gets an average performance improvement of 20.06% with 29.98% energy savings.
00:39 CET		P-PIM: A PARALLEL PROCESSING-IN-DRAM FRAMEWORK ENABLING ROWHAMMER PROTECTION Authors: Ranyang Zhou¹, Sepehr Tabrizchi², Mehrdad Morsali¹, Arman Roohi³ and Shaahin Angizi¹ ¹New Jersey Institute of Technology, US; ²University of Nebraska–Lincoln (UNL), US; ³University of Nebraska - Lincoln, US Abstract In this work, we propose a Parallel Processing-In-DRAM architecture named P-PIM leveraging the high density of DRAM to enable fast and flexible computation. P-PIM enables bulk bit-wise in-DRAM logic between operands in the same bit-line by elevating the analog operation of the memory sub-array based on a novel dual-row activation mechanism. With this, P-PIM can opportunistically perform a complete and inexpensive in-DRAM RowHammer (RH) self-tracking and mitigation technique to protect the memory unit against such a challenging security vulnerability. Our results show that P-PIM achieves ~72% higher energy efficiency than the fastest charge-sharing-based designs. As for the RH protection, with a worst-case slowdown of ~0.8%, P-PIM archives up to 71% energy-saving over the SRAM/CAM-based frameworks and about 90% saving over DRAM-based frameworks.
00:39 CET		PRIVE: EFFICIENT RRAM PROGRAMMING WITH CHIP VERIFICATION FOR RRAM-BASED IN-MEMORY COMPUTING ACCELERATION Authors: Wangxin He¹, Jian Meng¹, Sujan Gonugondla², Shimeng Yu³, Naresh Shanbhag⁴ and Jae-sun Seo¹ ¹Arizona State University, US; ²Amazon, US; ³Georgia Institute of Technology, US; ⁴University of Illinois Urbana-Champaign, US Abstract As deep neural networks (DNNs) have been successfully developed in many applications with continuously increasing complexity, the number of weights in DNNs surges, leading to consistent demands for denser memories than SRAMs. RRAM-based in-memory computing (IMC) achieves high density and energy-efficiency for DNN inference, but RRAM programming remains to be a bottleneck due to high write latency and energy consumption. In this work, we present the Progressive-wRite In-memory program-VErify (PRIVE) scheme, which we verify with an RRAM testchip for IMC-based hardware acceleration for DNNs. We optimize the progressive write operations on different bit positions of RRAM weights to enable error compensation and reduce programming latency/energy, while achieving high DNN accuracy. For 5-bit precision DNNs, PRIVE reduces the RRAM programming energy by 1.82X, while maintaining high accuracy of 91.91% (VGG-7) and 71.47% (ResNet-18) on CIFAR-10 and CIFAR-100 datasets, respectively.
00:39 CET		END-TO-END DNN INFERENCE ON A MASSIVELY PARALLEL IN-MEMORY COMPUTING ARCHITECTURE Authors: Nazareno Bruschi¹, Giuseppe Tagliavini¹, Angelo Garofalo¹, Francesco Conti¹, Irem Boybat², Luca Benini³ and Davide Rossi⁴ ¹University of Bologna, IT; ²IBM Research Europe - Zurich, CH; ³Università di Bologna and ETH Zurich, IT; ⁴University Of Bologna, IT Abstract The demand for computation resources and energy efficiency of Convolutional Neural Networks (CNN) applications requires a new paradigm to overcome the "Memory Wall”. Analog In-Memory Computing (AIMC) is a promising paradigm since it performs matrix-vector multiplications, the critical kernel of many ML applications, in-place in the analog domain within memory arrays structured as crossbars of memory cells. However, several factors limit the full exploitation of this technology, including the physical fabrication of the crossbar devices, which constrain the memory capacity of a single array. Multi-AIMC architectures have been proposed to overcome this limitation, but they have been demonstrated only for tiny and custom CNNs or performing some layers off-chip. In this work, we present the full inference of an end-to-end ResNet-18 DNN on a 512-cluster heterogeneous architecture coupling a mix of AIMC cores and digital RISC-V cores, achieving up to 20.2 TOPS. Moreover, we analyze the mapping of the network on the available non-volatile cells, compare it with state-of-the-art models, and derive guidelines for next-generation many-core architectures based on AIMC devices.
00:39 CET		UHS: AN ULTRA-FAST HYBRID STORAGE CONSOLIDATING NVM AND SSD IN PARALLEL Authors: Qingsong Zhu, Qiang Cao and Jie Yao, Huazhong University of Science and Technology, CN Abstract Non-Volatile Memory (NVM) with persistent and near-DRAM performance has been commonly used as first-level fast storage atop Solid-State Drives (SSDs) and Hard Disk Drives (HDDs), constituting classic hierarchy architecture with high cost-performance. However, the NVM/SSD tiered storage overuses primary NVM with limited actual performance and under-utilizes secondary SSD with increasing bandwidth. Besides, NVM and SSD exhibit distinguished I/O characteristics, but are complementary in I/O pattern. It motivate us to design a superior hybrid storage to fully exploit NVM and SSD simultaneously. In this paper, we propose UHS, an Ultra-fast Hybrid Storage consolidating NVM and SSD to reap their own merits with key enabled techniques. First, UHS builds a uniform yet heterogenous block-level storage view for the upper applications, e.g., file systems or key-value stores. UHS provides static address-mapping to explicitly partition the global block-space into coarse-grain NVM-zones and SSD-zones, which mainly serve the metadata and file data respectively. Second, UHS proposes a fine-grain request-level NVM buffer to dynamically absorb small file-writes in runtime and then migrates them to the SSDs in the background. Third, UHS designs I/O-affinity write allocation and hash-based buffer indexing to trade off write gain and read cost of the NVM-buffer. Finally, UHS designs a multi-thread I/O model to take full advantage of parallelism in both NVM and SSD. We implement UHS and evaluate it under a variety of workloads. The experiments show that UHS outperforms SSD, NVM, Bcache-writeback (representative hierarchy storage), and Device-Mapper (state-of-the-art hybrid storage) up to 8X, 1.5X, 3.5X, and 6X respectively.
00:39 CET		BRANCH PREDICTOR DESIGN FOR AMBIENT ENERGY HARVESTING NONVOLATILE PROCESSORS Authors: Mengying Zhao, Shuo Xu, Hao Zhang, Huichuan Zheng and Xiaojun Cai, Shandong University, CN Abstract Non-volatile processors are proposed for ambient energy harvesting systems to enable accumulative computing across power failures. They employ nonvolatile memory for processor status backup before power outage and resume the system after power recovers. A straightforward backup policy is to back up all volatile data in processors, but it induces high backup cost. In this paper, we focus on branch predictor, an important component in processor, and propose efficient backup schemes to reduce backup cost while maintaining its prediction ability. We first analyze the modules in branch predictor, and accordingly propose two backup mechanisms pertaining to saturation-guided and locality-guided backup. Evaluation shows that, when compared with no-backup and all-backup strategy, the proposed design achieves 12.8% and 52.5% energy reduction, respectively.
00:39 CET		OPTIMIZING DATA MIGRATION FOR GARBAGE COLLECTION IN ZNS SSDS Authors: Zhenhua Tan¹, Linbo Long², Renping Liu³, Congming Gao⁴, Yi Jiang³ and Yan Liu³ ¹College of Computer Science and Technology of Chongqing University of Posts and Telecommunications, CN; ²College of Computer Science and Technology, Chongqing University of Posts and Telecommunications, CN; ³Chongqing University of Posts and Telecommunications, CN; ⁴Xiamen University, CN Abstract The NVMe Zoned Namespace (ZNS) is proposed as a high-performance interface for solid-state drives (SSDs), where the logical address space is divided into fixed-size and sequential-write (flash-friendly) zones. ZNS SSDs shift the responsibility of garbage collection (GC) to the host. However, data migration in GC needs to move data to the host's buffer first and write back to the new location, resulting in an unnecessary end-to-end transfer overhead during GC. Moreover, due to the pre-configured mapping between zones and blocks, GC needs to perform a large number of unnecessary block-to-block data migrations between zones. To address these issues, this paper proposes a dynamic zone mapping ZNS SSD design, termed Brick-ZNS, with in-storage data migration and address remapping. First, a new ZNS command, Zone_MD, is designed to realize in-storage data migration to avoid the end-to-end transfer overhead of GC. Second, a remapping strategy based on parallel physical blocks is proposed to reduce the amount of block-to-block data migrations between zones while ensuring zone parallelism. Based on a full-stack SSD emulator, our evaluation shows that Brick-ZNS reduces GC latency by 6.78× and improves SSD lifetime by 1.17× on average.
00:39 CET		ENASA: TOWARDS EDGE NEURAL ARCHITECTURE SEARCH BASED ON CIM ACCELERATION Authors: Shixin Zhao¹, Songyun Qu², Ying Wang³ and yinhe han⁴ ¹University of Chinese Academy of Sciences. Institute of Computing Technology, Chinese Academy of Sciences, CN; ²University Of Chinese Academy of Sciences, Institute Of Computing Technology Chinese Academy Of Sciences, CN; ³State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, CN; ⁴Institute of Computing Technology,Chinese Academy of Sciences, CN Abstract One-shot Neural Architecture Search (NAS) has achieved remarkable improvement over human-designed neural network architecture in accuracy and hardware-oriented metrics such as power and latency. However, one-shot NAS requires hundreds of GPU hours to complete the search process and its tedious search time hinders the extensive application of one-shot NAS to the use cases that need quickly adapt or customize the network architecture for the deployment situations via NAS. In this work, we combine the Computing-in-Memory (CIM) and NAS technology, and propose a ReRAM-based accelerator, ENASA, so that NAS can be applied to various edge devices for them to customize the most suitable individual network architecture. However, the one-shot NAS process must repetitively evaluate the sampled sub-network within a large-scale supernet before converging to the best sub-network architecture. Thereby, how to map this iterative network inference task onto the CIM arrays makes a big difference in the performance and power overhead. To realize efficient in-memory supernet sampling and evaluation, we design a novel mapping method that tactically executes a group of sub-nets in the CIM arrays, not only to boost the sub-net concurrency but also to eliminate the repetitive operations shared by these subnets. Meanwhile, to further enhance the subnet-level operation concurrency and sharing in the CIM arrays, we proposed a novel CIM-friendly one-shot NAS algorithm that purposely samples those operation-sharing subnets in each iteration while still maintaining the convergence performance of NAS. According to the experiment results, our CIM NAS accelerator achieves an improvement of 196.6× and 1200× in performance speedup and energy saving, respectively, compared to the CPU+GPU baseline.