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The time zone for all times mentioned at the DATE website is CET – Central Europe Time (UTC+1). AoE = Anywhere on Earth.

ET02 Embedded Tutorial: On-Device Continual Learning Meets Ultra-Low Power Processing

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Date: Monday, 25 March 2024
Time: 11:00 CET - 12:30 CET
Location / Room: Break-Out Room S3+4

This tutorial provides an overview of the recent On-Device Learning (ODL) topic for ultra-low power extreme edge devices, such as MicroController compute units (MCU).

Nowadays, these devices are capable of running Deep Neural Network (DNN) inference tasks to extract high-level information from data captured by on-board sensors. The DNN algorithms are typically trained off-device using high-performance servers and, then, frozen and deployed on resource-constrained MCU-powered platforms. However, the data used for the DNN training may not be representative of the deployment environment, causing mispredictions/misclasifications that eventually reflect into (i) expensive model redesigns and (ii) re-deployments at scale. Recently proposed Continual Learning methods stand out as potential solutions to this fundamental issue, enabling DNN model personalization by incorporating new knowledge (e.g. new class, new domains, or both) given the new data retrieved for the target environment. However, the DNN learning task has been normally considered out-of-scope for highly resource-constrained devices because of the high memory and computation requirements, limiting its application to server machines where, thanks to the potentially unlimited resources, custom DNN models can be retrained from scratch as soon as new data becomes available.

This tutorial focuses on the application of the Continual Learning (CL) paradigm on MCUs devices, to enable small sensor nodes to adapt their DNN models in-the-field, without relying on external computing resources. After providing a brief taxonomy of the main CL algorithms and scenarios, we will review the fundamental ODL operations, referring to the backpropagation learning algorithm. We will analyze the memory and computational costs of the learning process when targeting a multi-core RISC-V-based MCU, derived from the PULP-project template, and we will use a case study to see how these costs constrain an on-device learning application. Next, a hands-on session will bring the audience to familiarize with software optimizations for DNN learning primitives using PULP-TrainLib (, the first software library for DNN training on RISC-V multicore MCU-class devices. Finally, we will conclude by reviewing the main ODL challenges and limitations and describing the latest major results in this field.


  • Dr. Manuele Rusci, post-doc KU Leuven
  • Cristian Cioflan, PhD student ETH Zurich
  • Davide Nadalini, PhD student UNIBO and POLITO

Tutorial Learning Objectives:

  • A brief taxonomy of Continual Learning scenarios, metrics and benchmarks.
  • Basic operations and building blocks of On-Device Learning.
  • Analysis of memory and computation costs for ODL on MCU-class devices.
  • Software optimization hands-on for ODL on a multi-core RISC-V platform.
  • Present main research directions and challenges for ODL on ultra-low power MCUs.

Target Audience

This tutorial targets researchers and practitioners interested in new hardware & software solutions for On-Device Learning on low-end devices, such as MCUs. Participants should be familiar with concepts of Deep Neural Networks (main building blocks, inference vs training) and basic C programming for Microcontrollers.

Hands-on & Material

The hands-on will demonstrate the open-source PULP-TrainLib software library (, the state-of-the-art software package for MCU class devices, to provide a concrete embodiment of the ODL concepts and explain the application of software optimization to the learning routines, i.e. parallelization, low-precision (half-precision floating point), loop unrolling, and vectorization. The speaker will show the main library features using reference code examples. To this aim, we will adopt the open-source PULP platform simulator ( and encourage the audience to practice with the PULP-TrainLib ODL framework during the session. We will collect all the materials and installation instructions on a dedicated Github repository, which will be made available to the audience in advance and after the tutorial.

Detailed Program

Part I: M. Rusci (KUL). On-Device Continual Learning: motivation and intro. (10’)

  • Tutorial Intro
  • Limitation of DNN inference on MCUs
  • Continual Learning scenarios and Metrics
  • Dealing with Catastrophic forgetting

Part II: C. Cioflan (ETHZ). On-device Adaptation on a multi-core MCU device (25’ + 5’ Q&A)

  • Revisiting ODL basic operations
  • Reviewing DNN learning from an embedded system perspective: computation and memory
  • Learning on the PULP platform
  • Case study: On-Device noise adaptation for keyword spotting

Part III: D. Nadalini (UNIBO). Hands-on On-Device Learning on MCUs: Pulp-TrainLib. (25’ + 5’ Q&A)

  • PULP-TrainLib Overview, Operator Definitions and Learning deployment
  • Code Optimizations: parallelization, low-precision and vectorization

Part IV: M. Rusci (KUL). Challenges and Research Directions for On-Device Continual Learning – 15’ + 5’ Q&A

  • ODL software frameworks for MCUs
  • Memory-efficient learning and architectures
  • Data efficient learning
  • Open Problems

Final Q&A

W03 Workshop: Workshop on Nano Security: From Nano-Electronics to Secure Systems

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Date: Monday, 25 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Break-Out Room S6+7


Ilia Polian, University of Stuttgart, Germany

Nan Du, Friedrich Schiller University Jena, Germany, Germany

Shahar Kvatinsky, Technion – Israel Institute of Technology, Israel

Ingrid Verbauwhede, KU Leuven, Belgium

URL: Workshop website at the University of Stuttgart

Today’s societies critically depend on electronic systems. Security of such systems are facing completely new challenges due to the ongoing transition to radically new types of nano-electronic devices, such as memristors, spintronics, or carbon nanotubes. The use of such emerging nano-technologies is inevitable to address the essential needs related to energy efficiency, computing power and performance. Therefore, the entire industry are switching to emerging nano-electronics alongside scaled CMOS technologies in heterogeneous integrated systems. These technologies come with new properties and also facilitate the development of radically different computer architectures.

The second edition of the NanoSec workshop will bring together researchers from hardware-oriented security and from emerging hardware technology. It will explore the potential of new technologies and architectures to provide new opportunities for achieving security targets, but it will also raise questions about their vulnerabilities to new types of hardware-oriented attacks. The workshop is based on a Priority Program funded since 2019 by the German DFG, and will be open to members and non-members of that Priority Program alike.


Mon, 14:00 - 14:45

Session chair

Michael Hutter, PQShield, Vienna, Austria

The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security

Lilas Alrahis, NYU Abu Dhabi

Session 1: Secure Architectures

Mon, 14:45 - 15:15

Session chair

Giorgio Di Natale, TIMA, France

Okapi: A Lightweight Architecture for Secure Speculation Exploiting Locality of Memory Accesses

Philipp Schmitz1, Tobias Jauch1, Alex Wezel1, Mohammad R. Fadiheh2, Thore Tiemann3, Jonah Heller3, Thomas Eisenbarth3, Dominik Stoffel1, Wolfgang Kunz1

1RPTU Kaiserslautern-Landau, 2Stanford U, 3U Lübeck

Neuromorphic and In-Memory Computing Based on Memristive Circuits for Predictive Maintenance and Supply-Chain Management and Security

Nikolaos Athanasios Anagnostopoulos, Nico Mexis, Stefan Katzenbeisser, Elif Bilge Kavun, Tolga Arul, U Passau

Poster session: Projects of Priority Program Nano Security

Mon, 15:15 - 16:00


Ilia Polian, University of Stuttgart, Germany

OnE-Secure: Securing State-of-the-Art Chips Against High-Resolution Contactless Optical and Electron-Beam Probing Attacks

Sebastian Brand (FhG IMWS), Rolf Drechsler (U Bremen), Jean-Pierre Seifert TU Berlin), Frank Sill Torres (DLR)

STAMPS-PLUS: Exploration of an integrated Strain-based TAMPer Sensor for Puf and trng concepts with best-in-class Leakage resilience and robUStness

Ralf Brederlow (TU Munich), Matthias Hiller (FhG AISEC), Michael Pehl (TU Munich)

RAINCOAT: Randomization in Secure Nano-Scale Microarchitectures 2

Lucas Davi (U Duisburg-Essen), Tim Güneysu (RU Bochum)

EMBOSOM: Embedded Software Security into Modern Emerging Hardware Paradigms

Rolf Drechsler (U Bremen), Tim Güneysu (RU Bochum)

MemCrypto: Towards Secure Electroforming-free Memristive Cryptographic Implementations

Nan Du (FSU Jena), Ilia Polian (U Stuttgart)

HaSPro: Verifiable Hardware Security for Out-of-Order Processors

Thomas Eisenbarth (U Lübeck), Wolfgang Kunz (TU Kaiserslautern)

NanoSec2: Nanomaterial-based platform electronics for PUF circuits with extended entropy sources

Sascha Herrmann (TU Chemnitz), Stefan Kat-zenbeisser (U Passau), Elif Kavun (U Passau)

SecuReFET: Secure Circuits through Inherent Reconfigurable FET

Akash Kumar (TU Dresden), Thomas Mikolajick (NaMLab GmbH)

SSIMA: Scalable Side-Channel Immune Micro-Architecture

Amir Moradi (TU Darmstadt)

SeMSiNN: Secure Mixed-SIgnal Neural Networks

Maurits Ortmanns (U Ulm), Ilia Polian (U Stuttgart)

Session 2: Physical Aspects of Secure Computing in the Nano Regime

Mon, 16:30 - 17:15

Session chair

Francesco Regazzoni, University of Amsterdam, NL and Università della Svizzera italiana, Switzerland

Hardware Trojan Detection Using Optical Probing

Sajjad Parvin1, Frank Sill Torres2, Rolf Drechsler1, 1U Bremen, 2DLR Bremen

A Cautionary Note about Bit Flips in ReRAM

Felix Staudigl1, Jan Philipp Thoma2, Christian Niesler3, Karl J. X. Sturm1, Rebecca Pelke1, Dominik Sisejkovic1, Jan Moritz Joseph1, Tim Güneysu2, Lucas Davi3, Rainer Leupers1

1RWTH Aachen, 2RU Bochum, 3U Duisburg Essen

An Analysis of the Effects of Temperature on the Performance of ReRAM-Based TRNGs

Nico Mexis, Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser, Tolga Arul, U Passau

Session 3: Emerging Technologies for Security

Mon, 17:15 - 18:00

Session chair

Haralampos-G. Stratigopoulos, Sorbonne Universités, CNRS, LIP6, France

A Guide to Assessing Emerging Reconfigurable Nanotechnologies for Robust IP Protection

Armin Darjani, Nima Kavand, Akash Kumar, TU Dresden

Fingerprinting and Identification of Hall Sensors

Christoph Frisch1, Tobias Chlan1, Carl Riehm1, Markus Sand2, Markus Stahl-Offergeld3, Michael Pehl1, Ralf Brederlow1,3

1TU Munich, 2LZE GmbH, 3Fraunhofer Institute for Integrated Circuits IIS

Memristors in the Context of Security and AI

Alexander Tekles, Tolga Arul, Nico Mexis, Stefan Katzenbeisser, Nikolaos Athanasios Anagnostopoulos, U Passau

W04 Workshop: 4th Workshop on Open-Source Design Automation (OSDA 2024)

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Date: Monday, 25 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Multi-Purpose Room M1B+D

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

ET03 Embedded Tutorial: Coarse-Grained Reconfigurable Arrays: Modelling and Exploration Using the Open-Source CGRA-ME Framework

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Date: Tuesday, 26 March 2024
Time: 08:30 CET - 10:00 CET
Location / Room: Break-Out Room S3+4

Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware devices within the broader umbrella of reconfigurable architectures. They are promising candidates for the realization of application accelerators. In contrast to FPGAs, CGRAs are configurable at the word level, rather than the bit level. This distinction positions CGRAs to deliver power, performance, and area characteristics more closely aligned with custom ASICs. Notably, the emergence of numerous machine-learning accelerator startups, such as Tenstorrent, Groq, Cerebras, and SambaNova, offer architectures that closely resemble CGRAs.

CGRA-ME is an open-source CGRA modeling and exploration framework actively being developed at the University of Toronto. CGRA-ME is intended to facilitate research on new CGRA architectures and new CAD algorithms. Given the current surge in research interest in CGRAs from both industry and academia, this tutorial aims to provide valuable insights and practical guidance in this dynamic field.


  • Dr. Jason Anderson, Professor, University of Toronto, Toronto, Canada
  • Dr. Boma Adhi, Researcher, RIKEN Center for Computational Science, Kobe, Japan
  • Omar Ragheb, Ph.D. Candidate, University of Toronto, Toronto, Canada
  • Stephen Wicklund, MASc. Candidate, University of Toronto, Toronto, Canada

Target Audience

We invite DATE 2024 participants with a keen interest in reconfigurable architectures and computer-aided design (CAD) tools. Please join us!

Learning objectives

  • A brief history of coarse-grained reconfigurable arrays (CGRAs).
  • An introduction to the CGRA-ME framework.
  • Details of the building blocks of the tool.
  • Description of the CAD algorithms utilized.
  • Learning how CGRA architectures are defined.
  • Hands-on experimentation using CGRA-ME.
  • Motivate future research within the CGRA-ME framework.

Required background

  • Familiarity with C++ and Linux.
  • A keen interest in learning about CGRA architectures and CAD, or application acceleration using CGRAs.
  • Desirable: prior knowledge of reconfigurable hardware and associated design methodologies.

Detailed Program

  • Part 1: Lecture (45 mins)
  • Part 2: Hands-on session (45 mins)

W02 Workshop: 3D Integration: Heterogeneous 3D Architectures and Sensors

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Date: Tuesday, 26 March 2024
Time: 08:30 CET - 12:30 CET
Location / Room: Break-Out Room S6+7


Pascal Vivet, CEA-LIST, France

Workshop Description

3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.

Technical Program

Subject to final changes

  • 8:30 - 8:35 : Workshop Introduction, Pascal Vivet, CEA-List, FR
  • 8:35 - 9:00 : Keynote
    • “Enabling a Chiplet Ecosystem”, Tony Mastroianni, SIEMENS EDA, USA
  • 9:00 - 10:00 : Session 1 : Chiplet architecture and AI acceleration
    • "Occamy - A 432-Core Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support", Gianna Paulin, ETH-Z, CH (*now in AXELERA)
    • “Chiplets for future automotive application”, Andy Heinig, Fraunhofer, Dresden, DE
    • “Silicon Photonic Network-on-Interposer Design for Energy Efficient Convolutional Neural Network Acceleration on 2.5D Chiplet Platforms”, Sudeep Pasricha, Colorado State Univ, USA
    • “Multiple-Stacked-Wafer (MSW) technology : the appropriate technology for ultra-low power Smart Sensor”, Sébastien Thuriès, CEA-List and IRT-Nanoelec, FR
  • 10:00 - 11:00 : Coffee Break
  • 11:00 - 12:30 : Session 2 : Advanced Architectures and Thermal management
    • “Foundry Monolithic 3D Logic+Memory Stack unlocks Large IC Architectural Benefits”, Tathagata Srimani, Carnegie Mellon Univ., USA
    • “3D Evolution in Nanosheet: A Glance on General Purpose AI, Dense-XR and Edge computing”, Sudipta Das, IMEC, BE
    • “Machine Learning for Thermal Modeling of 3D Integrated Circuits”, Yuanqing Cheng, Beihang University, China
    • “Thermal Management for 3D-Stacked Processors”, Anuj Pathania, University of Amsterdam, NL
    • “Heterogeneous 3D integration for quantum computer chip”, Ryoichi Ishihara, TU Delft, NL
  • 12:30 : Closing

Workshop Committee

Pascal Vivet, CEA-List & IRT Nanoelec, France

Gianna Paulin, ETH-Z, Switzerland

Peter Ramm, Fraunhofer EMFT, Germany

Mustafa Badaroglu, QUALCOMM, United States

Subhasish Mitra, Stanford University, United States

Past editions

The 3D Integration workshop took place from 2009 to 2015 and restarted in 2022.

W01 Workshop: Eco-ES: Eco-design and circular economy of Electronic Systems

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Date: Tuesday, 26 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Break-Out Room S6+7


Chiara Sandionigi, CEA, FR

David Bol, UC Louvain, BE

Jonas Gustafsson, RISE, SE

Jean-Christophe Crebier, CNRS/G-INP/UGA, FR

Eco-ES, the workshops devoted to Eco-design and circular economy of Electronic Systems, comes back to DATE 2024 for its second edition. This half-day event consists of a plenary keynote, invited talks and regular presentations. As a novelty, the second edition proposes also a session dedicated to European projects working on the sustainability of electronics.

Workshop Description

The impact of electronics on the environment is becoming an important issue, especially because of the number of systems growing exponentially. Eco-design and circular economy applied to Electronic Systems are thus becoming major challenges for our society to respond to the dangers for the environment: exponential increase in electronic waste generation, depletion of resources, contribution to climate change and poor resiliency to supply-chain issues. Electronic Systems designers willing to engage in eco-design face several difficulties, related in particular to a limited knowledge of the environmental impact from the design phase and the uncertain extension of the service lifetime of the system or parts of the system, owing to the variability in user behaviour and business models.

The objective of the workshop Eco-ES is to gather experts from both academia and industry, covering a wide scope in the environmental sustainability of Electronic Systems. Regular sessions with talks and a poster session will offer a place for the audience to discuss and share ideas.

Topic Areas

Workshop topics include:

  • Specification and modelling of sustainable Electronic Systems
  • Life Cycle Assessment tools and techniques
  • Electronic Design Automation tools for eco-design
  • Design Space Exploration including environmental aspects
  • Eco-reliability techniques to design sustainable systems with extended lifetime
  • Reparability methods
  • Reuse strategies
  • Recycling of Electronic Systems and Refurbish for a second life of the products
  • Digital infrastructure refresh and reuse strategies
  • Inter-disciplinary works linking the technology aspects of eco-design and circular economy to social and economic sciences
  • Projects in progress on the previous topics

Introduction and keynote

Tue, 14:00 - 14:40

14.00: Workshop introduction (C. Sandionigi, CEA)

14.10: Keynote - Challenged with Planetary Boundaries? Addressing Design for Absolute Sustainability in Electronics Research and Development Processes (M. Rio, INP-Gre)

Sustainable electronics in Europe

Tue, 14:40 - 16:00

Session chair

Jonas Gustafsson, RISE, SE

14.40: Towards the creation of a European ecosystem for Sustainable Electronics (C. Sandionigi, CEA)

15.00: The Sustronics project (O. Kattan, Philips)

15.20: ESOS - Electronics: Sustainable, Open and Sovereign (T. Marty, INSA-Rennes)

15.40: Components circular re-use of electronic scrap (N. Canis-Moal, Continental; J. Gabriel, CEA)

Life Cycle Assessment and eco-design of electronics

Tue, 16:15 - 18:00

Session chair

Chiara Sandionigi, CEA, FR

16.15: 4MOD's eco-design method for consumer electronics: Integrating Life Cycle Assessment into the design and R&D process (E. Whitmore, 4MOD)

16.30: Assessing the embodied carbon footprint of a cellular base station with a parametric LCA (R. Dethienne, UCLouvain)

16.45: Data center IT hardware refresh driven by environmental impact assessment for a circular economy (P. Thampi, RISE)

17.00: Chiplets: Opportunities for reusable/replaceable/life-extended sustainable electronic chips (R. Massoud, EPFL)

17.15: On the need for open life cycle analysis datasets (T. Marty, INSA-Rennes)

17.30: Integrating screening Life Cycle Assessment in digital system design flow to enable eco-design (M. Peralta, CEA)

17.45: Making electronic greener? Profiling greener IC and boards (G. Saucier, D&R)

W08 ASD-Workshop: Autonomous Systems Certification and Homologation

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Date: Tuesday, 26 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Break-Out Room S8


Selma Saidi, Technische Universität Dortmund, Germany

Rolf Ernst, Technical University Braunschweig, Germany

Sebastian Steinhorst, Technical University of Munich, Germany

ASD6 Workshop (Tuesday March 26: 14h00h- 18h00)

Title: “Autonomous Systems Certification and Homologation”

Abstract: Autonomous functions have been proposed for pretty much all transport systems, vehicles, aircraft, or rail systems. Such transport systems and their design are governed by safety standards that are developed by large groups in public bodies or standardization organizations. At the core of such safety standards are certification or homologation processes that govern the regulatory approval of an autonomous system. A major challenge for this approval is the coexistence of traditional transport systems and transport systems with different levels of autonomy. This coexistence is a necessity, as there will be no exclusive space for autonomous transport systems, neither in the air nor on the ground, especially in densely populated areas. There are many related projects and initiatives addressing this challenge with different requirements and rules, in part a result of the specific form of potential system interference, in part based on the tradition of safety guarantees in the respective domain. The European U-space initiative is a very good example regulating the coexistence of traditional and unmanned aircrafts and drones and the related design processes and protection mechanisms.

Workshop Organization: After an introduction, the workshop will start with a first session of introductory talks by experts from industry and public authorities in the different domains. In the second session, a panel of experts will discuss the implications for Autonomous Systems Design and research in the field.

ASD6.1: Introductory Talks (14h00-16h00)

Talk 1: “ISO PAS 8800: An AI safety standard for automotive applications”,

Simon Burton, Independent Consultant and Honorary Visiting Professor, University of York

Talk 2: “Certifying Autonomy in Railway Systems”,

Mario Trapp, Director Fraunhofer Institute Cognitive Systems

Talk 3: “AI Assurance and Challenges”,

Huafeng Yu, Highly Automated Systems Safety Center of Excellence (HASS COE), US Department of Transportation

Talk 4: “Autonomous Systems: Management Oversight of Certification and Homologation”,

William Widen, School of Law, University of Miami

ASD6.2: Panel (16h30-18h00)

Confirmed Panelists:

  • Huafeng Yu, HASS COE, US Department of Transportation
  • Simon Burton, Independent Consultant & University of York
  • Bill Widen, University of Miami
  • Mario Trapp, Fraunhofer IKS
  • Matthieu Gallas, Airbus
  • Benjamin Lesage, ONERA

ET01 Embedded Tutorial: Using Generative AI for Next-generation EDA

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Date: Tuesday, 26 March 2024
Time: 16:30 CET - 18:00 CET
Location / Room: Break-Out Room S1+2


Hammond Pearce, University of New South Wales Sydney, Australia


Jason Blocklove, NYU, United States

Siddharth Garg, NYU, United States

Jeyavaijayan Rajendran, TAMU, United States

Ramesh Karri, NYU, United States


Tutorial resources:

Motivation: There are increasing demands for integrated circuits but a shortage of designers - Cadence’s blog reports a shortage of 67,000 employees in the US alone. These increasing pressures alongside shifts to smaller nodes and more complexity lead to buggy designs and slow time-to-market. State-of-art Generative AI tools like GPT-4 and Bard have shown promising capabilities in automatic generation of register transfer level (RTL) code, assertions, and testbenches, and in bug/Trojan detection. Such models can be further specialized for hardware tasks by fine-tuning on open-source datasets. As Generative AI solutions find increasing adoption in the EDA flow, there is a need for training EDA experts on using, training and fine-tuning such models in the hardware context.
Intended audience: Students, academics, and practitioners in EDA/VLSI/FPGA and Security
Objectives In this tutorial we will show the audience how one can use current capabilities in generative AI (e.g. ChatGPT) to accelerate hardware design tasks. We will explore how it can be used with both closed and open-source tooling, and how you can also train your own language models and produce designs in a fully open-source manner. We'll discuss how commercial operators are beginning to make moves in this space (GitHub Copilot, Cadence JedAI) and reflect on the consequences of this in education and industry (will our designs become buggier? Will our graduating VLSI students know less?). We'll cover all of this using a representative suite of examples both simple (basic shift registers) to complex (AXI bus components and microprocessor designs).
Abstract There are ever-increasing demands on complexity and production timelines for integrated circuits. This puts pressure on chip designers and design processes, and ultimately results in buggy designs with potentially exploitable mistakes. When computer chips underpin every part of modern life, enabling everything from your cell phone to your car, traffic lights to pacemakers, coffee machines to wireless headphones, then mistakes have significant consequences. This unfortunate combination of demand and increasing difficulty has resulted in shortages of qualified engineers, with some reports indicating that there are 67,000 jobs in the field yet unfilled.


Fortunately, there is a path forward. For decades, the Electronic Design Automation (EDA) field has applied the ever-increasing capabilities from the domains of machine learning and artificial intelligence to steps throughout the chip design flow. Steps from layouts, power and performance analysis and estimation, and physical design are all improved by programs taught rather than programmed.

In this tutorial we will explore what's coming next: EDA applications from the newest type of artificial intelligence, generative pre-trained transformers (GPTs), also known as Large Language Models. We will show how models like the popular ChatGPT can be applied to tasks such as writing HDL, searching for and repairing bugs, and even applying itself to the production of complex debugging tasks like producing assertions. Rather than constrain oneself just to commercial and closed-source tooling, we'll also show how you can train your own language models and produce designs in a fully open-source manner. We'll discuss how commercial operators are beginning to make moves in this space (GitHub Copilot, Cadence JedAI) and reflect on the consequences of this in education and industry (will our designs become buggier? Will our graduating VLSI students know less?). We'll cover all of this using a representative suite of examples both simple (basic shift registers) to complex (AXI bus components and microprocessor designs).

Necessary background Experience with EDA flows and softwares such as Xilinx Vivado, Yosys, iverilog, etc. will be helpful but is not required as training on the day will be provided.

(Tutorial presenters in bold)

S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. Dolan Gavitt, S. Garg , "Benchmarking Large Language Models for Automated Verilog RTL Code Generation," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6, doi: 10.23919/DATE56975.2023.10137086.

J. Blocklove, S. Garg., R. Karri, H. Pearce, “Chip-Chat: Challenges and Opportunities in Conversational Hardware Design,” 2023 Machine Learning in CAD Workshop (MLCAD),. Preprint:

H. Pearce, B. Tan, B. Ahmad, R. Karri and B. Dolan-Gavitt, "Examining Zero-Shot Vulnerability Repair with Large Language Models," 2023 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, USA, 2023, pp. 2339-2356, doi: 10.1109/SP46215.2023.10179324.

B. Ahmad, S. Thakur, B. Tan, R. Karri, H. Pearce, “Fixing Hardware Security Bugs with Large Language Models,” under review. Preprint:

R. Kande, H. Pearce, B. Tan, B. Dolan-Gavitt, S. Thakur, R. Karri, J. Rajendran, “LLM-assisted Generation of Hardware Assertions,” under review. Preprint:

On the day:

Hands on session

Content: Audience members will use the language models to achieve various tasks within a simple EDA environment focused on simulation.

Goals: While we will also demo approaches using more complex software, the hands-on session will focus on the use of iverilog, which is a simple, free, and open-source software for simulation of Verilog designs. iverilog is not demanding (it can be run on local machines/laptops) and is compatible with windows, Linux, and mac.

Pre-requisites: While it is preferable for participants to have installed gcc, build-essential, iverilog, and gtkwave in advance, doing so on the day is not difficult and we can provide guidance at the beginning of the session.

Tutorial material Reference material on the pre-requisites and the manuscripts from the listed references.
Tutorial plan

0-15 mins: Introduction and motivation by Hammond Pearce, Ramesh Karri, Siddharth Garg, and Jason Blocklove (presenter TBD)

15-35 mins: Hands-on Chip-chat - using ChatGPT for writing, simulating, and bug-fixing Verilog by Jason Blocklove and Hammond Pearce (participants will be provided with scripts that they can adapt to interact with ChatGPT for their own tools)

35-60 mins: Hands-on VeriGen: Developing Open-source EDA datasets and models by Shailja Thakur and Jason Blocklove

60-80 mins: AI for Bug Detection: Accelerating hardware fuzzing and flagging bugs and Trojans with Generative AI by Benjamin Tan and JV Rajendran

80-90 mins: Gazing into the Crystal Ball: The future of EDA with Generative AI by Siddharth Garg and Ramesh Karri

ET04 Embedded Tutorial: Introduction to Certifiable General Purpose GPU Programming for Safety-Critical Systems using Khronos APIs

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Date: Wednesday, 27 March 2024
Time: 08:30 CET - 10:00 CET
Location / Room: Break-Out Room S6+7

GPUs are currently considered from all safety critical industries (automotive, avionics, aerospace, healthcare and others) to accelerate general purpose computations and meet performance requirements of new advanced functionalities, which are not possible with the legacy, single-core processors used in these domains. However, most of the R&D in companies from these domains is focused on proof of concepts, which demonstrate the capabilities of employing GPUs in these domains, ignoring the certification challenges introduced by GPUs.

In this tutorial, we will teach the attendees how general purpose GPU code can be developed and certified according to safety critical standards used in these industries, using open standards such as Khronos APIs. In particular, the tutorial covers two essential APIs. The first half is focused on OpenGL SC 2.0, a well established graphics API already deployed in several high criticality systems, including DAL A systems in avionics such as the primary flight displays in modern aircraft, as well as in ASIL D systems in automotive dashboards of contemporary high-end vehicles.

The second half of the tutorial focuses on SYCL and its upcoming variant SYCL SC, which abstracts away the low-end complexity of heterogeneous programming in safety critical systems. SYCL is a programming model that lets developers support a wide variety of devices (CPUs, GPUs, and through the SYCLOPS Horizon project RISC-V accelerators) from a single code base. Given the growing heterogeneity of processor roadmaps, moving to an open platform-independent standard such as SYCL is essential for modern software developers. SYCL has the further advantage of supporting a single-source style of programming from completely standard C++. In this tutorial, we will introduce SYCL and provide programmers with a solid foundation they can build on to gain mastery of this language. The main benefit of using SYCL over other heterogeneous programming models is the single programming language approach, which enables one to target multiple devices using the same programming model, and therefore to have a cleaner, portable, and more readable code.

The tutorial includes the latest advancements in Khronos SC APIs, through the developments in the on-going Horizon Europe projects, METASAT ( and SYCLOPS (

This is a hands-on tutorial. The format will be short presentations followed by hands-on exercises. Hence, attendees will require their own laptop to perform the hands-on exercises, by connecting to a ready to use remote system with a preinstalled environment.


  • Leonidas Kosmidis, Barcelona Supercomputing Center (BSC)
  • Victor Perez, Codeplay/Intel

Target Audience

Academic and industrial attendees from the domain of embedded, real-time and safety critical areas, who are interested in safety critical GPU programming APIs and safety certification. We expect particular interest from DATE attendees, as well as from the ones attending the Autonomous Systems Design (ASD) initiative at DATE. This includes practitioners from automotive, avionics, space and other safety critical domains, which face high performance needs that can be satisfied by GPUs.

Learning objectives

The tutorial is going to be a mixture of fundamentals and hands on. At first, we will introduce the fundamental theory/concepts on how we can achieve certification of general purpose GPU code, using already certified graphics-based solutions such as OpenGL SC 2.0. Next we will present the upcoming solution, SYCL, whose SC version is currently under development at Khronos. During the interleaved presentations and hands-on sessions, the attendees will have the opportunity to obtain hands on experience with the presented methods through a series of exercises.

Required background

The tutorial attendees must be familiar with C++. Moreover, understanding of safety critical systems and familiarity with at least one safety standard (ISO 26262, DO-178C, ECSS) and safety critical code development guidelines (i.e. MISRA C/C++) is desirable but not required.

Detailed Program

8:30 - 8:40 Certification and challenges with GPUs (L. Kosmidis)
8:40 - 9:10 OpenGL SC 2.0 (L. Kosmidis)
9:10 - 9:50 SYCL (V. Perez)
9:50 - 10:00 What’s new in upcoming SYCL SC (L. Kosmidis)

W07 Workshop: Enabling rapid and sustainable RISC-V based research using open source HW and SW

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Date: Wednesday, 27 March 2024
Time: 08:30 CET - 12:30 CET
Location / Room: Break-Out Room S3+4


David Atienza, EPFL, CH

Davide Schiavone, ESL, EPFL, CH

Jose Miranda, ESL, EPFL, CH

Alfonso Rodriguez, CEI, UPM, ES

Alessio Burrello, Polytechnic of Turin, IT

Daniele Pagliari, Polytechnic of Turin, IT

Maurizio Martina, Polytechnic of Turin, IT


As our world becomes more interconnected and reliant on digital systems, the need for transparency, accessibility, and collaborative innovation in hardware and software design has become paramount. Closed and proprietary solutions often limit user sovereignty and control, hinder interoperability, and stifle innovation by locking users into a specific ecosystem. In contrast, open-source initiatives are leading towards rapid prototyping of novel ideas and systems and unlocking from any specific vendor by empowering academic and industrial users to control, modify, and build upon existing technology. This workshop will bring both academic and industry members into a discussion about open-source hardware (HW) and software (SW) interests and showcase the potential of open-source technology with the eXtendable Heterogeneous Energy-Efficient Platform, X-HEEP. X-HEEP is an EU and RISC-V-based enabler platform for rapid and sustainable VLSI/ASIC system design, automation, and testing. Following the success stories of open-source projects in the SW ecosystem, with Linux kernel as the best example, X-HEEP aims to foster innovative, easy-to-integrate, easy-to-use ASIC-oriented technology. Similarly, other open-source HW initiatives, such as OpenHW Group, OpenRoad, and SkyWater are already revolutionising the semiconductor industry by democratising chip design via open-source IPs, EDA tools, and PDKs. To this end, X-HEEP enables HW research and freely delivers industrial-grade, silicon-proven open-source CPU IPs from OpenHW. Together with our academic and industrial partners, we will showcase the usage of X-HEEP for 1) SW engineers to deploy end-to-end applications, 2) HW engineers to integrate and evaluate their own IPs, and 3) system-level designers to architect a full system using its configurability and extendibility capabilities.

Open-source HW and SW are becoming essential in the rapidly evolving technological landscape. This workshop fosters a shared knowledge and creativity culture, enabling a broader range of applications, from affordable healthcare devices to sustainable energy solutions. It stands as a critical pillar for a more inclusive, innovative, and sustainable technological future. Thus, open-source hardware and software is a paramount topic for the DATE conference, as it encourages ethical and sustainable practices by promoting repairability and reducing electronic waste. This topic is completely integrated and part of DATE’s technical scope considering the four different conference tracks. Moreover, the presentation and fostering of openly, easy-to-integrate, and easy-to-use ASIC-oriented technology is innovative, and we can expect submissions in this regard in the future.

W05 Workshop: Unlocking Tomorrow's Technology: Hyperdimensional Computing and Vector Symbolic Architectures for Automation and Design in Technology and Systems

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Date: Wednesday, 27 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Break-Out Room S3+4


Antonello Rosato, Sapienza University of Rome, IT

Short Description: The Workshop at DATE 2024 invites submissions for an exploration of cutting-edge developments in Hyperdimensional Computing (HDC) and Vector Symbolic Architectures (VSA) regarding the both the theory and application of these concepts to study, design and automate new systems that leverage the mathematical properties of high-dimensional spaces. The goal is to provide new insights on how HDC and VSA can be useful for a variety of practical applications in different field, also to enhance our understanding of human perception and cognition. The workshop will be organized in two main parts: an invited speakers’ keynote presentation and a poster session with open discussion.

Format: Hybrid event, with invited speakers and call for poster presentations.

Scope: We seek participants that delve into the practical application of HDC and VSA principles in various domains, with a particular focus on automation, design, and advanced AI functionalities. The poster presentations are encouraged in the following areas (but not limited to):

  1. Neural Network Models and AI algorithms: Present novel solutions and systems utilizing HDC and VSA in neural network architectures and generalized AI models, emphasizing their application potential.
  2. Practical Applications: Showcase how HDC and VSA concepts have been deployed to solve real-world challenges in fields such as Computer Vision, Wireless Communication, Language Processing, Classification, Time Series Prediction, and Neural Modeling.
  3. System Design: Explore the potential of constructing comprehensive artificial intelligence systems based on HDC/VSA principles and discuss the taxonomy of recent advancements in this area.
  4. Interpretability and Human Interaction: Investigate the new possible insights obtainable via HDC & VSA on explainability and human-machine teaming.
  5. Future Directions and New Perspectives: Reflect on the present and future of HDC and VSA principles, in the theory realm and examining their applications in emerging technologies such as robotics and energy-aware AI developments.


Wed, 14:00 - 18:00


Evgeny Osipov, Luleå University of Technology, SE

Abbas Rahimi, IBM Research Zurich, CH

Alpha Renner, Peter Grünberg Institute, DE

Kenny Schlegel, Chemnitz University of Technology, DE

Poster Session

Wed, 16:00 - 18:00


W06 Workshop: Tips and Tricks for a Successful Multi-Project-Wafer (MPW) Chip

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Date: Wednesday, 27 March 2024
Time: 14:00 CET - 18:00 CET
Location / Room: Break-Out Room S6+7


Clive Holmes, Europractice, UK

Tobias Vanderhenst, imec / EUROPRACTICE, BE

Paul Malisse, imec / EUROPRACTICE, BE

Thomas Drischel, Fraunhofer IIS / EUROPRACTICE, DE

URL: Learn about MPW Fabrication with EUROPRACTICE

Multi-Project-Wafer (MPW) prototyping is a cost-effective and fast way to fabricate, test and validate new chip designs. However, it also poses several challenges and pitfalls that can compromise the quality and functionality of the final chip. This leads to eventual design iterations, extending the initial timeline and increasing costs.

In this workshop, EUROPRACTICE experts will discuss the best practices and lessons learned from the MPW prototyping process, sharing practical tips and tricks on avoiding common errors, optimising the design for tape-out, and troubleshooting the issues that may arise.

We will also discuss how to select the appropriate test and packaging options, especially for smaller advanced nodes. In addition, we will showcase some successful examples and case studies of MPW prototyping from different domains and applications. Finally, we will explain how to access the EUROPRACTICE platform, which provides affordable MPW fabrication services in a wide range of technologies, including ASICs, MEMS, Photonics, Microfluidics, Flexible Electronics, and more.

The workshop is intended for anyone who is interested in or involved in MPW prototyping, from beginners to experts.

RTL signoff analysis

Wed, 14:00 - 14:45




Choosing a technology for your design

Wed, 14:45 - 15:30



Design finishing and sign off

Wed, 16:00 - 16:45


Tobias Vanderhenst, imec / EUROPRACTICE, BE

Syed Shahnawaz, Fraunhofer IIS / EUROPRACTICE, DE

Selecting a packaging solution

Wed, 16:45 - 17:30


Tobias Vanderhenst, imec / EUROPRACTICE, BE