PhD Forum Best Poster Prize supported by EDAA, ACM Sigda and IEEE CEDA

Enabling Caches in Probabilistic Timing Analysis
Leonidas Kosmidis, Barcelona Supercomputing Center, ES

Towards Computer-Aided Design of Quantum Logic
Philipp Niemann, University of Bremen, DE

IEEE Fellow Award

Prof. Todd Austin University of Michigan elevated to IEEE Fellow "for contributions to simulation techniques and resilient system design in computer architecture”
Prof. Valeria Bertacco University of Michigan elevated to IEEE Fellow "for contribution to computer-aided verification and reliable system design”
Prof. Cristina Silvano Politecnico di Milano elevated to IEEE Fellow “for contributions to energy-efficient computer architectures”
Prof. Alex Yakovlev Newcastle University elevated to IEEE Fellow “for contributions to theory and design of asynchronous circuits”

DATE Fellow Award

Dr. Juergen Haase edacentrum For long term outstanding contribution to the DATE Exhibition Theatre
Prof. Luca Fanucci Università di Pisa For outstanding service contribution as General Chair of DATE 2016

IEEE CEDA Service Award

Prof. Luca Fanucci For outstanding service contribution as General Chair of DATE 2016

IEEE CS TTTC Outstanding Contribution Award

Prof. Luca Fanucci For outstanding service contribution as General Chair of DATE 2016

IEEE TTTC Lifetime Contribution Medal

Bernard Courtois For outstanding technical contribution and fundamental impact on Test Technology

DATE 2017 Best Paper Awards

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by an award committee, based on the results of the reviewing process and the quality of the final paper.

DATE Best Paper Awards have been given during the DATE Party

D Track

AUTOMATIC PLACE-AND-ROUTE OF EMERGING LED-DRIVEN WIRES WITHIN A MONOLITHICALLY-INTEGRATED CMOS+III-V PROCESS
Tushar Krishna¹, Arya Balachandran², Siau Ben Chiah², Li Zhang³, Bing Wang³, Cong Wang², Kenneth Lee Eng Kian³, Jurgen Michel⁴ and Li-Shiuan Peh^5
1Georgia Institute of Technology, US; ²NTU, SG; ³SMART, SG; ⁴MIT, US; ⁵Professor, National University of Singapore, SG

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A Track

COSYN: EFFICIENT SINGLE-CELL ANALYSIS USING A HYBRID MICROFLUIDIC PLATFORM
Mohamed Ibrahim¹, Krishnendu Chakrabarty¹ and Ulf Schlichtmann^2
1Duke University, US; ²TU München, DE

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T Track

FAST AND WAVEFORM-ACCURATE HAZARD-AWARE SAT-BASED TSOF ATPG
Jan Burchard¹, Dominik Erb¹, Adit D. Singh², Sudhakar M. Reddy³ and Bernd Becker^1
1University of Freiburg, DE; ²Auburn University, US; ³University of Iowa, US

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E Track

MODNN: LOCAL DISTRIBUTED MOBILE COMPUTING SYSTEM FOR DEEP NEURAL NETWORK
Jiachen Mao¹, Xiang Chen², Kent W. Nixon¹, Christopher Krieger³ and Yiran Chen^1
1University of Pittsburgh, US; ²George Mason University, US; ³University of Maryland, Baltimore County, US

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DATE 2017 Best IP Award

DATE Best IP Award has been given during the DATE Party

EVOAPPROX8B: LIBRARY OF APPROXIMATE ADDERS AND MULTIPLIERS FOR CIRCUIT DESIGN AND BENCHMARKING OF APPROXIMATION METHODS (Paper/SoftConf ID: 241)
Vojtech Mrazek, Radek Hrbacek, Zdenek Vasicek and Lukas Sekanina, Brno University of Technology, CZ

New directions in software design and optimization for embedded, cyber-physical and secure systems

Marco Zimmerling, Ph.D. (ETHZ, CH; Advisor: Prof. Lothar Thiele)

"End-to-end Predictability and Efficiency in Low-power Wireless Networks"

New directions in system-on-chip platforms co-design, novel architectures and system-level management

Bingjun Xiao, Ph.D. (UCLA, US; Advisor: Prof. Jason Cong)

"Communication Optimization for Customizable Domain-Specific Computing"

New directions in logic, physical design and CAD for analog/mixed-signal, nano-scale and emerging technologies

Kai Hu, Ph.D. (Duke University, USA; Advisor: Prof. Krishnendu Chakrabarty)

"Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips"

New directions in robust circuit design, reliability-aware design and system test

Veit Benedikt Kleeberger, Ph.D. (TUM, DE; Advisor: Prof. Ulf Schlichtmann)

"Resilient Cross-Layer Design of Digital Integrated Circuits"

DATE 2017 opens doors on March 27 at the SwissTech Convention Center in Lausanne, Switzerland
2017 is a special year for the world’s favourite electronic systems design and test conference, as we celebrate its 20th edition and it will be held for the first time in Switzerland, at the SwissTech Convention Center on the EPFL campus in Lausanne, from March 27 to 31, 2017.

On Tuesday, the conference will be opened by the plenary keynote speakers Dr. Arvind Krishna from IBM who will talk about “Design Automation in the Era of AI and IoT: Challenges and Pitfalls” and Dr. Doug Burger from Microsoft to talk about “A New Era of Hardware Microservices in the Cloud”. In addition, a keynote lecture from Prof. Giovanni De Micheli (Professor at EPFL and Director of Nano-Tera.ch) will be given on Tuesday on "Distributed Systems for Health and Environmental Monitoring" within the Nano-Tera.ch initiative. On the same day, the Executive Track, including one Executive Panel Session and three Innovative Technologies & Applications (IT&A) Sessions, offers a series of business panels discussing hot topics. Executive speakers from companies leading the design and automation industry will address some of the complexity issues in electronics design and discuss about the advanced technology challenges and opportunities. A special session is dedicated to Ralph Otten, pioneer of physical design, who prematurely died in an accident.

Two Special Days in the programme will focus on areas bringing new challenges to the system design community: Designing Electronics for the Internet of Things Era and Designing Wearable and Smart Medical Devices, each having a full programme of keynotes, panels, tutorials and technical presentations.