Welcome to the DATE 2021 Website

DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

Wed, 3 Mar 2021 22:40

DATE 2021 conference – the DATE community gathered virtually in large numbers for another unique conference

Following the last-minute transformation of DATE 2020 to a virtual conference, DATE planned to gather its community again in Grenoble, France for DATE 2021 from 1 to 5 February 2021. Again, considering the continued erratic development of the worldwide COVID-19 pandemic and thus related restrictions of world-wide travelling as well as the safety and health of the DATE community, the Organising Committees decided to also host DATE 2021 as a virtual conference.

DATE combines the world’s favourite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. This year, the conference was held as a virtual live conference from 1 to 5 February 2021 which offered an exciting, wide-ranging technical programme.

The 2021 DATE week was opened by six in-depth technical tutorials on the main topics and given by leading experts in their respective fields. The topics covered Industrial Control Systems Security, Software-Defined Hardware: Digital Design in the 21st Century with Chisel, How Emerging Memory Technology Will Reshape Future Computing, Security in the Post-Quantum Era: Threats and Countermeasures, Automation goes both ways: ML for security and security for ML as well as CAD for SoC Security.

With the Opening Ceremony, live online on Tuesday morning, virtual DATE 2021 officially opened its doors and started off with one of the plenary keynote lectures given by John Martinis, professor of Physics at UC Santa Barbara, who gave an insight on “Quantum Supremacy Using A Programmable Superconducting Processor”.

Anna Grassellino, recently named “Woman of the Year” by the Italian magazine “D La Repubblica”, opened the afternoon live slot of the online conference with her plenary keynote lecture on “Superconducting Quantum Materials and Systems (SQMS) – a new DOE National Quantum Information Science Research Center”.

61 technical sessions were organized in line with the main conference programme, which participants could follow live during two time slots each from Tuesday to Thursday.

Thu, 4 Feb 2021 20:00

DATE 2021 Awards

Awards Ceremony during DATE 2021 Closing Session

Best IP Award


Isaías Bittencourt Felzmann1, João Fabrício Filho2 and Lucas Wanner2

1University of Campinas, BR; 2Unicamp/UTFPR, BR; 2Unicamp, BR

ACM SIGDA/CEDA/EDAA PhD Forum Best Poster Prize


Muhammad Abdullah Hanif

Institute of Computer Engineering, Vienna University of Technology, AT


Dr. G.A. Gillani

University of Twente, NL

EDAA Outstanding Dissertations Award 2020

Topic 1:

Thesis: "Accelerator Architectures for Deep learning and Graph Processing"

Linghao Song, Ph.D. (Duke University, US, Advisor: Prof. Yiran Chen and Prof. Hai Li)

Topic 2:

Thesis: "Data Structures and Algorithms for Logic Synthesis in Advanced Technologies".

Eleonora Testa, Ph.D. (EPFL, CH; Advisors: Prof. Giovanni de Micheli and Dr. Mathias Soeken)

Topic 3:

Thesis: "Remote Attacks on FPGA Hardware"

Dennis Gnad, PhD. (KIT, DE; Advisor: Prof. Mehdi Tahoori)

Topic 4:

Thesis: "Improving DRAM Performance, Security and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins"

Jeremie Kim, Ph.D. (Carnegie Mellon University, US; Advisor: Prof. Onur Mutlu)

Previous recipients of the award

Will be announced in Closing Ceremony on Thursday, 4 February 2021

Best University Booth Award


Daniel Hauer, Friedrich Bauer, Felix Braun, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima TaheriNejad and Philipp-Sebastian Vogt

TU Wien, AT

Awards Ceremony during DATE 2021 Opening Session

EDAA Achievement Award

Georges Gielen, KU Leuven, BE

Press release

DATE Fellow Award

Giorgio Di Natale, TIMA / Université Grenoble Alpes, FR

IEEE Fellow Award

Mehdi Tahoori, Karlsruhe Institute of Technology, DE

For contributions to resilient nanoscale integrated circuits

DATE Best Paper Awards 2021

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Ian O'Connor, Theocharis Theocharides, Ilia Polian and Valeria Bertacco and the following members: Lorena Anghel, David Atienza, Koen Bertels, Christos-Savvas Bouganis, Luca Carloni, Stefano Di Carlo, Jose Flich, Pierre-Emmanuel Gaillardon, Tsung-Yi Ho, Artur Jutman, Huichu Liu, Jan Madsen, Maria K. Michael, Francesco Regazzoni, Johanna Sepulveda, Muhammad Shafique, Haralampos Stratigopoulos, Lionel Torres, Jiang Xu, Chengmo Yang.

The DATE 2021 best papers are:

D Track

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

A Track

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

T Track

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2, Gernot Heiser3

1 ETH Zurich, 2 Università di Bologna and ETH Zurich, 3 UNSW and Data61, CSIRO

E Track

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia1, Arne Hamann2, Dirk Ziegenbein2, Martina Maggio3

1 Universität des Saarlandes, 2 Robert Bosch GmbH, 3 Lund University


Best Paper Award Nominations

D Track

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Qi Sun1, Tinghuan Chen1, Siting Liu1, Jin Miao2, Jianli Chen3, Hao Yu4, Bei Yu1

1 The Chinese University of Hong Kong, 2 Cadence Design Systems, 3 Fudan University, 4 Southern University of Science and Technology

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks

Aqeeb Iqbal Arkal1, Biresh Kumar Joardar1, Jana Doppa1,

Partha Pratim Pande1, Krishnendu Chakrabarty2

1 Washington State University, 2 Duke University

LSP: Collective Cross-Page Prefetching for NVM

Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen

Chinese Academy of Sciences

Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration

Ourania Spantidi1, Iraklis Anagnostopoulos1, Georgios Fainekos2

1 Southern Illinois University Carbondale, 2 Arizona State University

Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance

Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, Mikail Yayla

Technical University of Dortmund

FPGA Architectures for Approximate Dense SLAM Computing

Maria-Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas

University of Thessaly

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Ravi Ledalla, Chaobo Li, Debjit Sinha, Adil Bhanji, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile

IBM Corporation

COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter

Sven Thijssen1, Sumit Kumar Jha2, Rickard Ewetz1

1 University of Central Florida, 2 University of Texas at San Antonio

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories

Arman Kazemi1, Mohammad Mehdi Sharifi1, Ann Franchesca Laguna1, Franz Mueller2, Ramin Rajaei1, Ricardo Olivo2, Thomas Kaempfe2, Michael Niemier1, X. Sharon Hu1

1 University of Notre Dame, 2 Fraunhofer IPMS-CNT

A Track

Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks

Cyan Subhra Mishra, John (Jack) Sampson, Mahmut Kandemir, Vijaykrishnan Narayanan

The Pennsylvania State University

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache

Anurag Agarwal, Jaspinder Kaur, Shirshendu Das

Indian Institute of Technology Ropar

As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation

Stefan Hillmich1, Richard Kueng1, Igor L. Markov2, Robert Willie1

1 Johannes Kepler University Linz, 2 University of Michigan

T Track

Characterization and Fault Modeling of Intermediate State Defect in STT-MRAMs

Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1, Erik Jan Marinissen2, Gouri Sankar Kar2, Said Hamdioui1

1 Delft University of Technology, 2 IMEC

Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs

Christian Fibich1, Martin Horauer1, Roman Obermaisser2

1 University of Applied Sciences Technikum Wien, 2 University of Siegen

DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures

Muhammad Abdullah Hanif1, Muhammad Shafique2

1 Vienna University of Technology, 2 New York University Abu Dhabi

Digital test of ZigBee transmitters: Validation in industrial test environment

Thibault Vayssade1, Florence Azais1, Laurent Latorre1, François Lefevre2

1 Université de Montpellier, 2 NXP Semiconductors

Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks

Trevor Kroeger1, Wei Cheng2, Sylvain Guilley2, Jean-Luc Danger2, Naghmeh Karimi1

1 University of Maryland, 2 Institut Polytechnique de Paris

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2, Gernot Heiser3

1 ETH Zurich, 2 Università di Bologna and ETH Zurich, 3 UNSW and Data61, CSIRO

E Track

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators

Geng Yuan1, Payman Benham2, Yuxuan Cai1, Ali Shafiee3, Jingyan Fu4, Zhiheng Liao4, Zhengang Li1, Xiaolong Ma1, Jieren Deng5, Jinhui Wang6, Mahdi Bojnordi2, Yanzhi Wang1, Caiwen Ding5

1 Northeastern University, 2 University of Utah, 3 Samsung, 4 North Dakota State University, 5 University of Connecticut, 6 University of South Alabama

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia1, Arne Hamann2, Dirk Ziegenbein2, Martina Maggio3

1 Universität des Saarlandes, 2 Robert Bosch GmbH, 3 Lund University

DATE Newsletter Subscription

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Mon, 1 Feb 2021 13:42

Conference and Exhibition - March 2022

Call for Papers

Scope of the Event

The 25th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, emerging technologies, embedded systems and embedded software.

Structure of the Event

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials, workshops, special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software and (industrial) design experiences from different application domains, such as automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design automation, design and test communities. Special space will also be allocated for multi-partner innovative research projects to show their results.

More details are available on the DATE website: www.date-conference.com.

Areas of Interest

Within the scope of the conference, the main areas of interest are: design automation, design tools and hardware architectures for electronic and embedded systems; test and dependability at system, chip, circuit and device level for analogue and digital electronics; modelling, analysis, design and deployment of embedded software and cyber-physical systems; application design and industrial design experiences.

Topics of interest include, but are not restricted to:

  • System Specification and Modelling
  • System-level Design Methodologies and High-Level Synthesis
  • System Simulation and Validation
  • Formal Methods and Verification
  • Design and Test for Analogue and Mixed-Signal Circuits and Systems, and MEMS
  • Design and Test of Secure Systems
  • Network on Chip and Communication-Centric Design
  • Architectural and Microarchitectural Design
  • Low-power, Energy-efficient and Thermal-aware Design
  • Approximate Computing
  • Reconfigurable Systems
  • Logical and Physical Analysis and Design
  • Emerging Design Technologies for Future Computing
  • Emerging Design Technologies for Future Memories
  • Power-efficient and Sustainable Computing
  • Robotics and Industry 4.0
  • Automotive Systems and Smart Energy Systems
  • Augmented Living and Personalized Healthcare
  • Secure Systems, Circuits and Architectures
  • Self-adaptive and Learning Systems
  • Applications of Emerging Technologies
  • Modelling and Mitigation of Defects, Faults, Variability and Reliability
  • Test Generation, Test Architectures, Design for Test, and Diagnosis
  • Microarchitecture-Level Dependability
  • System-Level Dependability
  • Real-time and Dependable Systems
  • Embedded Systems for Deep Learning
  • Model-based Design, Verification and Security for Embedded Systems
  • Embedded Software Architectures, Compilers and Tool Chains
  • Cyber-Physical Systems Design

Submission of Papers

All papers must be registered by Sunday, 12 September 2021 AoE (title, abstract and co-authors), the final version of the paper to be submitted by Sunday, 19 September 2021 AoE (firm deadline) via: https://www.date-conference.com/

Papers can be submitted either for standard oral presentation or for interactive presentation.

The Program Committee also encourages proposals for Special Sessions, Tutorials, Friday Workshops, University Booth Demonstrations, PhD Forum and Exhibition Theatre.


General Chair:
Cristiana Bolchini, Politecnico di Milano, IT
E-mail: cristiana [dot] bolchiniatpolimi [dot] it

Programme Chair:
Ingrid Verbauwhede, KU Leuven, BE
E-mail: Ingrid [dot] verbauwhedeatkuleuven [dot] be

Conference Organisation

c/o K.I.T. Group GmbH Dresden
Bautzner Str. 117–119, 01099 Dresden, DE
Phone: +49 351 65573-137
E-mail: dateatkitdresden [dot] de

Wed, 6 Jan 2021 10:49

Career Fair – Call for Submissions

Information for Students

The Young People Program aims at bringing together Ph.D. Students and potential job seekers with recruiters from EDA and microelectronic companies. Interested jobseekers have the opportunity to present themselves through a five minutes video and through their CVs to the best workplaces in the industry. If a student raises the interest of the company, the Young People Program chairs will schedule an interview at the company booth or in dedicated interview rooms.


The following two classes of students are eligible:

Tue, 22 Dec 2020 22:11

Event Overview

Mon, 21 Dec 2020 09:50

DATE 2021 - Call for Papers

Submission Key Dates

The accepted papers of DATE 2021 are listed at https://www.date-conference.com/accepted.

Submission Instructions Deadline
Camera-ready paper due date Wednesday, 09 December 2020 23:59:59 AoE Monday, 14 December 2020 23:59:59
Young People Program: Student preregistration is closing Friday, 15 January 2021 23:59:59 AoE
Young People Program: Student final upload date Friday, 22 January 2021 23:59:59 AoE
Young People Program: Company final submission date Monday, 18 January 2021 23:59:59 AoE

Kindly note that all deadlines are strict and no extensions can be given.

Fri, 20 Nov 2020 13:27


The vibrant exhibition at DATE 2018, Dresden

BASIC (Exhibitors)

  • Logo / Link (website, virtual platform)
  • Company profile (website, virtual platform)
  • Small banner (virtual platform)
  • Link to video (virtual platform)
  • Download information material (virtual platform)
  • Chat function at the booth (virtual platform)
  • Presentation in the Exhibition Theatre - if requested
  • Participation in Young People Program - if requested
  • One complimentary conference registration*

(*Please note: this complimentary conference registration includes access to all conference sessions as well as conference materials, but it does neither include access to the Monday Tutorials nor to the Friday Workshops.)

Total cost: € 2,500

Other ideas or special requests?

Tailor-made packages can be arranged to suit your special requests.

Feel free to contact us to discuss your needs and ideas.

For more details, please contact the 

Kathleen Schäfer, K.I.T. Group GmbH Dresden, DEConference Organisation - Exhibition and Sponsorship
Kathleen Schäfer, K.I.T. Group GmbH Dresden, DE
dateatkitdresden [dot] de

Subscribe to



Tue, 07:50
John Martinis

John Martinis, Google, UCSB and Quantala, United States


The promise of quantum computers is that certain computational tasks might be executed exponentially faster on a quantum processor than on a classical processor. A fundamental challenge is to build a high-fidelity processor capable of running quantum algorithms in an exponentially large computational space. Here we report the use of a processor with programmable superconducting qubits to create quantum states on 53 qubits, corresponding to a computational state-space of dimension 2^53 (about 10^16). Measurements from repeated experiments sample the resulting probability distribution, which we verify using classical simulations. Our Sycamore processor takes about 200 seconds to sample one instance of a quantum circuit a million times—our benchmarks currently indicate that the equivalent task for a state-of-the-art classical supercomputer would take approximately 10,000 years. This dramatic increase in speed compared to all known classical algorithms is an experimental realization of quantum supremacy for this specific computational task, heralding a much-anticipated computing paradigm.


John Martinis did pioneering experiments in superconducting qubits in the mid 1980’s for his PhD thesis. He has worked on a variety of low temperature device physics during his career, focusing on quantum computation since the late 1990s. He was awarded the London Prize in Low temperature physics in 2014 for his work in this field. From 2014 to 2020 he worked at Google to build a useful quantum computer, culminating in a quantum supremacy experiment in 2019.

K.2 Opening Keynote: Superconducting Quantum Materials and Systems (SQMS) – a new DOE National Quantum Information Science Research Center

Tue, 15:00
Anna Grassellino

Anna Grassellino, National Quantum Information Science Superconducting Quantum Materials and Systems Center, Fermilab, United States


In this talk I will describe the mission, goals and the partnership strengths of the new US National Quantum Information Research Center SQMS. SQMS brings the power of DOE laboratories, together with industry, academia and other federal entities, to achieve transformational advances in the major cross-cutting challenge of understanding and eliminating the decoherence mechanisms in superconducting 2D and 3D devices, with the final goal of enabling construction and deployment of superior quantum systems for computing and sensing. SQMS combines the strengths of an array of experts and world-class facilities towards these common goals.

Materials science experts will work in understanding and mitigating the key limiting mechanisms of coherence in the quantum regime.  Coherence time is the limit on how long a qubit can retain its quantum state before that state is ruined by noise. It is critical to advancing quantum computing, sensing and communication. SQMS is leading the way in extending coherence time of superconducting quantum systems thanks to world-class materials science and through the world leading expertise in superconducting RF cavities which are integrated with industry-designed and -fabricated computer chips.

Leveraging new understanding from the materials development, quantum device and quantum computing researchers will pursue device integration and quantum controls development for 2-D and 3-D superconducting architectures. One of the ambitious goals of SQMS is to build and deploy a beyond-state-of-the-art quantum computer based on superconducting technologies. Its unique high connectivity will provide unprecedented opportunity to explore novel quantum algorithms. SQMS researchers will ultimately build quantum computer prototypes based on 2-D and 3-D architectures, enabling new quantum simulation for science applications.


Anna Grassellino is the Director of the National Quantum Information Science Superconducting Quantum Materials and Systems Center, a Fermilab Senior Scientist and the head of the Fermilab SQMS division. Her research focuses on radio frequency superconductivity, in particular on understanding and improving SRF cavities performance to enable new applications spanning from particle accelerators to detectors to quantum information science. Grassellino is a fellow of the American Physical Society, and the recipient of numerous awards for her pioneering contributions to SRF technology, including the 2017 Presidential Early Career Award, the 2017 Frank Sacherer Prize of the European Physical Society, the 2016 IEEE PAST Award, the 2016 USPAS prize and a $2.5 million DOE Early Career Award. She holds a Ph.D. in physics from the University of Pennsylvania and a master’s of electronic engineering from the University of Pisa, Italy.


Tue, 10:20
William J. Dally

William J. Dally, Stanford University and NVIDIA, United States


High-Performance computers require continued scaling of performance and efficiency to handle more demanding applications and scales. With the end of Moore’s Law and Dennard Scaling, continued performance scaling will come primarily from specialization. Specialized hardware engines can achieve performance and efficiency from 10x to 10,000x a CPU through specialization, parallelism, and optimized memory access. Graphics processing units are an ideal platform on which to build domain-specific accelerators. They provide very efficient, high performance communication and memory subsystems - which are needed by all domains. Specialization is provided via “cores”, such as tensor cores that accelerate deep learning or ray-tracing cores that accelerate specific applications.


Bill is Chief Scientist and Senior Vice President of Research at NVIDIA Corporation and a Professor (Research) and former chair of Computer Science at Stanford University. Bill is currently working on developing hardware and software to accelerate demanding applications including machine learning, bioinformatics, and logical inference. He has a history of designing innovative and efficient experimental computing systems. While at Bell Labs Bill contributed to the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. At the Massachusetts Institute of Technology his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. At Stanford University his group developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, which led to GPU computing, and the ELM low-power processor. Bill is a Member of the National Academy of Engineering, a Fellow of the IEEE, a Fellow of the ACM, and a Fellow of the American Academy of Arts and Sciences. He has received the ACM Eckert-Mauchly Award, the IEEE Seymour Cray Award, the ACM Maurice Wilkes award, the IEEE-CS Charles Babbage Award, and the IPSJ FUNAI Achievement Award. He currently leads projects on computer architecture, network architecture, circuit design, and programming systems. He has published over 250 papers in these areas, holds over 160 issued patents, and is an author of the textbooks, Digital Design: A Systems Approach, Digital Systems Engineering, and Principles and Practices of Interconnection Networks.

K.4 Keynote: Cyber-Physical Systems for Industry 4.0: An Industrial Perspective

Wed, 15:00

Philippe Magarshack, STMicroelectronics, France

Philippe Magarshack, STMicroelectronics, France

Since 2016, Philippe Magarshack is MDG Group Vice President at ST Microelectronics, in charge of Microcontrollers and Digital ICs Group (MDG) Strategy, Technology & System Architecture. Magarshack was President of the Minalogic Collaborative R&D Cluster in Grenoble France, from 2014 to 2020. In 2012, he was VP for Design Enablement & Services, with a focus on the 28nm FD-SOI design ecosystem, and then during 2015, CTO of the Embedded Processing Solutions. In 2005, Magarshack was appointed Group VP and GM of ST’s Central CAD and Design Solutions for technologies ranging from CMOS to BICMOS and embedded NVM.

In 1994, Magarshack joined the Central R&D Group of SGS-THOMSON Microelectronics (now STMicroelectronics), where he held several roles in CAD and Libraries management for advanced integrated-circuit manufacturing processes. From 1985 to 1989, Magarshack worked as a microprocessor designer at AT&T Bell Labs in the USA. Magarshack graduated with an engineering degree in Physics from Ecole Polytechnique, Paris, France, and with an Electronics Engineering degree from Ecole Nationale Supérieure des Télécommunications in Paris, France.


Thu, 15:00
Pascal Traverse, Airbus, FR

Pascal Traverse, Airbus, France


Autonomy is in the air: on one hand, automation is clearly a lever to improve safety margins; on another hand technologies are maturing, pulled by the automotive market. In this context, Airbus is building a concept airplane from a blank sheet with the objective to improve human-machine teaming for better overall performance. Foundation of this new concept is that when they are made aware of the “big picture” with enough time to analyze it, humans are still the best to make strategic decisions. Autonomy technologies are the main enabler of this concept. Benefit are expected both in a two-crew cockpit and eventually in Single Pilot Operations.


Pascal Traverse is General Manager for the Autonomy “fast track” at Airbus. Autonomy is a top technical focus area for Airbus. The General Manager creates a vision, coordinates R&T activities with the objective to accelerate the increase of knowledge in Airbus. Before his nomination last year, Pascal was coordinating Airbus Commercial R&T activities related to the cockpit and flight operations. Earlier in his carrier, Pascal participated in the A320/A330/A340/A380 Fly-by-Wire developments, certification harmonization with FAA and EASA, management of Airbus safety activities and even of qualities activities in the A380 Final Assembly Line. Pascal has Master and Doctorate’s degrees in embedded systems from N7, conducted research in LAAS and UCLA and is a 3AF Fellow.

K.6 Embedded Keynote: Privacy this unknown - The new design dimension of computing architecture

Thu, 07:00
Mauro Conti

Mauro Conti, University of Padua, Italy


The Security is often presented as being based on the CIA triad, where the “C” actually stands for Confidentiality. Indeed, in many human activities we like to keep some(things) confidential, or “private”; this is particularly true when these activities are done in the cyber world where a lot of our private data are transmitted, processed, and stored.

In this talk, we will first introduce the concept of privacy, and then see how this is interlaced with two important research threads. First we’ll discuss how computer architectures and particularly “trusted components” in processors could be helpful to protect privacy, allowing us to trust remote systems. Finally, we’ll discuss the issues of side-channels (in a broad sense, not only in processors) that could lead to leak of private information.


Mauro Conti is Full Professor at the University of Padua, Italy. He is also affiliated with TU Delft and University of Washington, Seattle. He obtained his Ph.D. from Sapienza University of Rome, Italy, in 2009. After his Ph.D., he was a Post-Doc Researcher at Vrije Universiteit Amsterdam, The Netherlands. In 2011 he joined as Assistant Professor the University of Padua, where he became Associate Professor in 2015, and Full Professor in 2018. He has been Visiting Researcher at GMU, UCLA, UCI, TU Darmstadt, UF, and FIU. He has been awarded with a Marie Curie Fellowship (2012) by the European Commission, and with a Fellowship by the German DAAD (2013). His research is also funded by companies, including Cisco, Intel, and Huawei. His main research interest is in the area of Security and Privacy. In this area, he published more than 350 papers in topmost international peer-reviewed journals and conference. He is Area Editor-in-Chief for IEEE Communications Surveys & Tutorials, and Associate Editor for several journals, including IEEE Communications Surveys & Tutorials, IEEE Transactions on Information Forensics and Security, IEEE Transactions on Dependable and Secure Computing, and IEEE Transactions on Network and Service Management. He was Program Chair for TRUST 2015, ICISS 2016, WiSec 2017, ACNS 2020, and General Chair for SecureComm 2012 and ACM SACMAT 2013. He is Senior Member of the IEEE and ACM. He is a member of the Blockchain Expert Panel of the Italian Government.