The time zone for all times mentioned at the DATE website is CEST – Central Europe Summer Time (UTC+1). AoE = Anywhere on Earth.

OK01.1 Opening Keynote: CHIPLET STANDARDS: A NEW ROUTE TO ARM-BASED CUSTOM SILICON

Start
Mon, 25 Mar 2024 09:00
End
Mon, 25 Mar 2024 09:45

Robert Dimond, ARM, United Kingdom

Abstract

A key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries, with maximum efficiency, while managing costs associated with manufacturing and yield? Today, as the ever more complex AI-accelerated computing landscape evolves, a key solution emerging is chiplets.

Chiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution, made of a number of smaller dice instead of one single larger monolithic die. This creates interesting new design possibilities, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions.
This talk will describe two complementary approaches to realising this chiplet opportunity:
· Decomposing an existing system across multiple chiplets, in the same way a monolithic chip is composed of IP blocks.
· Aggregating well-defined peripherals across a motherboard into a single package.
Both of these approaches require collaboration in standards to align on the many non-differentiating choices in chiplet partitioning. This talk will describe the standards framework that Arm is building with our partners, and the broader industry. Including, own specifications such as the Arm Chiplet System Architecture (Arm CSA), AMBA chip-to-chip and the role of industry standards such as UCIe.

Bio

Rob Dimond is System Architect and Fellow at Arm.
Rob works in the Architecture and Technology group at Arm where his focus is future technology development for the infrastructure segment (servers & networking). Rob is part of the extended leadership team for Arm's Infrastructure line of business.
Prior to Arm, Rob was Chief Hardware Architect at FPGA computing start-up Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College, London.