The workshop begins with an introduction to the growing importance of sustainability in intelligent system design. The kick-off highlights the critical roles of Carbon Footprint reduction, TinyML, and RISC-V, setting the stage for discussions on how these pillars drive energy-efficient and eco-friendly innovations. This opening session underscores the need for collaboration and open-source initiatives to meet global sustainability goals while pushing the boundaries of embedded AI and hardware design.

Achieving a truly sustainable AI continuum requires a holistic approach, where both cloud and edge infrastructures are designed with efficiency in mind. This session highlights the EcoCloud initiative at EPFL, showcasing how it serves as a living example of sustainability in cloud computing. We will discuss how sustainability principles must be integrated at every level—from hardware and system design to software optimization—to build energy-efficient hybrid cloud-edge AI systems. A key focus will be on EcoCloud's experimental facility, which provides a sustainable playground for researchers and industry partners to test and validate novel hardware-software co-design approaches. This facility enables real-world experimentation on energy-efficient architectures, allowing us to push the boundaries of sustainable AI. The talk will also emphasize how these technologies can be leveraged to create scalable, low-power, and environmentally responsible AI solutions. Attendees will be encouraged to actively engage in discussions, making this an interactive session.

The MYRTUS project is paving the way for a more secure, sustainable, and efficient computing ecosystem by leveraging RISC-V and open-source hardware. In this session, we will explore how MYRTUS addresses challenges in trustworthy computing and energy-efficient architectures, focusing on its impact on edge AI, security, and sustainability. Join us to discover how this project shapes the future of hardware-software co-design for next-generation applications. (MYRTUS is funded by the European Union, by grant No. 101135183)

In this talk, we will first describe a novel hardware architecture that merges in-memory computing with a RISC-V core to significantly reduce energy consumption and latency for TinyML tasks. Then, we detail MATCH, a flexible compiler, built on the TVM framework, designed to optimize AI workloads across heterogeneous edge systems prioritizing efficiency. Finally, we will demonstrate the full pipeline by deploying a deep neural network onto the presented hardware using MATCH, showcasing the flexibility of the compilation tool and the efficiency of the in-memory accelerator.

Generative AI (GenAI) models are designed to produce realistic and natural data, such as images, audio, or written text. Due to their high computational and memory demands, these models traditionally run on powerful remote computing servers. However, there is growing interest in deploying GenAI models at the edge, on resource-constrained embedded devices. Since 2018, the TinyML community has proved that running fixed topology AI models on edge devices offers several benefits, including independence from the Internet connectivity, low-latency processing, and enhanced privacy. Nevertheless, deploying resource-consuming GenAI models on embedded devices is challenging since the latter have limited computational, memory, and energy resources. This talk reviews several papers about the progress made to date in the field of Edge GenAI, an emerging area of research within the broader domain of EdgeAI which focuses on bringing GenAI to edge devices. Papers released between 2022 and 2024 that addressed the design and deployment of GenAI models on embedded devices have been identified and described. Additionally, their approaches and results have been compared. These manuscripts contribute to understanding the ongoing transition from TinyML to Edge GenAI, providing the AI research community valuable insights into this emerging and impactful, quite under-explored field. Further examples of Edge GenAI will prove that some of these workloads can run on existing ST MCU and MPU processors, thus showing the EdgeGenAI research field is in active development.

At INTERA we are committed to offering a complete IoT stack, from cloud to edge. At the foundation of the company, we started to work on the development of a proprietary IoT platform, oriented towards the EDGE, i.e. towards communication and control of remote devices. The natural evolution of the platform was the inclusion of AI capabilities, providing execution of models at the cloud level, including automated training and deployment based on continuously acquired data. Recently we started the journey towards the execution of artificial intelligence models at the edge, the so-called EDGE AI, incorporating and adapting open source TinyML/RISC-V worldwide resources, paving the foundation for the development of our own hardware and associated toolchain at an affordable pace. TinyML/RISC-V allows us to co-develop optimised hardware and AI models, connecting them to INTERA's (or third-party) cloud services and products to offer a "full-stack" AI solution. The goal of this journey is to offer technologies and solutions that impact sustainability.

The final session of the workshop will be an interactive roundtable discussion, bringing together experts and attendees to reflect on key insights from the day’s talks. This session will focus on identifying open challenges, future research directions, and collaborative opportunities at the intersection of sustainability-enabling technologies. Participants will have the opportunity to engage directly with speakers and panellists, discussing how the workshop's key themes can drive innovation in embedded AI and eco-friendly computing.