Kick-off presentation: platforms/tools to enable rapid and sustainable ASIC research, design, and implementation

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Integrating reconfigurable hardware components into heterogeneous Systems-on-Chip (SoCs) presents a promising opportunity for tackling the growing demand for performance, flexibility, and energy efficiency in computing systems. In this context, this presentation describes the use of Coarse-Grained Reconfigurable Architectures (CGRAs) for deploying domain-specific applications in energy-constrained scenarios. Despite being less flexible than fine-grain reconfigurable FPGAs, the coarser granularity of the CGRA reconfigurable elements reduces the reconfiguration overhead in terms of time and power consumption. CGRA-base acceleration can benefit from the Open-source RISC-V-based ecosystem to provide innovative SoCs by reusing highly flexible processing architectures already tested and validated, together with the proposed reconfigurable architecture. This approach makes it possible to focus on exploring different configurations for the memory infrastructure, on-chip interconnections, and control interfaces to properly exploit the CGRA. In particular, this presentation addresses the integration of an elastic CGRA accelerator into two different open-source frameworks: Chipyard and X-HEEP. These two variants target different computing scenarios, high-performance, and low-power embedded computing, respectively, showcasing the adaptability of the CGRA fabric while meeting diverse computing needs.

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This talk will discuss how the X-HEEP platform enables a streamlined, open-source, and efficient development of new hardware components and new software flows that target such hardware, including AI deployment on heterogeneous accelerators. Moreover, the talk will discuss hardware and software methods to deal with safety and security aspects. In particular, the talk will focus on three main aspects: i) a near-memory hardware platform designed and tailored to artificial intelligence (AI) and machine learning (ML) applications, mainly deep neural networks (DNNs). This hardware is integrated into the X-HEEP ecosystem, demonstrating the crucial need for an open-source hardware environment to deploy new accelerators efficiently; II) a flexible and automated deployment framework that can be easily extended to new hardware for executing full-fledged DNNs on it. The pipeline will be demonstrated on previous existing open-source hardware, showing the key aspects to be adapted for new hardware platforms as the one shown in the first part; and III) methodologies and key figures to deal with the safety and security of RISC-V systems. Concerning safety, a brief overview of the methods to develop Software Test Libraries (STLs) will be shown, as well as fault grading experiments on RISC-V cores embedded in the X-HEEP ecosystem. On the other side, a preliminary analysis regarding the security issues of a tinyML application fully implemented on X-HEEP was done.

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Embecosm develops commercially robust open source compilers for a wide range of processors. By commercially robust, we mean compilers which reliably produce correct code which is fast and/or compact.

To achieve this robustness, we must thoroughly test and benchmark the compilers. This can be achieved by running on the target architecture's silicon. However we are often developing compilers pre-silicon, and so we must rely on processor models for testing. For functional testing we can use design models or instruction set simulators, although there is always the small risk that the design specification does not match the final implementation. However for benchmarking and sign-off testing, we must use the implementation, for which there are broadly three choices.

1. We can test against traditional event-driven simulation, but such simulators are not very fast, mostly closed source and are not easy to interface to from software environments.

2. We can use FPGA emulation, although not all designs work well in emulation, and large FPGAs can be expensive.

3. Finally, Verilator models are an attractive option, because they are cycle accurate, reasonably fast and easy to interface.

To test a compiler, the target needs more than the processor core. It has to be combined with memory in which to hold programs and data. And for all but the simplest processors its needs a debug unit, to allow the processor to be halted with its exterior state (registers, memory) in a consistent state.

Creating the target with memory and debug is often problematic. It is not the final chip, so has to be created just to allow the tool chain to be tested. X-Heep is the potential solution to this, allowing us to generate FPGA implementations or Verilator models with flexible memory and debug configurations. For this reason we chose X-Heep for testing the compilers for the OpenHW Group's CV32E40Pv2 processors.

In this talk, I'll take you through our experience with X-Heep and its use to generate FPGA bitstreams and Verilator models. I'll look at what worked well and what did not, and I'll present some suggestions on how X-Heep can be improved for the future.

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Open-source hardware holds a promise of sustaining the progress of the semiconductor industry in the age of heterogeneous computing. It can enable design reuse, foster design collaboration, and support workforce development. ESP is an open-source research platform for system-on-chip (SoC) design that combines a modular architecture and an agile design methodology. The ESP architecture simplifies the design and prototyping of heterogeneous chips with multiple RISC-V processor cores and dozens of loosely-coupled accelerators, all interconnected with a scalable network-on-chip. The ESP methodology promotes system-level design while accommodating different specification languages and design flows. ESP's capabilities have allowed a small team of mostly graduate students to realize two SoCs of growing complexity, each in the span of just a few months. Conceived as a heterogeneous system integration platform and developed through years of teaching at Columbia University, ESP is intrinsically suited to advance collaborative engineering across the open-source hardware community.
 

The hardware-software co-design process often involves specialists with different expertise, sometimes struggling to see the big picture. To gain a comprehensive understanding of solution effectiveness and efficiency, design space exploration is crucial. However, it typically involves lengthy simulations or custom developments, posing significant time and resource challenges.
In this presentation, we introduce X-HEEP's FEMU, an open-source platform designed to address these challenges. FEMU enables rapid prototyping of complete applications by leveraging hardware emulation and energy estimations, powered by an FPGA implementation of the open-hardware X-HEEP MCU. Our focus will be on showcasing the virtualization of an ADC (analog-to-digital converter) to evaluate acquisition applications. This demonstration allows real-time configuration of application, hardware, and software parameters, offering insights into latency issues and facilitating informed decision-making in the co-design process.

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