Artificial intelligence (AI) is clearly a transformative force reshaping our technological landscape and igniting a surge of interest in disruptive innovations across all levels of abstraction. As we stand on the brink of an AI revolution, the demand for advanced computing capabilities is skyrocketing. Yet, traditional memory solutions like on-chip SRAM and off-chip DRAM are struggling to keep up, creating a critical bottleneck that can impede the AI juggernaut. Imagine the possibilities if we could achieve over 100X improvements in memory density, bandwidth, latency, performance, and energy efficiency! This isn't just a dream—it's an urgent necessity for the future of AI. Enter ferroelectric devices, which hold incredible potential when co-optimized for key parameter indices (KPIs) across system, design, device, technology and materials. This talk will explore the exciting opportunities and formidable challenges that lie ahead as we transition from established memory devices, technologies and materials to novel ones. Join this journey as we envision a future where memory technology not only supports but accelerates the AI revolution!

Ferroelectric device has been widely investigated as a candidate to replace the charge trap device in NAND flash owing to its low operating voltage, high speed, and structural similarity to conventional cell. Moreover, it has potential to be utilized for the compute-in-memory applications targeting energy-efficient processing of ultra-large AI models. In this talk, the current device-level research progresses on ferroelectric NAND (FeNAND) will be presented briefly, then the array-level NAND cell simulator designed to assess the feasibility of ferroelectric cell will be introduced. Following this, its potential and applicability to compute-in-memory architectures will be discussed.

Perovskite-based Ferroelectric Random Access Memories (FeRAM) cannot scale beyond 130nm and offer poor CMOS compatibility. The discovery of hafnia-zirconia-based films changed FeRAM paradigm about 15 years ago.  This talk will cover HZO-based FeRAM demonstrations from 130nm down to 22nm node, highlighting the opportunities and challenges related to this promising technology.

Ferroelectric tunneling junctions (FTJ) are 2-terminal non-volatile memory devices, that consist of an active ferroelectric layer or multi-layer stack which is sandwiched between two metallic or semiconducting electrodes. In these devices the non-destructive read operation bases on the modulation of the tunneling current by the polarization state of the ferroelectric layer. Due to their high-impedance and rectifying properties FTJs are interesting candidates for the implementation of selector-less passive cross-bar arrays and for massive parallel readout for the realization of MVM in scalable selector-less passive cross-bar arrays. In this talk I will introduce the concept of the FTJ devices and discuss the prospects for their adoption in memory applications and beyond.

Ferroelectric Field-Effect Transistors (FeFETs) are a promising technology with immense potential for in-memory computing and AI acceleration. However, modeling their reliability remains a significant challenge due to multiple sources of variability. Design-time variability from process variations, run-time fluctuations driven by temperature effects, and the inherent stochasticity of ferroelectric domain switching—rooted in its probabilistic nature—make accurate reliability prediction highly complex. Without robust reliability models, it is impossible to ensure the accuracy and dependability of FeFET-based AI accelerator systems, which directly impacts the precision and effectiveness of AI algorithms. This talk presents a holistic framework for reliability estimation, seamlessly integrating insights from device physics to circuit-level analysis. We also highlight the transformative role of deep learning in addressing these challenges, demonstrating how it enables precise reliability modeling and unlocks the full potential of FeFET technology for next-generation computing.

This talk will discuss strategies to implement an accelerated discovery and codesign platform for efficient design and discovery of new ferroelectric materials and their properties in relevant devices. Achieving this goal requires moving beyond conventional, linear approaches to materials discovery, transforming them into a cyclic and iterative process integrating computation, experiment, and theory to formulate the processing-structure-property-performance relationships necessary to advance ferroelectric materials and devices. We will describe our progress in using machine learning to automate and accelerate materials characterization leading to adaptive learning for simulation and high-throughput synthesis and characterization.

Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly.  Ideally, any such comparisons should be made to state-of-the-art/scaled CMOS solutions in an application-level context.  In this presentation, students from SUPREME PI Michael Niemier’s group consider how ferroelectric-based associative memories may be employed for different workloads, and present layout-based analysis to show how said solutions may ultimately compare to highly scaled CMOS solutions across different figures of merit.  Directions and suggestions for future efforts at the algorithmic, layout/chip-design, and materials science-levels – to derive maximum benefits from technology – will also be briefly discussed.

Non-volatile ferroelectric capacitor (nvCap) that leverages the small-signal non-destructive read is a new concept to the ferroelectric memory family. nvCap overcomes the endurance limitation imposed by the destructive read in conventional ferroelectric random access memory (FeRAM) that relies on large-signal polarization switching.  nvCap is also a promising candidate to enable the charge domain computation in a capacitive crossbar array for in-memory computing that only consumes dynamic power.  The key engineering goal of nvCap is to optimize a asymmetric C-V characteristics to open up the large capacitance on/off ratio at DC zero voltage. In this talk, we present the progresses of our work on optimizing the nvCap device. We first introduce the HZO-based MFM nvCap that demonstrates the proof-of-concept, and present the FeFET-based MFS nvCap that improves capacitance on/off ratio with reliability/scaling analysis. Finally we report our new results on BEOL-compatible MFS nvCap based on a oxide semiconductor layer. 
 

This talk introduces the possibility of charge-domain computing using a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET). This cell operating in the charge domain is marking a significant advancement for compute-in-memory (CIM) which improves the energy efficiency but also robustness due to the low capacitor mismatch. Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.

Compute-in-Memory (CIM) is a promising non-von Neumann computing paradigm that promises unprecedented improvements in performance and energy efficiency. Moving past manual designs, automation will be key to unleash the potential of CIM for multiple application domains and to accelerate cross-layer design cycles. This talks reports on an ongoing effort to build a high-level compiler infrastructure for different CIM approaches, built with MLIR to abstract from individual technologies to foster re-use. This includes abstractions and optimizations flows for logic-in memory, content-addressable memories, arithmetic operations in crossbars, and near-memory architectures. We also report on recent results retargeting the compiler for novel ferroelectric cells, exploring different memory modalities.