DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.


W04 Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE 2021)

Friday, 5 February 2021 08:45
Friday, 5 February 2021 18:00
Important Dates
Submission Deadline
Notification of Acceptance
General Chair
Maksim Jenihhin, Tallinn University of Technology, Estonia
General Co-Chair
Anton Klotz, Cadence Design Systems, Germany
Program Chair
Matteo SONZA REORDA, Politecnico di Torino, Italy
Program Co-Chair
Marcelo Brandalero, Brandenburg University of Technology Cottbus–Senftenberg, Germany
Raphael Segabinazzi Ferreira, Brandenburg University of Technology Cottbus–Senftenberg, Germany
Troya Çağıl Köylü, Delft University of Technology, Netherlands
Dmytro Petryk, Innovations for High Performance Microelectronics (IHP), Germany
Aleksa Damljanovic, Politecnico di Torino, Italy
Felipe Augusto da Silva, Cadence Design Systems, Germany
Thomas Lange, iRoC Technologies, France
Keynote Speaker
Said Hamdioui, Delft University of Technology, Netherlands
Pieter Weckx, imec, Belgium
Steve Carlson, Cadence Design Systems, United States
Paul Duplys, Robert Bosch GmbH, Germany
Vladimir Herdt, University of Bremen, Germany
Muhammad Usama Sardar, Technische Universität Dresden, Germany
Buse Ustaoglu, DFKI GmbH, Germany
Luca Sterpone, Politecnico di Torino, Italy
Milos Krstic, IHP Microelectronics, Germany
Panel Chair
Giorgio Di Natale, Univ. Grenoble Alpes, France
Dan Alexandrescu, iROC Technologies, France
Jürgen Alt, Infineon, Germany
Marc Witteman, Riscure, Netherlands
Georgios Selimis, Intrinsic ID, Netherlands
Davide Appello, ST Microelectronics, Italy
Francky Catthoor, imec, Belgium
Zain Ul Abideen, Talinn , Estonia
Jan Reznicek, Czech Technical University in Prague, Czechia
Tiago Diadami Perez, Tallinn University of Technology, Estonia
Peter Langendörfer, IHP Microelectronics, Germany


Last updated: 04.02.2020

- Final program and proceedings are now live!

Overview of the RESCUE Workshop

The relationship between reliability, quality, and security is often conflicting: despite pursuing the same goal, i.e., the safe and correct operation of a computing system, they start from completely different assumptions. Quality and reliability address technical errors occurring during the design and manufacturing of the computing system and along its lifetime, while security aims at defeating malicious attempts of altering the normal behavior of the system. These design aspects set mutual constraints and contradicting requirements, nevertheless techniques from one discipline can be successfully applied to the other (e.g., fault tolerance to counteract fault injection attacks). Eventually, designers should guarantee the correct operation of the system, regardless of the origin of the malfunctioning, i.e. being it malicious or technical. In this context, it is essential that designers are aware of the complete picture, and that researchers from these interdependent disciplines meet and exchange ideas and challenges.

RESCUE 2021 is looking forward to novel ideas, overview, application, or position papers on the interdisciplinary nature of security, reliability, quality, testing, and verification -- you can find the call for contributions below! At least one author of an accepted paper is required to register for DATE’21.

The workshop will also present some of the methods, tools, architectures, and results achieved in the European Training Network RESCUE ( funded by the European Union H2020 Programme under the Marie Skłodowska-Curie Action.

Important dates

  • Submission deadline: January 8, 2021
  • Notification of acceptance: January 17, 2021
  • Virtual Event: February 5, 2021 (08:45 - 18:00)


The proceedings for the event can be downloaded via this password-protected link. The password will be shared with workshop participants on the day of the event.

08:45 - 09:00 Opening Session
09:00 - 09:40 Industrial Invited Talk 1 by Pieter Weckx, IMEC
09:40 - 11:10 Session "Reliability, Security and Quality"
    Coffee Break
11:20 - 12:00 Industrial Invited Talk 2 by Paul Duplys, Robert Bosch GmbH
    Lunch Break
13:00 - 13:40 Keynote by Said Hamdioui, TU Delft
13:40 - 15:10 RESCUE Project Research Highlights
    Coffee Break
15:20 - 16:00 Industrial Invited Talk 3 by Steve Carlson, Cadence Design Systems
    Coffee Break
16:10 - 17:40 Panel "Reliability, Security, and Quality: Will They Really Integrate?"
17:40 - 18:00 Closing Session
Technical Program

08:45 - 09:00: Opening Session

Opening Session - Maksim Jenihhin, Anton Klotz, Matteo Sonza Reorda, Marcelo Brandalero.


09:00 - 09:40: Industrial Invited Talk #1

Design Optimisation by Exploiting Workload Dependence of Aging.
Pieter Weckx, R&D Team Leader, IMEC, BE.

Session Chair: Marcelo Brandalero, Brandenburg University of Technology.

Abstract: Physical degradation mechanisms are an inevitable reality of real-world CMOS devices. They introduce a significant design challenge for IDMs, foundries, and fabless manufacturers. Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of environmental variations (Voltage, Temperature) and manufacturing process variations. On top of PVT variations, aging-related parametric drift (e.g. caused by NBTI, HCI, and EM) also limits performance by requiring additional margin. The industry adopted corner-based design paradigms involve applying margins that may be too optimistic or pessimistic and tends to ignore the correlation effects which exist inherently due to the circuit topology and the workload. In this talk we will discuss a workload-dependent, reliability aware design paradigm utilizing. Here an optimal margining scheme can be found which is determined by the system workload. The interdependence seen between system workloads and aging mechanisms is therefore exploited to achieve the desired Power-Performance-Area (PPA) goals at minimum reliability penalty.

Speaker Bio: Pieter Weckx received the B.Sc degree in Electronic Engineering,  M.Sc. degree in Nanoscience and –technology, and Ph.D. degree in Engineering from the Katholieke Universiteit Leuven - Belgium, in 2009, 2011, and 2016 respectively. In 2015 he joined imec as a researcher working on Design and System technology optimizations for advanced future scaled CMOS. Currently, he is R&D team leader of the circuit design and architecture team for technology explorations.


09:40 - 11:10: Session: Reliability, Security, and Quality

Session Chairs: Matteo Sonza Reorda, Politecnico di Torino & Marcelo Brandalero, Brandenburg University of Technology.


11:10 - 11:20: Coffee Break


11:20 - 12:00: Industrial Invited Talk #2

Automating Safety and Security from Chip to Cloud: Challenges and Opportunities.
        - Paul Duplys, Security, Privacy & Safety, Corporate Research, Robert Bosch GmbH

Session Chair: Luca Sterpone, Politecnico di Torino.

Abstract: The combination of ever-growing system complexity and connectivity being added to ever more devices led to a rapid attack surface increase, not only in automotive electronic systems. In a similar way, the introduction of open context systems like (highly) automated driving created new safety challenges resulting from a huge state space, a large number of corner cases, and a high rate of change. Contrary to the above developments, resources for either one, safety or security, remain largely unchanged. Nearly the same amount of security people need to guard a vastly larger attack surface and almost the same number of safety people need to tame a much higher complexity. As a result, automation becomes key for both safety and security. In this talk, I will cover both challenges and opportunities for automation in security and safety, from the chip to the cloud. I will cover challenges in different stages of the product life cycle and describe the opportunities offered by automation offers.

Bio: Paul Duplys is a security researcher and leads the security, privacy & safety research program at the Corporate Research division of Robert Bosch GmbH, a Tier-1 automotive supplier and manufacturer of industrial, residential, and consumer goods. He is doing applied research in various fields of information security since 2007. Paul's current research interests include security automation, software security, monitoring, intrusion detection & honeypots, threat intelligence, AI applications for security and security of AI, privacy engineering, privacy-preserving technologies, and edge & cloud security and safety. Paul holds a Ph.D. degree from the University of Tuebingen on side-channel evaluation for the automotive domain.


12:00 - 13:00: Lunch Break


13:00 - 13:40: Keynote

Re-Engineering Test and Reliability for Emerging Computing Technologies. 
      Said Hamdioui, TU Delft, NL.

Session Chair: Peter Langendörfer, IHP Microelectronics. 

Abstract: Emerging applications are extremely demanding in terms of storage, computing power, and energy efficiency. On the other hand, both today’s computer architectures and device technologies are facing major challenges making them incapable to deliver the required functionalities and features at an economically affordable cost. In order for computing systems to continue to deliver sustainable benefits for the foreseeable future society, alternative computing architectures are being explored in the light of emerging new device technologies. This calls for new methods to guarantee the outgoing product quality and reliability of such new computing engines. 

This talk first briefly addresses the need for a new computing paradigm with the energy efficiency of the order of fJ/operation to enable zillions of e.g., edge applications. Then, a classification of computing architectures is presented; and computation-in-memory as an alternative architecture is defined. Logic and arithmetic circuit designs using memristor devices and how they enable such architectures are briefly covered, and some data measurements are shown to demonstrate the CIM concept and its potential. Thereafter, testing of memristor-based CIM is discussed; it will be demonstrated that the traditional approach for fault modeling and test development is incapable to deal with realistic defects in emerging CIM devices, and a new approach called Device Aware Test (DAT) will be covered. Industrial data are presented to show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approaches. Moreover, reliability concerns of such computing engines will be discussed; these concerns can raise from the device nonidealities as well as from the characteristics of the employed circuit architecture. Finally, future CIM challenges including architectures, design, test, and reliability will be highlighted.

Bio: Said Hamdioui is currently the Head of the Quantum and Computer Engineering department, and serves as Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions. Said Hamdioui received the MSEE and Ph.D. degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Said Hamdioui worked at Intel Corporation (California, USA), at Philips Semiconductors R&D (Crolles, France), and at Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and computing paradigms, and hardware dependability. He published over 230 technical conference and journal papers on these topics. 

13:40 - 15:10: RESCUE Project Research Highlights

Session Chair: Maksim Jenihhin, Tallinn University of Technology

  • 13:40 - 13:55: Processor Behavior Under Faults. Troya Köylü*, Cezar Reinbrecht*, Marcelo Brandalero^, Said Hamdioui*, Mottaqiallah Taouil*.
    • * Delft University of Technology, Netherlands and ^ Brandenburg University of Technology, Germany.
  • 13:55 - 14:10: Run-time Dynamic Configuration of Functional Units Redundancy for Mixed-Critical Scenarios. Raphael Segabinazzi Ferreira, Jörg Nolte.
    • Brandenburg University of Technology, Germany.
  • 14:10 - 14:25: Radiation Hardness Does Not Mean Tamper Resistance. Dmytro Petrik, Zoya Dyka, Milos Krstic, Peter Langendörfer.
    • IHP – Leibniz-Institut für innovative Mikroelektronik, Germany.
  • 14:25 - 14:40: AutoSoC: A Suite of Open-Source Automotive SoC Benchmarks. Felipe Augusto da Silva*^, Ahmet Cagri Bagbaba*, Said Hamdioui^, Christian Sauer*
    • Cadence Design Systems, DE and ^ Delft University of Technology, Netherlands.
  • 14:40 - 14:55: IEEE 1687 IJTAG - Interdependent Aspects of Quality and Reliability. Aleksa Damljanovic, Giovanni Squillero
    • Politecnico di Torino, Italy.
  • 14:55 - 15:10: Machine Learning to Tackle the Challenges of Soft Errors in Complex Circuits. Thomas Lange*^, Aneesh Balakrishnan*+, Dan Alexandrescu*, Luca Sterpone^.
    • * iRoC Technologies, France and ^ Politecnico di Torino, Italy and + Tallinn University of Technology, Estonia.


15:10 - 15:20: Coffee Break


15:20 - 16:00: Industrial Invited Talk #3

PPA, Reliability, Security, and Quality: They Have to Integrate!
Steve Carlson, Director/Solution Architect Aerospace and Defense, Cadence Design Systems San José, US.

Session Chair: Milos Krstic, IHP Microelectronics.

Abstract: The limits of siloed, serially applied expertise are being reached. To wring the most out of today's silicon process technologies that serve more complex markets with multi-factor value points,  PPA, Reliability, Security, and Quality must be addressed earlier in the design process, and in a manner where the effects of pushing on one axis can be measured and weighed against the other axes. In this talk, a methodology is proposed to open the door and provide a path to a holistic approach to an integrated view of PPA, Reliability, Security, and Quality.

Speaker Bio: A thirty-year veteran of the electronics industry, Steve has been focused on Aerospace and Defense system solutions for the past six years. His current research interests are in hardware and system security, systems verification, digital twinning, advanced semiconductor design processes, and approaches to parts obsolescence. Prior, Steve headed marketing Chief Strategy Office and for the Silicon Realization Group which included the digital, custom/analog, and sign-off products. Steve joined Cadence in April 2003 via the Get2Chip acquisition, where he was the VP of Marketing. Prior to Get2Chip, Steve was the CEO of Tharas Systems, a hardware acceleration company. Steve has also held various management positions at Escalade, LSI Logic, United Technologies, and Synopsys.

At Synopsys, Steve was a part of the original Design Compiler technical team responsible for timing analysis and optimization. Steve was the author of the industry’s first book on high-level design titled, “Introduction to HDL-based Design Using VHDL”. Steve earned a BSEE, BSCS, and an MSEE from the University of Colorado. He has authored numerous books, papers, articles related to advanced electronics design. Steve is a volunteer and supporter of the Lazarex Cancer Foundation (


16:00 - 16:10: Coffee Break


16:10 - 17:40: Panel

Reliability, Security, and Quality: Will They Really Integrate?

Moderator: Giorgio di Natale, Director of Research - CNRS. LIRRM, Montpellier, FR.


  • Dan Alexandrescu, IROC, FR
  • Davide Appello, ST Microelectronics, IT
  • Francky Catthoor, IMEC, BE
  • Georgios Selimis, Intrinsic ID, FR
  • Jürgen Alt, Infineon, DE
  • Marc Witteman, Riscure, NL
  • Paul Duplys, Bosch, DE
  • Steve Carlson, Cadence Design Systems, US


17:40 - 18:00: Closing Session

Closing Session - Maksim Jenihhin, Anton Klotz, Matteo Sonza Reorda, Marcelo Brandalero.

Call for Contributions

RESCUE 2021 is looking forward to novel ideas, overview, application, or position contributions on topics including, but are not limited to:

  • design methods and tools for reliable, secure, and high-quality systems;
  • adaptive techniques for improving reliability and security;
  • HW/SW co-design towards reliability, security, and quality;
  • test, reliability, security, and verification of emerging technologies;
  • self-aware systems for improved reliability and security.

Submissions for technical presentations can be in the form of abstracts (2 pages) or full papers (4-6 pages) prepared according to the IEEE format and submitted via EasyChair. Accepted contributions will be distributed among the workshop participants. At least one author of an accepted paper is required to register for the workshop.

Organizing Committee

General Chairs

  • Maksim Jenihhin, Tallin UT, EE
  • Anton Klotz, Cadence, DE

Program Chairs

  • Matteo Sonza Reorda, POLITO, IT
  • Marcelo Brandalero, BTU, DE

Program Committee

  • D. Alexandrescu, IROC, FR
  • Z. Dyka, IHP, DE
  • M. Glorieux, IROC, FR
  • S. Hamdioui, TU Delft, NL
  • M. Huebner, BTU, DE
  • M. Krstic, IHP, DE
  • P. Langendoerfer, IHP, DE
  • J. Nolte, BTU, DE
  • J. Raik, Tallinn UT, EE
  • C. Sauer, Cadence, DE
  • G. Selimis, IID, NL
  • G. Squillero, POLITO, IT
  • L. Sterpone, POLITO, IT
  • M. Taouil, TU Delft, NL
  • H.T. Vierhaus, BTU, DE


Flag of the European Union. The RESCUE ETN project has received funding from the European Union’s Horizon 2020 Programme under the Marie Skłodowska-Curie actions for research, technological development and demonstration, under grant no. 722325.