In preparations for DATE 2021, the Organizing Committees will continue to closely monitor the development of the worldwide Covid-19 situation and adjust the conference format accordingly. Updated information will always be available on this page.

W02 Computation-In-Memory (CIM): from Device to Applications

Friday, 13 March 2020 08:30
Friday, 13 March 2020 17:00
Important Dates
Submission Deadline

Aim of the Conference: All issues with which the architectures and technologies are face today have led to the slowdown of the traditional device scaling. In order for computing systems to continue deliver sustainable benefits for the foreseeable future, alternative computing architectures and notions have to be explored in the light of emerging new device technologies. This workshop aims at providing a forum to discuss Computation-in-Memory (as an alternative architecture) in the light of emerging non-volatile devices (such as RRAM, PCM and STT-MRAM), and its potential applications. It also aims at reinforcing the CIM community and at offering a holistic vision of this emerging computing paradigm to the electronic design, automation and test communities.

The authors of accepted papers will be invited to submit an extended version of their work to the Special Issue of ACM Journal of Emerging Technologies in Computing.  

The workshop covers all aspects of CIM based on non-volatile devices including (but not limited to):

  • Device and technology: physics and modeling, device technologies, device characterization.
  • Novel logic and circuit design concepts using NV devices: Boolean logic, threshold logic, arithmetic circuits, multi-level based logic, memories, PUF technology, TRNG design.
  • System architectures and new computing paradigms: resistive computing, neuro-inspired computing, novel architectures and CMOS integration, cellular automata and array computing.
  • Applications exploiting NV devices: signal processing, chaos and complex networks, sensors applications, AI applications.
  • Automation and CAD tools: mapping tools, compilers, logic synthesis tools, design space exploration tools.
  • Test and Reliability: test and reliability solutions for circuits and architectures.

The workshop will be co-located with the DATE 2021 conference. At least one author of each accepted paper is expected to register to the workshop using DATE’s regular registration system. 

Opening Session Keynote Address

Session Start
Fri, 08:30
Session End
Fri, 09:30
Opening Session

Alberto Bosio (INL, France), Said Hamdioui (TUDelft, The Netherlands), Elena-Ioana Vatajelu (TIMA, France)

Keynote Address

To be announced

Invited Talk Invited Talk

Session Start
Fri, 09:30
Session End
Fri, 10:00

Panel Computation-In-Memory (CIM): from Device to Applications

Session Start
Fri, 10:30
Session End
Fri, 12:00

Panelists (preliminary list):

  • Henri-Pierre Charles (CEA-Leti, FR)
  • Shahar Kvatinsky (Technion, Israel)
  • Alexandre Levisse (EPFL, CH)
  • Georgios Sirakoulis (University of Thrace, GR)

Session Scientific Presentations

Session Start
Fri, 13:00
Session End
Fri, 14:30
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks 

Gokul Krishnan*, Sumit K. Mandal*, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, Yu Cao (School of Electrical, Computer and Energy Engineering, Arizona State University)

Conversion-in-Memory Using Floating-Gate Memristive Neural Networks

Loai Danial, Shahar Kvatinsky (Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology)

Exact Stochastic Computing Multiplication in Memristive Memory

Mohsen Riahi Alam, M. Hassan Najafi (University of Louisiana at Lafayette, Louisiana, USA), Nima TaheriNejad (TU Wien, Vienna, Austria)

Efficient 8-bit matrix multiplication on Computational SRAM architecture

Mambu Kévin, Charles Henri-Pierre, Kooli Maha (Université Grenoble Alpes, CEA LIST, F-38000 Grenoble, France)

Session Scientific Presentations

Session Start
Fri, 15:00
Session End
Fri, 17:30
​​​​​​Simulation and experimental characterization of memristive crossbar arrays for computation-in-memory

J. Mohr, C. Bengel, M. Abu, S.Hamdioui, D.J. Wouters, S. Menzel, R. Waser

Sensing and Processing in Memristive Arrays

Saurabh Khandelwal (School of ECM, Oxford Brookes University, Oxford), Shahar Kvatinsky (Viterbi Faculty of Electrical Engg., Technion - Israel Institute of Technology), Marco Ottavi, Eugenio Martinelli (Electronic Engg., University of Rome “Tor Vergata”, Rome, Italy), Abusaleh Jabir (School of ECM, Oxford Brookes University, Oxford)

Exploration of a Scalable Vector-Tile-based In-Memory Computing Architecture

Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noel, Bastien Giraud, Pascal Vivet (Université Grenoble Alpes, CEA LIST, Grenoble, France), Subhasish Mitra (Stanford University, Palo Alto, CA, USA), Henri-Pierre Charles (Université Grenoble Alpes, CEA LIST, Grenoble, France)

Reuse-aware architecture and synthesis flow for NVM-based FPGAs

João Paulo Cardoso de Lima, Rafael Fão de Moura, Luigi Carro (Departamento de Informática Aplicada Instituto de Informática - UFRGS)

Toward CIM architecture with a new tile-level simulator

Mahdi Zahedi, Stephan Wong, Said Hamdioui (Computer Engineering Laboratory, Delft University of Technology, The Netherlands)

Control, instruction set for memristor-based CIM