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W02 3D Integration: Heterogeneous 3D Architectures and Sensors

Start
Wednesday, 19 April 2023 14:00
End
Wednesday, 19 April 2023 18:00
Room
Nightingale Room 2.6.1/2
Organiser
Pascal VIVET, CEA, LIST, France
Organiser
Peter Ramm, Fraunhofer EMFT, Germany
Organiser
Mustafa Badaroglu, QUALCOMM, United States
Organiser
Subhasish Mitra, Stanford University, United States
URL
https://easychair.org/conferences?conf=date233dws

Workshop Description

3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.

The 3D Integration Workshop took place in DATE conference from 2009 to 2015 and took place again in 2022. With the continued evolution of 3D technologies in terms of interconnect density and its evolving manufacturing eco-system, there is a strong need to pursue the research efforts on key aspects of architecture and design, according to the potential capabilities offered by 3D integration.

The goal of the 3D Integration Workshop is to bring together experts from both academia and industry, interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

This half-day event consists of a plenary keynote, invited talks, and regular presentations

 

Technical Program

Tentative schedule, under construction

Keynote

Session Chair : Peter Ramm, Fraunhofer, Germany

14:00 – 14:30    Chiplets for AI – AI for chiplets

                        Paul Franzon, North Carolina State University, USA

Session 1 : Chiplet based systems

14:30 – 14:45    Occamy - A 432-core RISC-V Based 2.5D Chiplet System for Ultra-Efficient (Mini) Floating-Point Computation

                        Gianna Paulin, ETH-Z, Switzerland.

14:45 – 15:00    Toward industrialization of 2.5D/3D heterogeneous solutions for ASICs

                        Fady Abouzeid, Philippe Roche, STMicroelectronics, France.

15:00 – 15:15     (TBD)

                        Michael Fischer, Fraunhofer, IZM, Dresden, Germany

15:15 – 15:30    Energy-Efficient Communication in 2.5D Integrated Systems

                        Vasilis F. Pavlidis, Aristotle University of Thessaloniki, Greece.

15:30 – 16:15    Coffee Break

 

Session 2 : Advanced 3D architecture and design methodology

16:15 – 16:30    Temperature-Aware Design of 3D-Stacked Accelerators

                        Ayse K. Coskun,  Boston University, USA.

16:30 – 16:45    Thermally aware 3D sign-off and design enablement of 3-dies stack

                        Mohamed Naeim and Dragomir Milojevic, IMEC, UBL, Belgium

16:45 – 17:00     3D Integration and Advanced Packaging for Modular Quantum Computer based on Diamond Spin Qubits  

                        Ishihara Ryoichi, TU Delft, Nederlands

17:00 – 17:15    Efficient In Sensor processing based on advanced 3D technologies        

                        Sébastien Thuriès, CEA List, France

17:15 – 17:30    Why Advanced Packaging & 3D Integration Does Matter to Everybody

                        Anna Fontanelli, Monozukuri SpA, Rome, Italy

17:30 – 17:45    Integrating Fault Tolerance for 2.5D/3D Chiplets Using the Advanced Interface Bus (AIB)

                        Antoine Rouget, STMicroelectronics / CEA, LIST, Grenoble, France

17:45 – 18:00    Efficient and Reliable Hardware Architectures based on Vertical Nanowire FETs

                        Bastien Deveautour, Institute of Nanotechnology (INL), France

 

Key Dates

Abstract Submission deadline 22 January 2023 => extended 17 February 2023
Notification of Acceptance 5 February2023 => extended 24 February 2023
Presentations and posters ready 26 March 2023
Workshop Wednesday, 19 April 2023 - 14:00 - 18:00

 

Workshop Committee

  • General co-Chairs:
    • P. Vivet – CEA-LIST, IRT Nanoelec (FR)
    • M. Badaroglu, Qualcomm, (BE)
  • Program Chair:
    • P. Ramm, Fraunhofer EMFT (GE)
  • Special Session Chair
    • S. Mitra, Stanford University (USA)
  • Industrial Liaison Chair
    • Eric Ollier, CEA-Leti, IRT Nanoelec (FR)

 

Past editions

The 3D Integration workshop took place from 2009 to 2015 and was restarted in 2022.