- DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)
Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.
The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.
IP5_1 Interactive Presentations
Date: Wednesday, 03 February 2021
Time: 10:30 - 11:00
Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session
|IP5_1.1||EXPLORING MICRO-ARCHITECTURAL SIDE-CHANNEL LEAKAGES THROUGH STATISTICAL TESTING
Sarani Bhattacharya, KU Leuven, BE
Sarani Bhattacharya1 and Ingrid Verbauwhede2
1Phd, BE; 2KU Leuven - COSIC, BE
Micro-architectural side-channel leakage received a lot of attention due to their high impact on software security on complex out-of-order processors. These are extremely specialised threat models and can be only realised in practise with high precision measurement code, triggering micro-architectural behavior that leaks information. In this paper, we present a tool to support the inexperienced user to verify his code for side-channel leakage. We combine two very useful tools- statistical testing and hardware performance monitors to bridge this gap between the understanding of the general purpose users and the most precise speculative execution attacks. We first show that these event counters are more powerful than observing timing variabilities on an executable. We extend Dudect, where the raw hardware events are collected over the target executable, and leakage detection tests are incorporated on the statistics of observed events following the principles of non-specific t-test's. Finally, we show the applicability of our tool on the most popular speculative micro-architectural and data-sampling attack models.
|IP5_1.2||SECLUSIVE CACHE HIERARCHY FOR MITIGATING CROSS-CORE CACHE AND COHERENCE DIRECTORY ATTACKS
Vishal Gupta, Indian Institute of Technology, Kanpur, IN
Vishal Gupta1, Vinod Ganesan2 and Biswabandan Panda3
1Indian Institute of Technology, Kanpur, IN; 2Indian Institute of Technology Madras, IN; 3IIT Kanpur, IN
Cross-core cache attacks glean sensitive data by exploiting the fundamental interference at the shared resources like the last-level cache (LLC) and coherence directories. Complete non-interference will make cross-core cache attacks unsuccessful. To this end, we propose a seclusive cache hierarchy with zero storage overhead and a marginal increase in on-chip traffic, that provides non-interference by employing cache-privatization on demand. Upon a cross-core eviction by an attacker core at the LLC, the block is back-filled into the private cache of the victim core. Our back-fill strategy mitigates cross-core conflict based LLC and coherence directory-based attacks. We show the efficacy of the seclusive cache hierarchy by comparing it with existing cache hierarchies.