- DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)
Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.
The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.
IP1_1 Interactive Presentations
Date: Tuesday, 02 February 2021
Time: 09:50 - 10:20
Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session
|IP1_1.1||PARAMETRIC THROUGHPUT ORIENTED LARGE INTEGER MULTIPLIERS FOR HIGH LEVEL SYNTHESIS
Emanuele Vitali, Politecnico di Milano, IT
Emanuele Vitali, Davide Gadioli, Fabrizio Ferrandi and Gianluca Palermo, Politecnico di Milano, IT
The multiplication of large integers represents a significant computation effort in some cryptographic techniques. The use of dedicated hardware is an appealing solution to improve performance or efficiency. We propose a methodology to generate throughput oriented hardware accelerators for large integers multiplication leveraging High-Level Synthesis. The proposed micro-architectural template is composed of a combination of different multiplication algorithms. It exploits the recursive splitting of Karatsuba, reuse strategies, and the efficiency of Comba to control the extra-functional properties of the generated multiplier. The goal is to enable the end-user to explore a wide range of possibilities, in terms of performance and resource utilization, without requiring them to know implementation and synthesis details. Experimental results show the large flexibility of the generated architectures and that the generated Pareto-set of multipliers can outperform some state-of-the-art RTL design.
|IP1_1.2||LOCKING THE RE-USABILITY OF BEHAVIORAL IPS: DISCRIMINATING THE SEARCH SPACE THROUGH PARTIAL ENCRYPTIONS
Zi Wang, University of Texas at Dallas, US
Zi Wang and Benjamin Carrion Schaefer, University of Texas at Dallas, US
Behavioral IPs (BIPs) have one salient advantage compare to the traditional RTL IPs given in Verilog or VHDL or even gate netlists. The BIP can be used to generate RTLs with very different characteristics by simply specifying different synthesis directives. These synthesis directives are typically specified at the source code in the form of pragmas (comments) and control how to synthesize arrays (e.g. registers or RAM), loops (unroll or fold) and functions (inline or no). This allows a BIP consumer to purchase a BIP once and re-use it in future projects by simply specifying a different mix of these synthesis directives. This would obviously not benefit the BIP provider as the BIP consumer would not need to purchase the BIP again for future projects as oppose to IPs bought at the RT or gatenetlist level. To address this, this work presents a method to enable the BIP provider to lock the search space of the BIP such that the user can only generate micro-architectures within the specified search space. This leads to a significant benefit to both parties: The BIP provider can now discriminate the BIP price based on how much of the search space is made visible to the BIP consumer, while the BIP consumer benefits from a cheaper BIP, albeit limited in its search space. This approach is made possible through partial encryptions of the BIP. Thus, this work presents a method that selectively fixes some synthesis directives and allows the BIP user to modify the rest of the directives such that the micro-architectures generated are guaranteed to be in a given pre-defined search space limit.