2.1 Emerging trends in the HPC industry landscape

Date: Tuesday, 02 February 2021
Time: 16:00 - 17:30 CET
Virtual Conference Room: https://virtual21.date-conference.com/meetings/virtual/y3tu535LC2J2NARwr

Session chair:
Nehir Sonmez, BSC, ES

Session co-chair:
Miquel Moreto, BSC, ES

Organizers:
Gilles Sassatelli, LIRMM, FR
Miquel Moreto, BSC, ES

The hardware HPC landscape is rapidly changing with novel players challenging decade-long installed architectures and technologies. This session will shed light on the emerging trends through 3 contributions that will discuss the momentum around the RISC-V ecosystem and the emergence of tools for enabling its use in HPC environment, the European Mont-Blanc strategy and academia-industry partnership that is about to give birth to a European processor architecture.

Time Label Presentation Title
Authors
16:00 CET 2.1.1 TRENDS IN HPC DRIVEN BY THE RACE TO EXASCALE
Speaker and Author:
Craig Prunty, SiPEARL, FR
Abstract
HPC in Europe (and worldwide) is pushing to rapidly to exascale, where exascale is defined by double precision Linpack score. This push for performance, while remaining within cost and power consumption envelopes, and the need to support a wide variety of workloads is enforcing a diversion in processing elements, CPU and accelerators. CPU provide general processing capability across the bulk of workloads, with a focus in HPC toward balanced compute and memory bandwidth, demonstrated by HPCG performance. Accelerators are pushing the envelope on vector processing, with high Linpack scores, and also offer a platform for AI. This is leading to some interesting trends in HPC, including Modular system architectures, tight coupling between accelerators and general purpose processors, and the emergence of AI to address some of the Exascale challenges.
16:20 CET 2.1.2 COYOTE: AN OPEN SOURCE SIMULATION TOOL TO ENABLE RISC-V IN HPC
Speaker:
Borja Perez, Barcelona Supercomputing Center, ES
Authors:
Borja Perez, Alexander Fell and John Davis, Barcelona Supercomputing Center, ES
Abstract
The confluence of technology trends and economics has reincarnated computer architecture and specifically, software-hardware co-design. We are entering a new era of a completely open ecosystem, from applications to chips and everything in between. The software-hardware co-design of supercomputers for tomorrow requires flexible tools today that will take us to the Exascale and beyond. The MareNostrum Experimental Exascale Platform (MEEP) addresses this by proposing a flexible FPGA-based emulation platform, designed to explore hardware-software co-designs for future RISC-V supercomputers. This platform is part of an open ecosystem, allowing its infrastructure to be reused in other projects. MEEP’s inaugural emulated system will be a RISC-V based self-hosted HPC vector and systolic array accelerator, with a special aim at efficient data movement. Early development stages for such an architecture require fast, scalable and easy to modify simulation tools, with the right granularity and fidelity, enabling rapid design space exploration. Being a part of MEEP, this paper introduces Coyote, a new open source, execution-driven simulator based on the open source RISC-V ISA and which can provide detailed results at various levels and granularities. Coyote focuses on data movement and the modelling of the memory hierarchy of the system, which is one of the main hurdles for high performance sparse workloads, while omitting lower level details. As a result, performance evaluation shows that Coyote achieves an aggregate simulation of up to 5 MIPS when modelling up to 128 cores. This enables the fast comparison of different designs for future RISC-V based HPC architectures.
16:40 CET 2.1.3 MONT-BLANC 2020: TOWARDS SCALABLE AND POWER EFFICIENT EUROPEAN HPC PROCESSORS
Speaker:
Said Derradji, Atos, FR
Authors:
Adrià Armejach1, Bine Brank2, Jordi Cortina3, François Dolique4, Timothy Hayes5, Nam Ho2, Pierre-Axel Lagadec6, Romain Lemaire4, Guillem Lopez-Paradis7, Laurent Marliac6, Miquel Moreto7, Pedro Marcuello3, Dirk Pleiter2, Xubin Tan3 and Said Derradji6
1BSC & UPC, ES; 2Forschungszentrum Juelich, Juelich Supercomputing Centre, DE; 3Semidynamics Technology Services, ES; 4CEA-Leti, FR; 5Arm, GB; 6Atos, FR; 7BSC, ES
Abstract
The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European processor for exascale, defining the System-on-Chip (SoC) architecture and implementing new critical building blocks to be integrated in such an SoC. In this paper, we first present an overview of the MB2020 project, then we describe our experimental infrastructure, the requirements of relevant applications, and the IP blocks developed in the project. Finally, we present our emulation-based final demonstrator and explain how it integrates within our first generation of HPC processors.
17:00 CET 2.1.4 LIVE JOINT Q&A
Authors:
Nehir Sonmez1, Miquel Moreto1, Craig Prunty2, Borja Perez1 and Said Derradji3
1BSC, ES; 2SiPEARL, FR; 3Atos, FR
Abstract
30 minutes of live joint question and answer time for interaction among speakers and audience.