DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

DATE 2021 Programme on Tuesday

Slot 07:00 - 07:50 07:50 - 08:40 08:50 - 10:20 08:50 - 09:50 08:50 - 09:40 09:50 - 10:20 10:20 - 11:00 15:00 - 15:50 16:00 - 16:50 16:00 - 17:30 16:00 - 17:00 17:00 - 17:30 17:30 - 18:20 17:30 - 19:00 17:30 - 18:30 18:30 - 19:00
Slot 1
O.1 Opening K.1 Opening Keynote 1.1 Innovative technologies & architectures for tomorrow’s compute platforms 2.1 Emerging trends in the HPC industry landscape 3.1 Sustainable solutions at large: bettering energy efficiency in HPC
Slot 2
1.2 IT Sustainability (Embedded tutorials) K.2 Opening Keynote 2.2 3D integration: Today's practice and road ahead 3.2 Journey with Emerging Technologies and Architectures from Devices to System-Level Management
Slot 3
1.3 The Road Towards Predictable Automotive High-Performance Platforms K.3 Keynote - Special day on sustainable HPC 2.3 A Deep Dive into Future of Lightweight Cryptography: New Standards, Optimizations, and Attacks 3.3 Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Slot 4
1.4 HLS: from hardware optimization to security 2.4 Quantum Computing 3.4 Advances with Emerging Technologies: Biochips, Memory-Centric Computing, and Ion Trap Quantum Architectures
Slot 8
1.8 Industrial Design Methods and Tools: Future EDA Applications and Thermal Simulation for 3D 2.8 Exhibition Keynote on Digital Twins and Invitation to Become a Book Author 3.8 Industrial Design Methods and Tools: RISC-V
Slot 5
1.5 Adaptive and Learning Systems 2.5 Platform validation with simulation 3.5 Regularity and Optimization for Logic Synthesis
Slot 6
1.6 Soft error vulnerability analysis and mitigation, and hotspot identification 2.6 Hardware architectures for neural network applications with emerging technologies 3.6 RF and High-Speed design challenges
Slot 7
1.7 Novel Compilation Flows for Performance and Memory Footprint Optimization 2.7 Scheduling and Execution Time Variation 3.7 Lightweight Machine Learning at the Edge
Slot IP1_1
IP1_1 Interactive Presentations
Slot IP1_2
IP1_2 Interactive Presentations
Slot IP1_3
IP1_3 Interactive Presentations
Slot IP1_4
IP1_4 Interactive Presentations
Slot 01
UB.01 University Booth
Slot 02
UB.02 University Booth
Slot IP2_1
IP2_1 Interactive Presentations
Slot IP2_2
IP2_2 Interactive Presentations
Slot 03
UB.03 University Booth
Slot 04
UB.04 University Booth
Slot 05
UB.05 University Booth
Slot 06
UB.06 University Booth
Slot IP3_1
IP3_1 Interactive Presentations
Slot IP3_2
IP3_2 Interactive Presentations
Slot IP3_3
IP3_3 Interactive Presentations
Slot IP3_4
IP3_4 Interactive Presentations
Slot 08
UB.08 University Booth
Slot 09
UB.09 University Booth
Slot 10
UB.10 University Booth