Slot 6
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9.6 System-level Security |
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10.6 Smart Cities, Internet of Everything, Smart Consumer Electronics |
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11.6 Timing and Reconfigurable Logic |
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12.6 Attacks and defense mechanisms |
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13.6 Non-volatile memories, an enabler for highly efficient AI computing |
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Slot 1
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9.1 Autonomous Systems Design: Opening Panel |
10.1 Reliable Autonomous Systems: Dealing with Failure & Anomalies |
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11.1 Safety Assurance of Autonomous Vehicles |
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12.1 Designing Autonomous Systems: Experiences, Technology and Processes |
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13.1 Predictable Perception for Autonomous Systems |
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C.1 Closing |
Slot 2
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9.2 IP Protection |
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10.2 Multi-Partner Innovative Research Projects |
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11.2 Executive track: Silicon Photonics & Optical Computing |
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12.2 When FPGA Turns Against You: Side-Channel and Fault Attacks in Shared FPGAs |
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13.2 Hardware-based Malware Detectors: A Special Session on Embedded Security |
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Slot 3
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9.3 Heterogeneous Architectures and Design Space Exploration |
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10.3 Hardware-aware Training |
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11.3 Trust in Manufacturing |
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12.3 Emerging in memory computing paradigms |
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13.3 High Performance and Energy Efficiency: Microarchitecture to the rescue |
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Slot 4
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9.4 Analog layout conquers new frontiers |
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10.4 EDA tools: the next generation |
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11.4 Techniques for Low-Latency Neural Network Inference |
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12.4 NoC looking for higher performance |
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13.4 Machine Learning for Physical Design: It’s Never Too Late |
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Slot 5
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9.5 Energy-Efficient and Thermal Aware Systems for Machine Learning |
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10.5 Coarse Grained Reconfigurable Architectures |
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11.5 Approximate arithmetic and synthesis |
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K.5 Keynote - Special day on ASD |
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12.5 Intelligent Resource Optimization and Prediction for Power Management |
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13.5 Accelerating Clustering and Machine Learning Algorithms for Large Amounts of Data |
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Slot 7
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10.7 Software and architectural techniques for dependability |
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11.7 Artificial Intelligence and Fault Injection in Test |
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12.7 Advancement in modelling of defects and yield in memories. |
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13.7 Advancements in embedded and cyber-physical systems design |
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Slot ASD_1
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IP.ASD_1 Interactive Presentations |
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Slot IP8_1
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IP8_1 Interactive Presentations |
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Slot IP8_2
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IP8_2 Interactive Presentations |
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Slot IP8_3
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IP8_3 Interactive Presentations |
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Slot IP8_4
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IP8_4 Interactive Presentations |
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Slot IP8_5
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IP8_5 Interactive Presentations |
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Slot IP8_6
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IP8_6 Interactive Presentations |
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Slot 8
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11.8 Industrial Design Methods and Tools: Neural Network Design |
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12.8 Career forum: YPP panel |
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13.8 Career Forum: Which career path to take: SWOT analysis |
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Slot IP9_1
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IP9_1 Interactive Presentations |
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Slot IP9_2
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IP9_2 Interactive Presentations |
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Slot IP9_3
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IP9_3 Interactive Presentations |
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Slot IP9_4
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IP9_4 Interactive Presentations |
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Slot IP9_5
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IP9_5 Interactive Presentations |
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Slot IP9_6
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IP9_6 Interactive Presentations |
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Slot IP9_7
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IP9_7 Interactive Presentations |
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Slot W03-P1
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W03-P1 Cadence - BTU - Europractice Workshop - Generation and Implementation of an industry-grade ASSP core (Part 1) |
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Slot 20
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UB.20 University Booth |
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Slot 21
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UB.21 University Booth |
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Slot ASD_2
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IP.ASD_2 Interactive Presentations |
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Slot IP10_1
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IP10_1 Interactive Presentations |
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Slot IP10_2
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IP10_2 Interactive Presentations |
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Slot MPIRP_1
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IP.MPIRP_1 Interactive Presentations |
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Slot MPIRP_2
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IP.MPIRP_2 Interactive Presentations |
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Slot YPP
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EXTH_K.YPP YPP Keynote |
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Slot 22
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UB.22 University Booth |
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Slot 23
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UB.23 University Booth |
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Slot 24
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UB.24 University Booth |
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Slot IP11_1
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IP11_1 Interactive Presentations |
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Slot IP11_2
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IP11_2 Interactive Presentations |
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Slot IP11_3
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IP11_3 Interactive Presentations |
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Slot IP11_4
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IP11_4 Interactive Presentations |
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Slot REC
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ASD.REC ASD Reception |
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