DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

Defacto Technologies

Defacto Technologies
Contact Person
Chouki Aktouf

155-157 cours Berriat
38028 Grenoble

Defacto Technologies is a chip design software company providing breakthrough RTL design platforms to enhance integration, verification and Signoff of IP cores and System on Chips.

By adopting Defacto’s STAR SoC design solutions, major semiconductor companies are significantly reducing design engineering cost and getting better PPA (Power Performance Area) results. The related ROI has been proven for hundreds of projects.

Headquartered in the French Alps with a US branch in California, Defacto has today a worldwide presence with a 24/7 support all over the world.

STAR - RTL Build&Signoff Design solutions for complex SoC

Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff design process which opens new SoC integration and design optimization capabilities before and after logic synthesis.

STAR helps to face challenges of moving to sophisticated RTL coding styles like with System Verilog and manage into a unified automated design flow RTL and the variety of multi-domain design standards:

  • Architectural design formats such as IPXACT
  • Power intent such as UPF
  • Timing constraints such as SDC
  • Physical design information such as LEF/DEF
  • Design Libraries such as Liberty, etc.

Typical Applications

SoC Integration

  • Multi-format IP Insertion
  • Automate connectivity insertion
  • Monitor SoC integration progress real-time
  • Generate full chip views based on specification file

Design Optimization

  • Layout density improvement
  • Optimize logic structures
  • Hierarchical manipulation based on floorplan changes
  • Automatic feedthrough insertion

Design Verification

  • Simulation-free connectivity checks under constraints
  • RTL vs. libraries: SDC, liberty & UPF, IPXACT, LEF
  • Push-button flow for IP DFT Signoff