Welcome to DATE 2026

The AI field is evolving at an incredibly fast pace, with major models and updates being released almost every month. As these models evolve beyond Large Language Models towards next-gen AI with advanced reasoning capabilities, compute systems struggle to handle the heterogeneous workloads in a performant and sustainable way. However, developing new, AI-optimized compute architectures and the enabling semiconductor technologies takes much more time than writing algorithms. To prevent bottlenecks slowing down AI-based advancements, we must reinvent compute architectures and semiconductor technology platforms.

The presentation will shed light on the need for flexible, versatile compute architectures implemented in flexible, versatile technology platforms while addressing the increasing challenges of density, power and memory. To speed up both advanced semiconductor technology R&D and full stack innovation for future AI applications, imec is expanding its pilot line infrastructure under the EU Chips Act. Next to new infrastructure, imec aims to boost innovation through intensified collaborations with complementary knowledge partners and through further internationalization, attracting global talent and building strong, local ecosystems for diverse application domains, like health and automotive.

Transformative innovations for humankind hinge on the innovation pace of the semiconductor industry. It’s time to supercharge our innovation engine, it’s time to futureproof our prosperity.

Quantum computing is one of the most promising technologies of our era. The fundamentally different nature of quantum processors (QPUs) requires a highly interdisciplinary effort to tackle challenges across the entire system to effectively leverage quantum resources. To realize the commercial potential of quantum acceleration, significant HPC resources are required to accelerate workloads necessary to the operation of a QPU. These workloads involve tasks related to quantum error correction, system calibration, and optimal control, and hence require and ultra-low latency exchange between the quantum system controllers (QSCs) and traditional processors such as GPUs.

Introducing a tight coupling between HPC and QPU environment presents a number of challenges that have become a focus within the quantum-HPC community.

Most QSCs are implemented using FPGAs or RFSoC devices, which run a firmware-defined pulse processor unit (PPU). Connecting the QSC via PCIe card can enable direct communication but poses scaling challenges. A potentially preferable alternative that offers better options for distribution is the use of a network interface card (NIC) for connection via Ethernet or InfiniBand.

In this talk I will discuss NVIDIA's effort to facilitate the development of advanced QPUs using real-time processing on GPUs using the NVQLink architecture. NVQLink leverages the RDMA over Converged Ethernet (RoCE) protocol to bypass traditional network stacks and CPU involvement, enabling sub-microsecond data transfer. This is essential to achieve real-time quantum error correction, where latency tolerances are of the order of tens of microseconds for some QPU architectures. While most existing solutions are limited to using FPGA for real-time processing, the availability of real-time compute on GPUs greatly facilitates the use of machine learning and AI for automation and accuracy improvements. First realizations of NVQLink systems thus enable a big step forward towards achieving fault tolerant quantum computing at scale by enabling data-driven research and co-develop of hardware and software solutions to achieve the necessary throughput and latency for commercial applications.

We are living through a fundamental shift in computing, where performance and efficiency gains increasingly come from specialized accelerators tailored to "hot" domains like AI. Yet as accelerator-centric computing proliferates, it continues to build atop a longstanding disconnect between the way we design these systems and the way we program them. This divide slows hardware innovation, complicates the software stack, and makes accelerators far harder to evolve than the rapidly changing applications they are meant to serve.

In this talk, I will present our recent research on closing this gap through a unified hardware-software co-design stack. At the core is a new abstraction that generalizes single program multiple data beyond largely independent threads to encompass spatial structure and communication. It offers a single, composable model for expressing both how accelerators are constructed and how they are programmed. I will show how this abstraction is realized in Allo, an open-source, Python-based, MLIR-powered framework to enable concise specifications that map efficiently across FPGA, ASIC, NPU, and GPU platforms. I will conclude with a forward-looking perspective on automated compiler construction, differentiable hardware synthesis, and agentic design automation, and discuss how these directions may help move us toward truly evolvable heterogeneous computing.

Artificial Intelligence is reshaping how we explore, create, and teach. Tasks once considered inherently human are now increasingly delegated to systems that appear to reason, learn, and even invent. This development challenges long-standing notions of expertise, authorship, and the role of human judgment in science and education.

Through this development, AI already influences how research is conducted, published, and taught - often with remarkable efficiency, yet also with opaque mechanisms and uncertain reliability. The enthusiasm surrounding these tools must be balanced by a critical assessment of their capabilities and limitations. What AI systems produce can be impressive, but their results often lack genuine understanding or intent. The central question is how to preserve creativity, responsibility, and depth of insight in a world where machines can assist with almost everything - except understanding what they do.

In recent years, the paradigm of open source has moved beyond software to transform the landscape of semiconductor design. Open-source Electronic Design Automation (EDA) tools offer a transformative path toward lowering barriers to entry, ensuring technological sovereignty, and accelerating engineering productivity. This talk provides a comprehensive overview of the current state of the open-source hardware ecosystem and its future potential. We will take a deep dive into Europe’s strategic investments in these frameworks and explore how fostering a robust open-source toolchain is the essential catalyst for the next generation of open-source chips.