- DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)
Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.
The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.
IP4_1 Interactive Presentations
Date: Wednesday, 03 February 2021
Time: 09:00 - 09:30
Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session
|IP4_1.1||HARDWARE ACCELERATION OF FULLY QUANTIZED BERT FOR EFFICIENT NATURAL LANGUAGE PROCESSING
Zejian Liu, National Laboratory of Pattern Recognition, Institute of Automation, Chinese Academy of Sciences, CN
Zejian Liu1, Gang Li2 and Jian Cheng1
1National Laboratory of Pattern Recognition, Institute of Automation, Chinese Academy of Sciences, CN; 2Institute of Automation, Chinese Academy of Sciences, CN
BERT is the most recent Transformer-based model that achieves state-of-the-art performance in various NLP tasks. In this paper, we investigate the hardware acceleration of BERT on FPGA for edge computing. To tackle the issue of huge computational complexity and memory footprint, we propose to fully quantize the BERT (FQ-BERT), including weights, activations, softmax, layer normalization, and all the intermediate results. Experiments demonstrate that the FQ-BERT can achieve 7.94× compression for weights with negligible performance loss. We then propose an accelerator tailored for the FQ-BERT and evaluate on Xilinx ZCU102 and ZCU111 FPGA. It can achieve a performance-per-watt of 3.18 fps/W, which is 28.91× and 12.72× over Intel(R) Core(TM) i7-8700 CPU and NVIDIA K80 GPU, respectively.
|IP4_1.2||AXPIKE: INSTRUCTION-LEVEL INJECTION AND EVALUATION OF APPROXIMATE COMPUTING
Isaias Felzmann, University of Campinas, BR
Isaías Bittencourt Felzmann1, João Fabrício Filho2 and Lucas Wanner3
1University of Campinas, BR; 2Unicamp/UTFPR, BR; 3Unicamp, BR
Representing the interaction between accurate and approximate hardware modules at the architecture level is essential to understand the impact of Approximate Computing in a general-purpose computing scenario. However, extensive effort is required to model approximations into a baseline instruction level simulator and collect its execution metrics. In this work, we present the AxPIKE ISA simulation environment, a tool that allows designers to inject models of hardware approximation at the instruction level and evaluate their impact on the quality of results. AxPIKE embeds a high-level representation of a RISC-V system and produces a dedicated control mechanism, that allows the simulated software to manage the approximate behavior of compatible execution scenarios. The environment also provides detailed execution statistics that are forwarded to dedicated tools for energy accounting. We apply the AxPIKE environment to inject integer multiplication and memory access approximations into different applications and demonstrate how the generated statistics are translated into energy-quality trade-offs.