IP3_3 Interactive Presentations

Date: Tuesday, 02 February 2021
Time: 18:30 - 19:00 CET
Virtual Conference Room: https://virtual21.date-conference.com/meetings/virtual/fd6MteFcgFbqQecQy

Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session

Label Presentation Title
Authors
IP3_3.1 DOUBLE DQN FOR CHIP-LEVEL SYNTHESIS OF PAPER-BASED DIGITAL MICROFLUIDIC BIOCHIPS
Speaker:
Fang-Chi Wu, Department of Computer Science and Engineering, National Sun Yat-Sen University, TW
Authors:
Fang-Chi Wu1, Jian-De Li2, Katherine Shu-Min Li1, Sying-Jyan Wang2 and Tsung-Yi Ho3
1National Sun Yat-sen University, TW; 2National Chung Hsing University, TW; 3National Tsing Hua University, TW
Abstract
Paper-based digital microfluidic biochip (PB-DMFB) technology is one of the most promising solutions in biochemical applications due to the paper substrate. The paper substrate makes PB-DMFBs more portable, cost-effective, and less dependent on manufacturing equipment. However, the single-layer paper substrate, which entangles electrodes, conductive wires, and droplet routing in the same layer, raises challenges to chip-level synthesis of PB-DMFBs. Furthermore, current design automation tools have to address various design issues including manufacturing cost, reliability, and security. Therefore, a more flexible chip-level synthesis method is necessary. In this paper, we propose the first reinforcement learning based chip-level synthesis for PB-DMFBs. Double deep Q-learning networks are adapted for the agent to select and estimate actions, and then we obtain the optimized synthesis results. Experimental results show that the proposed method is not only effective and efficient for chip-level synthesis but also scalable to reliability and security–oriented schemes.
IP3_3.2 CONSTRUCTIVE USE OF PROCESS VARIATIONS: RECONFIGURABLE AND HIGH-RESOLUTION DELAY-LINE
Speaker:
Xiaolin Xu, Northeastern University, US
Authors:
Wenhao Wang1, Yukui Luo2 and Xiaolin Xu2
1ECE Department of Northeastern University, US; 2Northeastern University, US
Abstract
Delay-line is a critical circuit component for highspeed electronic design and testing, such as high-performance FPGA and ASICs, to provide timing signals of specific duration or duty cycle. However, the performance of existing CMOS-based delay-lines is limited by various practical issues. For example, the minimum propagation delay (resolution) of CMOS gates is limited by the process variations from circuit fabrication. This paper presents a novel delay-line scheme, which instead of mitigating the process variations from circuit fabrication, constructively leverages them to generate time signals of specific duration. Moreover, the resolution of the proposed delay-line method is reconfigurable, for which we propose a Machine Learning modeling method to assist such reconfiguration, i.e., to generate time duration of different scales. The performance of the proposed delay-line is validated with HSpice simulation and prototype on a Xilinx Virtex-6 FPGA evaluation kit. The experimental results demonstrate that the proposed delay