Topic: D8 Network on Chip

Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Luca Carloni, Columbia University, US, Contact

Members:

• Federico Angiolini, iNoCs, CH, Contact
• Masoud Daneshtalab, university of Turku, FI, Contact
• Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
• Josè Flich, Universidad Politecnica de Valencia, ES, Contact
• Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
• Paul Gratz, Texas A&M University, US, Contact
• Yinhe Han, Chinese Academy of Science, CN, Contact
• Andreas Hansson, ARM Ltd, GB, Contact
• Shaahin Hessabi, Sharif University of Technology, IR, Contact
• Ravi Iyer, Intel, US, Contact
• John Kim, KAIST, KR, Contact
• Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
• , Contact
• Hiroki Matsutani, Keio University, JP, Contact
• Steven Nowick, Columbia University, US, Contact
• Umit Ogras, Arizona State University, US, Contact