Technical Programme Committee 2016

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TPC Meeting

For detailed information about the DATE 2016 TPC meeting, please visit the event’s website at: http://date2016tpc.fau.de

For a short description of the DATE 2016 TPC meeting, agenda of the meeting and registration information, please click here

Track D: Design, Methods and Tools (click to open)

addressing design automation, design tools and hardware architectures for electronic and embedded systems. Emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems. This includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows and environments.

Track Chair: Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact

Topics

D1 System Specification and Modeling (click to open)

Chair: Christian Haubelt, University of Rostock, DE, Contact

Co-Chair: Andy Pimentel, University of Amsterdam, NL, Contact

Topic Members (click to open)

  • Andreas Gerstlauer, University of Texas at Austin, US, Contact
  • Timo Hämäläinen, Tampere University of Technology, FI, Contact
  • Michael Hübner, Ruhr-U Bochum, DE, Contact
  • Jorn W. Janneck, Lund University, SE, Contact
  • Frédéric Mallet, Université Nice Sophia Antipolis, FR, Contact
  • Frank Oppenheimer, OFFIS e. V., DE, Contact
  • Gianluca Palermo, Politecnico di Milano, IT, Contact
  • Laurence Pierre, TIMA, FR, Contact
  • Martin Radetzki, Institut für Technische Informatik, DE, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact

Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, High-Level Synthesis and Optimization (click to open)

Chair: Andreas Herkersdorf, TU München, DE, Contact

Co-Chair: Nikil Dutt, Unviersity of California, Irvine, US, Contact

Topic Members (click to open)

  • Alberto A. Barrio del, Universidad Complutense de Madrid: UCM, ES, Contact
  • Lars Bauer, KIT, DE, Contact
  • Philippe Coussy, Universite de Bretagne Sud / Lab-STICC, FR, Contact
  • Suhaib A. Fahmy, University of Warwick, GB, Contact
  • Michael Glaß, University of Erlangen, DE, Contact
  • Kim Grüttner, OFFIS - Institute for Information Technology, DE, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Luciano Lavagno, Politecnico di Torino, IT, Contact
  • Roman Lysecky, University of Arizona, US, Contact
  • Christian Plessl, University of Paderborn, DE, Contact
  • Donatella Sciuto, Politecnico di Milano, It, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • David Thomas, Imperial College London, GB, Contact
  • Jason Xue Chun, City University of Hong Kong, HK, Contact
  • Daniel Ziener, FAU Erlangen, DE, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; hw/sw design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Elena Vatajelu, Politecnico de Torino, IT, Contact

Co-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Mingsong Chen, East China Normal University, CN, Contact
  • Adrian Evans, iRoC Technologies, FR, Contact
  • Florian Letombe, Synopsys, FR, Contact
  • Ronny Morad, IBM Research - Haifa, IL, Contact
  • Xiaoke Qin, NVIDIA, US, Contact
  • Pablo Sanchez, University of Cantabria, ES, Contact
  • Alper Sen, Bogazici University, TR, Contact
  • Li Wang, UC Santa Barbara, US, Contact

Simulation-based validation and verification; acceleration-driven and emulation-based validation; post-silicon verification; online checkers and runtime verification targeting new and traditional architectures and addressing the verification challenge at any level, from system to circuit level; diagnosing and debugging solutions for any of the verification platforms above; testbenches, checkers, assertions and monitor generation for verification; multi-domain simulation techniques; validation of cyber-physical systems, SoCs and emerging architectures.

D4 Formal Methods and System Verification (click to open)

Chair: Julien Schmaltz, Eindhoven University of Technology, NL, Contact

Co-Chair: Christoph Scholl, University Freiburg, DE, Contact

Topic Members (click to open)

  • Armin Biere, Universitaet Linz, AT, Contact
  • Per Bjesse, Synopsys, IE, Contact
  • Gianpiero Cabodi, Politecnico di Torino, IT, Contact
  • Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
  • Marijn Heule, The University of Texas at Austin, US, Contact
  • John O’leary, Intel Coporation, US, Contact
  • Anna Slobodova, Centaur Technology, US, Contact
  • Daryl Stewart, ARM, GB, Contact
  • Markus Wedler, Synopsys, DE, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, SoCs, cores, real-time and embedded systems; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.

DT5 Design and Test for Analog and Mixed-Signal Systems and Circuits (click to open)

Chair: Andre Ivanov, UBC, CA, Contact

Co-Chair: Helmut Graeb, Technische Universitaet Muenchen, DE, Contact

Topic Members (click to open)

  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Árpád Bürmen, University of Ljubljana, SI, Contact
  • Catherine Dehollain, EPFL, CH, Contact
  • Günhan Dündar, Boğaziçi University, TR, Contact
  • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
  • Christoph Grimm, TU Vienna, AT, Contact
  • Lars Hedrich, University of Frankfurt, DE, Contact
  • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
  • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
  • (Mark) Po-Hung Lin, National Chung Cheng University, TW, Contact
  • Dominique MORCHE, CEA-Leti, FR, Contact
  • Jaijeet Roychowdhury, UC Berkeley, US, Contact
  • Haralampos-G. Stratigopoulos, LIP6 (CNRS, Sorbonne Universités, UPMC), FR, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel, BE, Contact

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

D6 Emerging Technologies and Systems (click to open)

Chair: Michael Niemier, University Of Notre Dame, US, Contact

Co-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • R. Iris Bahar, School of Engineering, Brown University, US, Contact
  • Swarup Bhunia, Case Western Reserve University, US, Contact
  • Krishnendu Chakrabarty, Duke University, US, Contact
  • Pierre-Emmanuel Gaillardon, EPFL, CH, Contact
  • Tuhin Ghua Neogi , GlobalFoundries, US, Contact
  • Bastien Giraud, CEA-Leti, Minatec, FR, Contact
  • Tsung-Yi Ho, National Cheng Kung University, TW, Contact
  • Hai Li, Dept. of Electrical and Computer Engineering University of Pittsburgh, US, Contact
  • Eike Linn, RWTH Aachen, DE, Contact
  • Jan Madsen, Technical University of Denmark, DK, Contact
  • Dmitri Maslov, National Science Foundation, US, Contact
  • Subhasish Mitra, Stanford University, US, Contact
  • Kartik Mohanram, University of Pittsburgh, US, Contact
  • Pritish Narayanan, IBM Research Almaden, US, Contact
  • Fabian Oboril, KIT, DE, Contact
  • Marco Ottavi, University of Rome "Tor Vergata", IT, Contact
  • Jean-Michel Portal, IM2NP, FR, Contact
  • Antonio Rubio, Universitat Politècnica de Catalunya (UPC), ES, Contact
  • Jack Sampson, Pennsylvania State University, US, Contact
  • Yiyu Shi, U. of Missouri / University of Notre Dame, US, Contact
  • Yvain Thonnart, CEA, LETI, MINATEC, FR, Contact
  • Aida Todri-Sanial, CNRS - LIRMM, FR, Contact
  • Andy M. Tyrrell, University of York, GB, Contact
  • Yu Wang, Tsinghua University, CN, Contact
  • Walter Weber, Namlab gGmbH, DE, Contact
  • Hao Yu, Nanyang Technological University, SG, Contact

Modeling, circuit design and design automation flows for future technologies: monolithic 3D integration (TSV modeling and design space exploration); MEMS; non-CMOS logic, memory, and interconnect (e.g., STT-RAM, PCRAM, advances in flash memory technology, optical, etc.); emerging FET devices (e.g., graphene-based FETs, TFETs, etc.). Biologically-based or biologically-inspired computing systems; Bio-MEMS, lab-on-a-chip. System design methods, models of computation, and case studies for emerging applications: quantum computing, reversible logic, wearable computing, e-textiles, etc.

D7 Power Modeling, Optimization and Low-Power Design (click to open)

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR, Contact

Topic Members (click to open)

  • Antonio Acosta, Univ. of Seville/IMSE, ES, Contact
  • Edith Beigne, CEA-Leti Minatec, FR, Contact
  • Andrea Calimera, Politecnico di Torino, IT, Contact
  • William Fornaciari, Politecnico di Milano, IT, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Jae-joon Kim, POSTECH, KR, Contact
  • Marisa Lopez-Vallejo, UPM, ES, Contact
  • Diana Marculescu, Carnegie Mellon University, US, Contact
  • Andrea Marongiu, University of Bologna, IT, Contact
  • Seda Memik, Northwestern University, US, Contact
  • Hiroshi Nakamura, Graduate School of Information Science and Technology, the University of Tokyo, JP, Contact
  • Alberto Nannarelli, Technical University of Denmark, DK, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • Donghwa Shin, Yeungnam University, KR, Contact
  • Tajana Simunic Rosing, UCSD, US, Contact
  • Sheldon Tan, UC Riverside, US, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact

Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

D8 Network on Chip (click to open)

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Luca Carloni, Columbia University, US, Contact

Topic Members (click to open)

  • Federico Angiolini, iNoCs, CH, Contact
  • Masoud Daneshtalab, university of Turku, FI, Contact
  • Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
  • Josè Flich, Universidad Politecnica de Valencia, ES, Contact
  • Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
  • Paul Gratz, Texas A&M University, US, Contact
  • Yinhe Han, Chinese Academy of Science, CN, Contact
  • Andreas Hansson, ARM Ltd, GB, Contact
  • Shaahin Hessabi, Sharif University of Technology, IR, Contact
  • Ravi Iyer, Intel, US, Contact
  • John Kim, KAIST, KR, Contact
  • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
  • Riccardo Locatelli, ST Microelectronics, FR, Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • Steven Nowick, Columbia University, US, Contact
  • Umit Ogras, Arizona State University, US, Contact

Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

D9 Architectural and Microarchitectural Design (click to open)

Chair: Todd Austin, University of Michigan, US, Contact

Co-Chair: Cristina Silvano, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Sandro Bartolini, University of Siena, IT, Contact
  • Mladen Berekovic, TU Braunschweig, DE, Contact
  • Elaheh Bozorgzadeh, University of California, Irvine, US, Contact
  • Jeronimo Castrillon, TU Dresden, Germany, DE, Contact
  • Francisco J. Cazorla, Barcelona Supercomputing Center, ES, Contact
  • Giuseppe Desoli, STMicroelctronics, IT, Contact
  • Pedro Diniz, University of Southern California, US, Contact
  • Leandro Fiorin, IBM Research, NL, Contact
  • Jörg Henkel, KIT, DE, Contact
  • Soontae Kim, KAIST, KR, Contact
  • Benjamin C. Lee, Duke University, US, Contact
  • Yun (eric) Liang, Peking University, CN, Contact
  • Onur Mutlu, Carnegie Mellon University, US, Contact
  • Sri Parameswaran, UNSW, AU, Contact
  • Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact
  • Laura Pozzi, University of Lugano, CH, Contact
  • Toshinori Sato, Fukuoka University, JP, Contact
  • Antonino Tumeo, Pacific Northwest National Laboratory, US, Contact
  • Stephan Wong, TU Delft, NL, Contact
  • Yuan Xie, Penn State University, US, Contact
  • Sotirios Xydis, National Technical University of Athens, GR, Contact

Architectural and micro-architectural design techniques; memory systems; power and energy efficient architectures; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, security, timing predictability.

D11 Reconfigurable Computing (click to open)

Chair: Fabrizio Ferrandi, Politecnico di Milano, IT, Contact

Co-Chair: Ryan Kastner, University of California San Diego, US, Contact

Topic Members (click to open)

  • Tobias Becker, Maxeler Technologies, GB, Contact
  • Michaela Blott, XILINX, IE, Contact
  • Philip Brisk, University of California, Riverside, US, Contact
  • Florent de Dinechin, INSA de Lyon, FR, Contact
  • Enno Luebbers, Intel Open Lab Munich, DE, Contact
  • Smail Niar, University of Valenciennes, FR, Contact
  • Marco Platzner, University of Paderborn, DE, Contact
  • Hayden So Kwok-Hay, University of Hong Kong, HK, Contact

Reconfigurable computing platforms and architectures; heterogeneous platforms (FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high performance and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.

D12 Logical and Physical Analysis and Design (click to open)

Chair: Patrick Groeneveld, Synopsys, US, Contact

Co-Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact

Topic Members (click to open)

  • Valentina Ciriani, University of Milano, IT, Contact
  • Luca Daniel, Massachusetts Institute of Technology, US, Contact
  • Azadeh Davoodi, University of Wisconsin - Madison, US, Contact
  • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
  • Jens Lienig, Technical University of Dresden, DE, Contact
  • Igor Markov, University of Michigan, US, Contact
  • José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact
  • Sven Peyer, IBM, DE, Contact
  • Cliff Sze, IBM Austin Research Laboratory, US, Contact
  • Tiziano Villa, University of Verona, IT, Contact
  • Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments. Parasitic and variation-aware extraction for on-chip interconnect, and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.

D10 Temperature and Variability Aware Design and Optimization (click to open)

Topic Members (click to open)

    The topic focuses on novel methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects. Themes of interest include, but are not limited to, design and run-time thermal, variability and reliability management of SoCs and multi-core platforms (both at hardware and software level), as well as modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.


    Track A: Application Design (click to open)

    is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design and test methodologies, and applications of specific design and test technologies. Contributions should illustrate state-of-the-art or record-breaking designs, which will provide viable solutions in tomorrow's silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.

    Track Chair: Ayse Coskun, Boston University, US, Contact

    Topics

    A1 Green Computing Systems (click to open)

    Chair: Murali Annavaram, University of Southern California, US, Contact

    Co-Chair: Andreas Burg, EPFL, CH, Contact

    Topic Members (click to open)

    • Luca Benini, ETHZ, CH, Contact
    • Jungsoo Kim, Samsung Electronics, KR, Contact
    • Yanzhi Wang, University of Southern California, US, Contact

    Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for parallel systems and cloud computing, virtualization, energy-efficient memory, processor, or communication architectures including emerging non-volatile memory architectures and their use as storage and memory in datacenters, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in the smart-grids.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Sergio Saponara, University of Pisa, IT, Contact

    Co-Chair: Steffen Paul, Unversity Bremen, DE, Contact

    Topic Members (click to open)

    • Nicola Acito, Direzione Studi Accademia Navale , IT, Contact
    • Amer Baghdadi, TELECOM Bretagne, FR, Contact
    • Christos Bouganis, Imperial College, GB, Contact
    • Marcello Coppola, STMicroelectronics, FR, Contact
    • Christian Drewes, Intel Mobile Communications GmbH, DE, Contact
    • Guido Masera, Politecnico di Torino, IT, Contact
    • Theocharis Theocharides, University of Cyprus, CY, Contact

    Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

    A3 Automotive Systems and Smart Energy Systems  (click to open)

    Chair: David Boyle, Imperial College London, GB, Contact

    Co-Chair: Felix Reimann, Audi, DE, Contact

    Topic Members (click to open)

    • Juergen Becker, KIT - Karlsruher Institut für Technolgie, DE, Contact
    • Martin Lukasiewycz, TUM CREATE, SG, Contact
    • Pit Pillatsch, UC Berkeley, US, Contact
    • Bart Vermeulen, NXP Semiconductors, NL, Contact
    • Wensi Wang, Tyndall National Institute, IR, Contact

    This topic covers works that describe design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Furthermore, this topic also includes design methods including models and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Finally, topics of interest are also hardware and software solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

    A4 Ambient Intelligence and Low-Power Systems for Healthcare, Wellness and Assistive Technology (click to open)

    Chair: Elisabetta Farella, Fondazione Bruno Kessler, IT, Contact

    Co-Chair: Francisco Rincon, EPFL, CH, Contact

    Topic Members (click to open)

    • Luca Fanucci, University of Pisa, IT, Contact
    • Srinivasan Murali, SmartCardia, CH, Contact
    • Joaquín Recas, Computense University of Madrid, ES, Contact

    Medical, healthcare, and life science applications require increasingly smarter and smaller devices enabling to easily interact among each other, with the environment and with the users in a smooth and smart way. Personal and personalized medicine and rehabilitation is leading to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. This topic covers the use of ambient intelligence, wireless body sensor networks, assistive and wearable technologies for healthcare, rehabilitation and wellness. This includes but it is not limited to: technologies for ultra-low/zero power systems for personal vital signs monitoring (such as heart rate, fitness devices); body area networks; mobile system for motor rehabilitation and assessment; (bio)feedback system for rehabilitation; wearable computing technologies, devices and systems for supporting healthy lifestyle and fitness; ambient assisted living technologies; innovative implantable miniaturized sensors and actuators; smart spaces for elderly and impaired users, technologies for motor disorders; personal health devices and assistive technology; Bio-MEMS; lab-on-a-chip; power management, on-board performance optimization and networking technologies for body area networks and ambient intelligence in wellness, healthcare and fitness.

    A5 Secure Systems (click to open)

    Chair: Tim Güneysu, University of Bremen, DE, Contact

    Co-Chair: Wieland Fischer, Infineon, DE, Contact

    Topic Members (click to open)

    • Viktor Fischer, Laboratoire Hubert Curien, FR, Contact
    • Aurélien Francillon, EURECOM, FR, Contact
    • Roel Maes, Intrinsic-ID, NL, Contact
    • Stefan Mangard, TU Graz, AT, Contact
    • Marcel Medwed, NXP Semiconductors, AT, Contact
    • Filippo Melzani, STMicroelectronics, IT, Contact
    • Maire O'Neill, Queen's University Belfast, GB, Contact
    • David Oswald, University of Birmingham, GB, Contact
    • Ilia Polian, University of Passau, DE, Contact
    • Francesco Regazzoni, AlaRI, CH, Contact
    • Patrick Schaumont, Virginia Tech, US, Contact
    • Ingrid Verbauwhede, KU Leuven and UCLA, BE, Contact
    • Marc Witteman, Riscure, NL, Contact

    Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: Praveen Raghavan, IMEC, BE, Contact

    Co-Chair: Christian Weis, University of Kaiserslautern, DE, Contact

    Topic Members (click to open)

    • Marco Domenico Santambrogio, Polimi, IT, Contact
    • Veit B. Kleeberger, Infineon Technologies AG, DE, Contact
    • Christian Pilato, Columbia University, US, Contact
    • Wenjing Rao, University of Illinois at Chicago, US, Contact
    • Chiara Sandionigi, CEA, FR, Contact

    As scaling continues, the impact of reliability/aging and variability has increased and design and applications need to take this into account. This topic covers the area of reliable, and variability aware adaptive systems for practical and industrial applications. The scope of this topic includes, but not limited to, the system development and optimization, practical application mechanisms and use cases that compensate reliability issues, such as aging, variability and temperature, the development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Industrial Experiences Brief Papers (click to open)

    Chair: Ahmed Jerraya, CEA Leti, FR, Contact

    Co-Chair: Michael Nicolaidis, TIMA, FR, Contact

    Topic Members (click to open)

    • Arkadi Bramnik, INTEL, US, Contact
    • Raphaël David, CEA LIST, FR, Contact
    • Emil Matus, Technische Universität Dresden, DE, Contact
    • Eugenio Villar, University of Cantabria, ES, Contact
    • Norbert Wehn, TU Kaiserslautern, DE, Contact

    Short or long industrial papers with a minimum size of two pages, and up to six pages, are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


    Track T: Test and Robustness (click to open)

    covering all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.

    Track Chair: Cecilia Metra, University of Bologna, IT, Contact

    Topics

    T1 Defects, Faults, Variability and Reliability Analysis and Modeling (click to open)

    Chair: Robert Aitken, ARM, US, Contact

    Co-Chair: Michel Renovell, LIRMM, FR, Contact

    Topic Members (click to open)

    • Bartomeu Alorda, Illes Balears University, ES, Contact
    • Sounil Biswas, NVIDIA, US, Contact
    • Said Hamdioui, Delft University of Technology, NL, Contact
    • Bram Kruseman, NXP Semiconductors, NL, Contact
    • Kuen-Jong Lee, National Cheng Kung University, TW, Contact
    • Irith Pomeranz, Purdue University, US, Contact
    • Rosa Rodriguez, UPC, ES, Contact
    • Mehdi Tahoori, Karlsruhe Institute of Technology, DE, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis; reliability analysis and modeling, failure mode and effect analysis (FMEA) and physics of failures; noise and uncertainty modeling; test and reliability issues in emerging technologies; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations; process yield modeling and enhancement; design-for-manufacturability and design-for-yield.

    T2 Test Generation, Simulation and Diagnosis (click to open)

    Chair: Bernd Becker, University of Freiburg, DE, Contact

    Co-Chair: Wu-Tung Cheng, Mentor Graphics, US, Contact

    Topic Members (click to open)

    • Jacob Abraham, University of Texas at Austin, US, Contact
    • Piet Engelke, Infineon, DE, Contact
    • Huawei Li, Institute of Computing Technology, CAS, CN, Contact
    • Nicola Nicolici, McMaster University, CA, Contact
    • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
    • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

    Test pattern generation (TPG); fault simulation; system test; test coverage metrics and estimation; adaptive test; self-healing/self-calibration/self-adaptation; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, 3D chips; hardware/software system test; processor based test.

    T3 Design-for-Test, Test Compression and Access (click to open)

    Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

    Co-Chair: Magdy Abadir, Independent, US, Contact

    Topic Members (click to open)

    • Dimitris Gizopoulos, University of Athens, Gr, Contact
    • Peter Harrod, ARM Ltd, GB, Contact
    • Paolo Prinetto, Politecnico di Torino, IT, Contact
    • Ozgur Sinanoglu, NYU-AD University, AE, Contact
    • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

    Design for test, debug, diagnosis, manufacturing and yield; hardware infrastructure for test, self-test, debug, diagnosis and post-silicon validation; reconfigurable scan; test of memories and regular structures; DFT for 3D-systems; test compression and compaction; power aspects of DFT; security and safety implications of test infrastructure; automatic test equipment; test economics and test standards.

    T4 On-Line Test, Fault Tolerance and Robust Systems (click to open)

    Chair: Fabrizio Lombardi, Northeastern University, US, Contact

    Co-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

    Topic Members (click to open)

    • Jaume Abella, Barcelona Supercomputing Center, ES, Contact
    • Lorena Anghel, TIMA, FR, Contact
    • Jennifer Dworak, Southern Methodist University, US, Contact
    • Jie Han, University of Alberta, CA, Contact
    • Viacheslav Izosimov, The Royal Institute of Technology, SE, Contact
    • Maksim Jenihhin, Tallinn University of Technology, EE, Contact
    • Maria Michael, University of Cyprus, CY, Contact
    • Kazutero Namba, Chiba University, JP, Contact
    • Salvatore Pontarelli, University of Rome "Tor Vergata", IT, Contact
    • Mihalis Psarakis, University of Piraeus, GR, Contact
    • Pedro Reviriego, Universidad Antonio de Nebrija, ES, Contact
    • Ioannis Sourdis, Chalmers Univeristy of Technology, SE, Contact
    • Andreas Steininger, Vienna University of Technology, AT, Contact

    Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuit and system design; dependability evaluation, reliable system design; hardware/software recovery; self-repair; fault tolerance.

    DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems (click to open)

    Chair: Andre Ivanov, UBC, CA, Contact

    Co-Chair: Helmut Graeb, Technische Universitaet Muenchen, DE, Contact

    Topic Members (click to open)

    • Manuel Barragan, TIMA Laboratory, FR, Contact
    • Árpád Bürmen, University of Ljubljana, SI, Contact
    • Catherine Dehollain, EPFL, CH, Contact
    • Günhan Dündar, Boğaziçi University, TR, Contact
    • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Lars Hedrich, University of Frankfurt, DE, Contact
    • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
    • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
    • (Mark) Po-Hung Lin, National Chung Cheng University, TW, Contact
    • Dominique MORCHE, CEA-Leti, FR, Contact
    • Jaijeet Roychowdhury, UC Berkeley, US, Contact
    • Haralampos-G. Stratigopoulos, LIP6 (CNRS, Sorbonne Universités, UPMC), FR, Contact
    • Gerd Vandersteen, Vrije Universiteit Brussel, BE, Contact

    Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.


    Track E: Embedded Systems Software (click to open)

    is devoted to modelling, analysis, design and deployment of embedded software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on modelbased design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked and dependable systems.

    Track Chair: Franco Fummi, Universita' di Verona, IT, Contact

    Topics

    E1 Real-time, Networked, and Dependable Systems (click to open)

    Chair: Rodolfo Pellizzoni, University of Waterloo, CA, Contact

    Co-Chair: Jan Reineke, Informatik, Universität des Saarlandes, DE, Contact

    Topic Members (click to open)

    • Iain Bate, University of York, GB, Contact
    • Marko Bertogna, University of Modena, IT, Contact
    • Liliana Cucu, INRIA, FR, Contact
    • Dionisio de Niz, Carnegie Mellon University, US, Contact
    • Raimund Kirner, University of Hertfortshire, GB, Contact
    • Kai Lampka, Uppsala University, SE, Contact
    • Benjamin Lesage, University of York, GB, Contact
    • Giuseppe Lipari, Scuola Superiore Sant'Anna, IT, Contact
    • Dorin Maxim, ISEP, PT, Contact
    • Florian Pölzlbauer, Virtual Vehicle, AT, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications.

    E2 Compilers and Software Synthesis for Embedded Systems (click to open)

    Chair: Tulika Mitra, National University of Singapore, SG, Contact

    Co-Chair: Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact

    Topic Members (click to open)

    • Sebastian Hack, University of Saarland, DE, Contact
    • Huynh Phung Huynh, A*STAR Institute of High Performance Computing, SG, Contact
    • Ronan Keryell, Xilinx, IE, Contact
    • Aviral Shrivastava, Arizona State University, US, Contact
    • Jingling Xue, University of New South Wales, AU, Contact

    Compiler support for multi-core/many-core architectures, GPUs, CGRAs, FPGAs, accelerators in heterogeneous computing platforms, memory hierarchy including caches, scratchpad, and non-volatile memories; Code analysis, optimization, and generation for different metrics (e.g., performance, power/energy, code/data size, reliability, security, WCET, etc.); Just-in-time compilation, interpreters, binary translation; Compiler support for enhanced debugging, profiling, and traceability; Software tools and techniques for design space exploration (compilers, simulators, synthesis tools); Compilation infrastructures for high-level synthesis and domain-specific or streaming languages for embedded systems; Software synthesis for IoT, wearables, cyber-physical systems, programmable microfluidics.

    E3 Model-based Design and Verification for Embedded Systems (click to open)

    Chair: Linh Thi Xuan Phan, University of Pennsylvania, US, Contact

    Co-Chair: Petru Eles, Linköping University, SE, Contact

    Topic Members (click to open)

    • Saddek Bensalem, Université Joseph Fourier, FR, Contact
    • Alain Girault, INRIA, FR, Contact
    • Lothar Thiele, ETH Zurich, CH, Contact
    • Stavros Tripakis, Aalto University/ UC Berkeley, FI, Contact
    • Wang Yi, Uppsala University, SE, Contact

    Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components.

    E4 Embedded Software Architectures (click to open)

    Chair: Marc Geilen, TU Eindhoven, NL, Contact

    Co-Chair: Frédéric Pétrot, TIMA Laboratory, FR, Contact

    Topic Members (click to open)

    • Oliver Bringmann, FZI / University of Tuebingen, DE, Contact
    • Gero Dittmann, IBM Research, CH, Contact
    • Akash Kumar, Electrical and Computer Engineering, National University of Singapore, SG, Contact
    • Orlando Moreira, Ericsson, NL, Contact
    • Tanguy Risset, Insa-Lyon, FR, Contact
    • Gunar Schirner, Norhteastern University, US, Contact
    • Hiroyuki Tomiyama, Ritsumeikan University, JP, Contact

    Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for reconfigurable components and accelerators; Software architectures for low power and temperature awareness.

    E5 Cyber-Physical Systems (click to open)

    Chair: Paul Pop, Technical University of Denmark, DK, Contact

    Co-Chair: Tarek Abdelzaher, University of Illinois at Urbana Champaign, US, Contact

    Topic Members (click to open)

    • Karl-Erik Arzen, Lund University, SE, Contact
    • Jean-Dominique Decotignie, EPFL, CH, Contact
    • Shiyan Hu, Michigan Technological University, US, Contact

    Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis; Case studies in CPS ranging from automotive systems, and avionics, to smart buildings and smart grids.