UB09 Session 9

Label	Presentation Title Authors
UB09.1	AHLS_DESYNC: DESYNCHRONIZATION TOOL FOR HIGH-LEVEL SYNTHESIS OF ASYNCHRONOUS CIRCUITS Presenter: Jean Simatic, TIMA Laboratory, FR Authors: Jean Simatic, Rodrigo Possamai Bastos and Laurent Fesquet, TIMA Laboratory, FR Abstract We present a tool for the high-level synthesis (HLS) of event-driven (asynchronous) circuits. Our approach first uses an existing HLS tool, AUGH, to generate a synchronous finite state machine (FSM) and a data-path. Then, the presented tool desynchronizes solely the FSM in 5 steps: 1. Parse the FSM to build a state graph containing the control signal assignments. 2. Separate multiplexer control and register control signals by analyzing the data-path. 3. Generate an event-driven FSM netlist by mapping the state graph on a dedicated set of asynchronous controllers. 4. Synthesize the data-path thanks to a commercial synthesis tool (Design Compiler). 5. Estimate the delays in the data-path with a static timing analysis tool (PrimeTime). Insert delays in the controller accordingly. Our demonstration will exhibit two testbenches: a GCD algorithm to expose the basic concepts and a non-uniform sampling FIR filter more representative of real-life applications. Download Paper (PDF)
UB09.2	D-VASIM: TIMING ANALYSIS OF GENETIC LOGIC CIRCUITS USING D-VASIM Presenter: Hasan Baig, Technical University of Denmark, DK Authors: Hasan Baig and Jan Madsen, Technical University of Denmark, DK Abstract A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to control gene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electronic logic circuits, timing and propagation delay analysis may also play a very significant role in the designing of genetic logic circuits. In this demonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagation delay analysis of a single as well as cascaded genetic logic circuits. D-VASim allows user to change the circuit parameters during runtime simulation to observe their effects on circuit's timing behavior. The results obtained from D-VASim can be used not only to characterize the timing behavior of genetic logic circuits but also to analyze the timing constraints of cascaded genetic logic circuits. Download Paper (PDF)
UB09.3	IN-NODE PROCESSING: MODELLING FRAMEWORK FOR IN-NODE PROCESSING IN INDUSTRIAL SENSOR AND ACTUATOR NETWORKS. Presenter: Qaiser Anwar, Mid Sweden University, SE Authors: Qaiser Anwar, Muhammad Imran and Mattias O´Nils, Mid Sweden University, SE Abstract Architecting efficient systems with on-board sensing capabilities with a growing number of sensing devices is a challenging task, in particular because of the range of the technological field, as well as the diversity and complexity of requirements. We present a novel modeling framework, which can describe different implementation strategies for computation of data locally. In this framework, we first describe the systems in Architecture Analysis and Design Language (AADL), following which the described system is exported to XML which is then given input to java based software program. This program automatically generates different implementation options, illustrates different parameters such as processing energy, communication energy, latency and design complexity. To show a proof-of-concept, we have modelled a real-life system in a modelling framework, which shows that the framework can be of use in automated design space and architecture exploration for in-node processing. Download Paper (PDF)
UB09.4	FORMAL VERIFICATION OF CLOCK DOMAIN CROSSING USING GATE-LEVEL MODELS OF METASTABLE FLIP-FLOPS Presenter: Ghaith Tarawneh, Newcastle University, GB Authors: Ghaith Tarawneh, Andrey Mokhov and Alex Yakovlev, Newcastle University, GB Abstract We present a first prototype of a gate-level tool that enables simple and intuitive verification of multi-clock designs. The tool's underlying methodology (described in the paper "Formal Verification of Clock Domain Crossing using Gate-level Models of Metastable Flip-Flops" to be presented in the conference) relies on transforming gate-level netlists so that they can reproduce problematic CDC behaviour digitally. Processed netlists can then be passed to formal verification tools to identify and debug CDC faults. The tool is at an early development stage but consists of a functional Verilog parser and CDC transformation functions that can be invoked from the command line. The demo will showcase the tool using simple sender-receiver circuits. Synthesized netlists will be processed by the tool and then fed to a formal verification tool to identify CDC issues (e.g. missing synchronizers, path convergence). Verification output from source and processed netlists will be compared. Download Paper (PDF)
UB09.5	LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA Presenter: Behailu Shiferaw Negash, University of Turku, FI Authors: Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen² ¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE Abstract There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud. Download Paper (PDF)
UB09.6	AUTOMATED REFINEMENT OF ANALOG/MIXED-SIGNAL SYSTEMC MODELS BY NON-FUNCTIONAL EFFECTS Presenter: Georg Gläser, IMMS, DE Authors: Georg Gläser¹, Hyun-Sek Lukas Lee², Eckhard Hennig³, Markus Olbrich² and Erich Barke² ¹IMMS, DE; ²Leibniz Universität Hannover, DE; ³Reutlingen University, DE Abstract Virtual prototyping of analog/mixed-signal (A/MS) systems is a key concern in the modern design process. The main challenge is performing the verification of functional properties with respect to non-functional effects, e.g. signal and power integrity. System architects are challenged by identifying critical scenarios where these effects possibly degrade or even destroy the system's functionality. We demonstrate a method to automatically extend an existing functional model by non-functional effects. Combined with an accelerated, piecewise-linear (PWL) simulation scheme (PRAISE), we explore the resulting system acceptance regions and identify critical scenarios. Download Paper (PDF)
UB09.7	A CIRCUIT EXTRACTION TOOL FOR FULL CUSTOM DESIGNED MEMS SENSORS Presenter: Axel Hald, Robert Bosch GmbH, DE Authors: Axel Hald¹, Johannes Seelhorst¹, Mathias Reimann¹, Juergen Scheible² and Jens Lienig³ ¹Robert Bosch GmbH, DE; ²Reutlingen University, DE; ³Technische Universität Dresden, DE Abstract In contrast to IC design, MEMS design still lacks sophisticated component libraries. Therefore, the physical design of today's MEMS sensors is mostly done by simply drawing polygons. Hence, the sensor structure is only given as plain graphic data which hinders the identification and investigation of topology elements. The growing complexity of future MEMS designs demands a deep and detailed analysis of the sensor structures and the topology elements in order to get a better understanding of the coupling capacitances and parasitics. Our tool is able to extract a circuit out of a MEMS sensor designed in a polygon based design flow. The key feature of this tool is a rule based structure recognition algorithm which identifies the topology elements of the sensor. Thereafter, the electrostatic RC-extraction is performed by a commercial field solver. The extracted lumped elements can be used for further simulation and optimization tasks during the design phase. Download Paper (PDF)
UB09.8	PSMGEN: AUTOMATIC GENERATION OF POWER STATE MACHINES Presenter: Alessandro Danese, University of Verona, IT Authors: Alessandro Danese¹, Graziano Pravadelli¹ and Daniel Lorenz² ¹University of Verona, IT; ²OFFIS - Institute for Information Technology, DE Abstract Power State Machines are a well-known approach to model and simulate the time-based energy consumption of IP cores for early virtual prototyping of SoCs. However, in the most of the works either the presence of PSMs is assumed or they are manually defined starting from a more or less precise knowledge of the functional blocks composing the target IP. To allow a tighter definition of PSMs, we present PSMGen, a tool implementing an automatic methodology for PSMs' generation and an efficient statistical approach for their simulation. The tool requires as input a set of functional traces exposing the IP's behaviours and the corresponding set of power traces over time that represent the golden model of the IP's energy consumption.It then generates PSM's states and transitions through a mining procedure that extracts the IP behaviours from the functional traces, analyses power changes on the power traces and annotate each PSM's state with the corresponding power characterization Download Paper (PDF)
UB09.9	6CH-SDR-PLATFORM: 6 CHANNEL SDR PROTOTYPING PLATFORM FOR VEHICLE SELF-LOCALIZATION Presenter: Marko Rößler, Technische Universität Chemnitz, DE Authors: Marko Rößler¹, Ulrich Heinkel¹, Daniel Fross¹ and Ahmad El-Assaad² ¹Technische Universität Chemnitz, DE; ²Novero GmbH, DE Abstract Many modern applications depend on location information. Precision and availability out- and indoor get more and more crucial. Acquisition of this information from radio links used for wireless data transfer is logical step. Link-availability, RSSI, timing or phase shifts are byproducts that carry knowledge about the distance between communication endpoints. Extensive signal processing, advanced receiver setups and statistical algorithms allow the extraction of reliable position information. We present a high performance multichannel SDR platform based on FPGA that allows the quick development of respective technology parts. It is based on KC705-Board connecting a Linux PC via PCIe. Featuring three RF-Frontends (AD-FMCOMM-S3) we are able to control six independent paths time synchronous. With 50 MSa/s at 12 bit resolution a data stream of 7.2 Gbit/s can be processed. We target for radio frequency based vehicle self-localization using smart array antennas. Download Paper (PDF)
UB09.10	UCAF TOOL: AN OPTIMIZATION-BASED DESIGN METHODOLOGY FOR ULTRA-LOW VOLTAGE ANALOG INTEGRATED CIRCUITS Presenter: Lucas Severo, Federal University of Pampa, BR Authors: Lucas Severo¹ and Wilhelmus Noije² ¹Federal University of Pampa, BR; ²University of São Paulo, BR Abstract This work presents an Ultra-Low Voltage (ULV) analog integrated circuit design methodology. This methodology is able to sizing analog circuits using an exploration in design space with Simulated Annealing optimization heuristic and an electrical simulator for the specifications estimation. This exploration includes the analysis of Process, Voltage and Temperature variations in order to reduce the effect of these variations in the circuit specifications. The methodology implementation is optimized to ULV circuits and has several testbenches, making possible to design a large number of circuit topologies. Parallel simulations are used to decrease the execution time. As an application of this methodology a 0.6 V fully differential Operational Transconductance Amplifier (OTA) is designed. In a second time, using a bottom-up approach, an active low pass filter is designed using the previously designed OTA. The filter results is in according with the IEEE 802.15.4 standard requirements. Download Paper (PDF)
12:00	End of session
12:30	Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 13:30 - 14:00

Label

Presentation Title
Authors

UB09.1

AHLS_DESYNC: DESYNCHRONIZATION TOOL FOR HIGH-LEVEL SYNTHESIS OF ASYNCHRONOUS CIRCUITS
Presenter:
Jean Simatic, TIMA Laboratory, FR
Authors:
Jean Simatic, Rodrigo Possamai Bastos and Laurent Fesquet, TIMA Laboratory, FR
Abstract
We present a tool for the high-level synthesis (HLS) of event-driven (asynchronous) circuits. Our approach first uses an existing HLS tool, AUGH, to generate a synchronous finite state machine (FSM) and a data-path. Then, the presented tool desynchronizes solely the FSM in 5 steps: 1. Parse the FSM to build a state graph containing the control signal assignments. 2. Separate multiplexer control and register control signals by analyzing the data-path. 3. Generate an event-driven FSM netlist by mapping the state graph on a dedicated set of asynchronous controllers. 4. Synthesize the data-path thanks to a commercial synthesis tool (Design Compiler). 5. Estimate the delays in the data-path with a static timing analysis tool (PrimeTime). Insert delays in the controller accordingly. Our demonstration will exhibit two testbenches: a GCD algorithm to expose the basic concepts and a non-uniform sampling FIR filter more representative of real-life applications.
Download Paper (PDF)

UB09.2

D-VASIM: TIMING ANALYSIS OF GENETIC LOGIC CIRCUITS USING D-VASIM
Presenter:
Hasan Baig, Technical University of Denmark, DK
Authors:
Hasan Baig and Jan Madsen, Technical University of Denmark, DK
Abstract
A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to control gene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electronic logic circuits, timing and propagation delay analysis may also play a very significant role in the designing of genetic logic circuits. In this demonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagation delay analysis of a single as well as cascaded genetic logic circuits. D-VASim allows user to change the circuit parameters during runtime simulation to observe their effects on circuit's timing behavior. The results obtained from D-VASim can be used not only to characterize the timing behavior of genetic logic circuits but also to analyze the timing constraints of cascaded genetic logic circuits.
Download Paper (PDF)

UB09.3

IN-NODE PROCESSING: MODELLING FRAMEWORK FOR IN-NODE PROCESSING IN INDUSTRIAL SENSOR AND ACTUATOR NETWORKS.
Presenter:
Qaiser Anwar, Mid Sweden University, SE
Authors:
Qaiser Anwar, Muhammad Imran and Mattias O´Nils, Mid Sweden University, SE
Abstract
Architecting efficient systems with on-board sensing capabilities with a growing number of sensing devices is a challenging task, in particular because of the range of the technological field, as well as the diversity and complexity of requirements. We present a novel modeling framework, which can describe different implementation strategies for computation of data locally. In this framework, we first describe the systems in Architecture Analysis and Design Language (AADL), following which the described system is exported to XML which is then given input to java based software program. This program automatically generates different implementation options, illustrates different parameters such as processing energy, communication energy, latency and design complexity. To show a proof-of-concept, we have modelled a real-life system in a modelling framework, which shows that the framework can be of use in automated design space and architecture exploration for in-node processing.
Download Paper (PDF)

UB09.4

FORMAL VERIFICATION OF CLOCK DOMAIN CROSSING USING GATE-LEVEL MODELS OF METASTABLE FLIP-FLOPS
Presenter:
Ghaith Tarawneh, Newcastle University, GB
Authors:
Ghaith Tarawneh, Andrey Mokhov and Alex Yakovlev, Newcastle University, GB
Abstract
We present a first prototype of a gate-level tool that enables simple and intuitive verification of multi-clock designs. The tool's underlying methodology (described in the paper "Formal Verification of Clock Domain Crossing using Gate-level Models of Metastable Flip-Flops" to be presented in the conference) relies on transforming gate-level netlists so that they can reproduce problematic CDC behaviour digitally. Processed netlists can then be passed to formal verification tools to identify and debug CDC faults. The tool is at an early development stage but consists of a functional Verilog parser and CDC transformation functions that can be invoked from the command line. The demo will showcase the tool using simple sender-receiver circuits. Synthesized netlists will be processed by the tool and then fed to a formal verification tool to identify CDC issues (e.g. missing synchronizers, path convergence). Verification output from source and processed netlists will be compared.
Download Paper (PDF)

UB09.5

LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA
Presenter:
Behailu Shiferaw Negash, University of Turku, FI
Authors:
Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen²
¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE
Abstract
There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud.
Download Paper (PDF)

UB09.6

AUTOMATED REFINEMENT OF ANALOG/MIXED-SIGNAL SYSTEMC MODELS BY NON-FUNCTIONAL EFFECTS
Presenter:
Georg Gläser, IMMS, DE
Authors:
Georg Gläser¹, Hyun-Sek Lukas Lee², Eckhard Hennig³, Markus Olbrich² and Erich Barke²
¹IMMS, DE; ²Leibniz Universität Hannover, DE; ³Reutlingen University, DE
Abstract
Virtual prototyping of analog/mixed-signal (A/MS) systems is a key concern in the modern design process. The main challenge is performing the verification of functional properties with respect to non-functional effects, e.g. signal and power integrity. System architects are challenged by identifying critical scenarios where these effects possibly degrade or even destroy the system's functionality. We demonstrate a method to automatically extend an existing functional model by non-functional effects. Combined with an accelerated, piecewise-linear (PWL) simulation scheme (PRAISE), we explore the resulting system acceptance regions and identify critical scenarios.
Download Paper (PDF)

UB09.7

A CIRCUIT EXTRACTION TOOL FOR FULL CUSTOM DESIGNED MEMS SENSORS
Presenter:
Axel Hald, Robert Bosch GmbH, DE
Authors:
Axel Hald¹, Johannes Seelhorst¹, Mathias Reimann¹, Juergen Scheible² and Jens Lienig³
¹Robert Bosch GmbH, DE; ²Reutlingen University, DE; ³Technische Universität Dresden, DE
Abstract
In contrast to IC design, MEMS design still lacks sophisticated component libraries. Therefore, the physical design of today's MEMS sensors is mostly done by simply drawing polygons. Hence, the sensor structure is only given as plain graphic data which hinders the identification and investigation of topology elements. The growing complexity of future MEMS designs demands a deep and detailed analysis of the sensor structures and the topology elements in order to get a better understanding of the coupling capacitances and parasitics. Our tool is able to extract a circuit out of a MEMS sensor designed in a polygon based design flow. The key feature of this tool is a rule based structure recognition algorithm which identifies the topology elements of the sensor. Thereafter, the electrostatic RC-extraction is performed by a commercial field solver. The extracted lumped elements can be used for further simulation and optimization tasks during the design phase.
Download Paper (PDF)

UB09.8

PSMGEN: AUTOMATIC GENERATION OF POWER STATE MACHINES
Presenter:
Alessandro Danese, University of Verona, IT
Authors:
Alessandro Danese¹, Graziano Pravadelli¹ and Daniel Lorenz²
¹University of Verona, IT; ²OFFIS - Institute for Information Technology, DE
Abstract
Power State Machines are a well-known approach to model and simulate the time-based energy consumption of IP cores for early virtual prototyping of SoCs. However, in the most of the works either the presence of PSMs is assumed or they are manually defined starting from a more or less precise knowledge of the functional blocks composing the target IP. To allow a tighter definition of PSMs, we present PSMGen, a tool implementing an automatic methodology for PSMs' generation and an efficient statistical approach for their simulation. The tool requires as input a set of functional traces exposing the IP's behaviours and the corresponding set of power traces over time that represent the golden model of the IP's energy consumption.It then generates PSM's states and transitions through a mining procedure that extracts the IP behaviours from the functional traces, analyses power changes on the power traces and annotate each PSM's state with the corresponding power characterization
Download Paper (PDF)

UB09.9

6CH-SDR-PLATFORM: 6 CHANNEL SDR PROTOTYPING PLATFORM FOR VEHICLE SELF-LOCALIZATION
Presenter:
Marko Rößler, Technische Universität Chemnitz, DE
Authors:
Marko Rößler¹, Ulrich Heinkel¹, Daniel Fross¹ and Ahmad El-Assaad²
¹Technische Universität Chemnitz, DE; ²Novero GmbH, DE
Abstract
Many modern applications depend on location information. Precision and availability out- and indoor get more and more crucial. Acquisition of this information from radio links used for wireless data transfer is logical step. Link-availability, RSSI, timing or phase shifts are byproducts that carry knowledge about the distance between communication endpoints. Extensive signal processing, advanced receiver setups and statistical algorithms allow the extraction of reliable position information. We present a high performance multichannel SDR platform based on FPGA that allows the quick development of respective technology parts. It is based on KC705-Board connecting a Linux PC via PCIe. Featuring three RF-Frontends (AD-FMCOMM-S3) we are able to control six independent paths time synchronous. With 50 MSa/s at 12 bit resolution a data stream of 7.2 Gbit/s can be processed. We target for radio frequency based vehicle self-localization using smart array antennas.
Download Paper (PDF)

UB09.10

UCAF TOOL: AN OPTIMIZATION-BASED DESIGN METHODOLOGY FOR ULTRA-LOW VOLTAGE ANALOG INTEGRATED CIRCUITS
Presenter:
Lucas Severo, Federal University of Pampa, BR
Authors:
Lucas Severo¹ and Wilhelmus Noije²
¹Federal University of Pampa, BR; ²University of São Paulo, BR
Abstract
This work presents an Ultra-Low Voltage (ULV) analog integrated circuit design methodology. This methodology is able to sizing analog circuits using an exploration in design space with Simulated Annealing optimization heuristic and an electrical simulator for the specifications estimation. This exploration includes the analysis of Process, Voltage and Temperature variations in order to reduce the effect of these variations in the circuit specifications. The methodology implementation is optimized to ULV circuits and has several testbenches, making possible to design a large number of circuit topologies. Parallel simulations are used to decrease the execution time. As an application of this methodology a 0.6 V fully differential Operational Transconductance Amplifier (OTA) is designed. In a second time, using a bottom-up approach, an active low pass filter is designed using the previously designed OTA. The filter results is in according with the IEEE 802.15.4 standard requirements.
Download Paper (PDF)

12:00

End of session

12:30

Lunch Break in Großer Saal + Saal 1
Keynote Lecture in "Saal 2" 13:30 - 14:00

Visit us at DATE 2016