Date: Thursday 17 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 2

Chair:
Valeria Bertacco, Univ. of Michigan, US

Co-Chair:
Sven Peyer, IBM, DE

The first paper proposes minimization techniques for Majority-Inverter Graphs. The second paper presents functional rectification taking into account placement information. The third paper combines slack matching gate sizing and repeater insertion to optimize leakage power in asynchronous circuits.

Time	Label	Presentation Title Authors
08:30	9.4.1	OPTIMIZING MAJORITY-INVERTER GRAPHS WITH FUNCTIONAL HASHING Speaker: Mathias Soeken, École Polytechnique Fédérale de Lausanne (EPFL), CH Authors: Mathias Soeken1, Pierre-Emmanuel Gaillardon2, Luca Amaru2 and Giovanni De Micheli2 1University of Bremen, DE; 2École Polytechnique Fédérale de Lausanne (EPFL), CH Abstract A Majority-Inverter Graph (MIG) is a recently introduced logic representation form whose algebraic and Boolean properties allow for efficient logic optimization. In particular, when considering logic depth reduction, MIG algorithms obtained significantly superior synthesis results as compared to the state-of-the-art approaches based on AND-inverter graphs and commercial tools. In this paper, we present a new MIG optimization algorithm targeting size minimization based on functional hashing. The proposed algorithm makes use of minimum MIG representations which are precomputed for functions up to 4 variables using an approach based on Satisfiability Modulo Theories (SMT). Experimental results show that heavily-optimized MIGs can be further minimized also in size, thanks to our proposed methodology. When using the optimized MIGs as starting point for technology mapping, we were able to improve both depth and area for the arithmetic instances of the EPFL benchmarks beyond the current results achievable by state-of-the-art logic synthesis algorithms. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	9.4.2	RESOURCE-AWARE FUNCTIONAL ECO PATCH GENERATION Speaker: Iris Hui-Ru Jiang, National Chiao Tung University, TW Authors: An-Che Cheng1, Iris Hui-Ru Jiang1 and Jing-Yang Jou2 1National Chiao Tung University, TW; 2National Central University, TW Abstract Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	9.4.3	SIMULTANEOUS SLACK MATCHING, GATE SIZING AND REPEATER INSERTION FOR ASYNCHRONOUS CIRCUITS Speaker: Gang Wu, Iowa State University, US Authors: Gang Wu and Chris Chu, Iowa State University, US Abstract Slack matching, gate sizing and repeater insertion are well known techniques applied to asynchronous circuits to improve their power and performance. Existing asynchronous optimization flows typically perform these optimizations sequentially, which may result in sub-optimal solutions as all these techniques are interdependent and affect one another. In this paper, we present a unified leakage power optimization framework by performing simultaneous slack matching, gate sizing and repeater insertion. In particular, we apply Lagrangian relaxation to integrate all these techniques into a single optimization step. A methodology to handle slack matching under the Lagrangian relaxation framework is proposed. Also, an effective look-up table based repeater insertion technique is developed to speed up the algorithm. Our approach is evaluated using a set of asynchronous designs and compared with both a sequential approach and a commercial asynchronous optimization flow. The experimental results have achieved significant savings in leakage power and demonstrated the effectiveness of our approach. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP4-8, 287	SYNTHESIS OF APPROXIMATE CODERS FOR ON-CHIP INTERCONNECTS USING REVERSIBLE LOGIC Speaker: Robert Wille, Johannes Kepler University Linz, AT Authors: Robert Wille1, Oliver Keszocze2, Stefan Hillmich2, Marcel Walter2 and Alberto Garcia-Ortiz3 1Johannes Kepler University Linz, AT; 2University of Bremen, DE; 3ITEM (U.Bremen), DE Abstract On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified and the synthesis algorithm has a higher flexibility to simplify the circuit. Since conventional synthesis methods are unsuitable here, we propose an alternative synthesis approach based on reversible logic. Experimental evaluations confirm the benefits of both, the proposed concept of approximate codings as well as the proposed design method. Download Paper (PDF; Only available from the DATE venue WiFi)
10:01	IP4-9, 310	DESIGN-SYNTHESIS CO-OPTIMISATION USING SKEWED AND TAPERED GATES Speaker: Ankur Shukla, India Systems Development Lab, IBM India, IN Authors: Ayan Datta1, James D. Warnock2, Ankur Shukla1, Saurabh Gupta1, Yiu Hing Chan2, Karthik Mohan1 and Charudhattan Nagarajan1 1India Systems Development Lab, IBM India, IN; 2IBM US, US Abstract This paper presents a novel technique to optimize the design of non-conventional tapered and skewed standard cell gates, and the synthesis algorithms for efficient usage of such gates in IBMs high-performance 22nm CMOS SOI technology. The focus is on design considerations to ensure that synthesis can use these gates efficiently, leveraging the resulting timing improvements for faster timing closure of high-performance microprocessor designs. A detailed analysis is presented, where by exposing these gates to synthesis at different points in the process, the optimal point of insertion is identified. Also an efficient algorithm is proposed to handle decisions regarding the conversion of conventional gates to non-conventional gates, after taking into account multiple factors including delay and slew. Results show 25 - 30% improvement in total negative slack of designs and 20 -25% reduction in the total number of negative paths, without any major impact on total power of the designs. Download Paper (PDF; Only available from the DATE venue WiFi)
10:02	IP4-10, 690	(Best Paper Award Candidate) A SYNTHESIS-PARAMETER TUNING SYSTEM FOR AUTONOMOUS DESIGN-SPACE EXPLORATION Speaker: Matthew Ziegler, IBM T. J. Watson Research Center, US Authors: Matthew Ziegler1, Hung-Yi Liu2, George Gristede1, Bruce Owens3, Ricardo Nigaglioni3 and Luca Carloni2 1IBM T. J. Watson Research Center, US; 2Columbia University, US; 3IBM Systems and Technology Group, US Abstract Advanced logic and physical synthesis tools provide a vast num-ber of tunable parameters that can significantly impact physical design quality, but the complexity of the parameter design space requires intelligent search algorithms. To fully utilize the opti-mization potential of these tools, we propose SynTunSys, a sys-tem that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis-parameter tuning pro-cess, i.e., job submission, results analysis, and next-step decision making, by automating a key portion of a human designer's decision process. We present the overall organization of Syn-TunSys, describe its main components, and provide results from employing it for the design of an industrial chip, the IBM z13 22nm high-performance server chip. During this major design, SynTunSys provided significant savings in human design effort and achieved a quality of results beyond what human designers alone could achieve, yielding on average a 36% improvement in total negative slack and a 7% power reduction. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area