Date: Wednesday 16 March 2016
Time: 14:30 - 16:00
Location / Room: Konferenz 6

Organiser:
Roberto Giorgi, University of Siena, IT

Chair:
Martin Schoeberl, Technical University of Denmark, DK

Co-Chair:
Roberto Giorgi, University of Siena, IT

Energy efficiency is a key non-functional property that is currently a number one goal of many designs. In this session several projects focused on future datacenters are illustrated. The adopted solutions and technologies are driving the design of next energy efficient smart embedded systems too.

Time	Label	Presentation Title Authors
14:30	7.2.1	EUROSERVER: SHARE-ANYTHING SCALE-OUT MICRO-SERVER DESIGN Speaker: Manolis Marazakis, FORTH, GR Authors: Manolis Marazakis1, John Goodacre2, Didier Fuin3, Paul Carpenter4, John Thomson5, Emil Matus6, Antimo Bruno7, Per Stenström8, Jerome Martin9, Yves Durand9 and Isabelle Dor9 1FORTH, GR; 2ARM Ltd, GB; 3STMicroelectronics, FR; 4Barcelona Supercomputing Center, ES; 5ONAPP Ltd, GB; 6Technische Universität Dresden, DE; 7NEAT Srl, IT; 8Chalmers University of Technology, SE; 9CEA, FR Abstract This paper provides a snapshot summary of the trends in the area of micro-server development and their application in the broader enterprise and cloud markets. Focusing on the technology aspects, we provide an understanding of these trends and specifically the differentiation and uniqueness of the approach being adopted by the EUROSERVER FP7 project. The unique technical contributions of EUROSERVER range from the fundamental system compute unit design architecture, through to the implementation approach both at the chiplet nanotechnological integration, and the everything-close physical form factor. Furthermore, we offer optimizations at the virtualisation layer to exploit the unique hardware features, and other framework optimizations, including exploiting the hardware capabilities at the run-time system and application layers. Download Paper (PDF; Only available from the DATE venue WiFi)
14:45	7.2.2	ENERGY MINIMIZATION AT ALL LAYERS OF THE DATA CENTER: THE PARADIME PROJECT Speaker: Christof Fetzer, Technische Universität Dresden, DE Authors: Oscar Palomar1, Santhosh Kumar Rethinagiri2, Gulay Yalcin1, Rubén Titos-Gil1, Pablo Prieto1, Emma Torrella1, Osman Unsal1, Adrián Cristal1, Pascal Felber3, Anita Sobe3, Yaroslav Hayduk3, Mascha Kurpicz3, Christof Fetzer4, Thomas Knauth4, Malte Schneegaß5, Jens Struckmeier5 and Dragomir Milojevic6 1Barcelona Supercomputing Center, ES; 2BSC-Microsoft Research Center, ES; 3University of Neuchâtel, CH; 4Technische Universität Dresden, DE; 5Cloud & Heat, DE; 6IMEC, BE Abstract The main objective of the ParaDIME project has been to minimize energy consumption at all levels of the data center. On the one hand, we have considered what can be achieved on currently existing systems, via improvements of the programming model and the runtime system. On the other hand, we investigated which techniques and design decisions can make future computing nodes more energy efficient. We have successfully proposed and developed several methodologies that enable up to 60% energy savings in data center's components. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	7.2.3	RACK-SCALE DISAGGREGATED CLOUD DATA CENTERS: THE DREDBOX PROJECT VISION Speaker: Dimitris Syrivelis, University of Thessaly, GR Authors: Kostas Katrinis1, Dimitris Syrivelis2, Dionisios Pnevmatikatos3, Georgios Zervas4, Dimitris Theodoropoulos5, Iordanis Koutsopoulos6, Kobi Hasharoni7, Daniel Raho8, Christian Pinto8, Felix Espina9, Sergio Lopez-Buedo9, Qianqiao Chen4, Mario Nemirovsky10, Damian Roca10, Hans Klos11 and Tom Berends11 1IBM Research Ireland, IE; 2University of Thessaly, GR; 3ECE Department, Technical Univrsity of Crete & FORTH-ICS, GR; 4HPN group, University of Bristol, GB; 5Foundation for Research and Technology Hellas (FORTH), GR; 6Athens University of Economics and Business, GR; 7Compass-EOS, IL; 8Virtual Open Systems, FR; 9NAUDIT HPCN, ES; 10Barcelona Supercomputing Center, ES; 11SINTECS, NL Abstract For quite some time now, computing systems servers, whether low-power or high-end ones designs are created around a common design principle:the main-board and its hardware components form a baseline, monolithic building block that the rest of the hardware/software stack design builds upon. This proportionality of compute/memory/network/storage resources is fixed during design time and remains static throughout machine lifetime, with known ramifications in terms of low system resource utilization, costly upgrade cycles and degraded energy proportionality. dReDBox takes on the challenge of revolutionizing the low-power computing market by breaking server boundaries through materialization of the concept of disaggregation. Besides proposing a highly modular software-defined architecture for the next generation datacentre, dRedBox will specify, design and prototype a novel hardware architecture where SoC-based microservers, memory modules and accelerators, will be placed in separated modular server trays interconnected via a high-speed, low-latency opto-electronic system fabric, and be allocated in arbitrary sets, as driven by fit-for-purpose resource/power management software. These blocks will employ state-of-the-art low-power components and be amenable to deployment in various integration form factors and target scenarios. dRedBox aims to deliver a full-fledged, vertically integrated datacentre-in-a-box prototype to showcase the superiority of disaggregation in terms of scalability, efficiency, reliability, performance and energy reduction which will be demonstrated in three pilot use-cases. Download Paper (PDF; Only available from the DATE venue WiFi)
15:15	7.2.4	ECOSCALE: RECONFIGURABLE COMPUTING AND RUNTIME SYSTEM FOR FUTURE EXASCALE SYSTEMS Speaker: Iakovos Mavroidis, Telecommunication Systems Institute, GR Authors: Iakovos Mavroidis1, Ioannis Papaefstathiou2, Luciano Lavagno3, Dimitrios Nikolopoulos4, Dirk Koch5, John Goodacre5, Ioannis Sourdis6, Vassilis Papaefstathiou6, Marcello Coppola7 and Manuel Palomino8 1Telecommunication Systems Institute, GR; 2Synelixis, GR; 3Politecnico di Torino, IT; 4Queen's University of Belfast, GB; 5University of Manchester, GB; 6Chalmers University of Technology, SE; 7STMicroelectronics, FR; 8Acciona Infraestructuras S.A., ES Abstract In order to reach exascale performance, current HPC systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development flow as well as the system architecture of future HPC systems. ECOSCALE tackles these challenges by proposing a scalable programming environment and architecture, aiming to substantially reduce energy consumption as well as data traffic and latency. ECOSCALE introduces a novel heterogeneous energy-efficient hierarchical architecture, as well as a hybrid many-core+OpenCL programming environment and runtime system. The ECOSCALE approach is hierarchical and is expected to scale well by partitioning the physical system into multiple independent Workers (i.e. compute nodes). Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of Partitioned Global Address Space (PGAS) partitions, or as a set of nodes hierarchically interconnected via an MPI protocol. To further increase energy efficiency, as well as to provide resilience, the Workers employ reconfigurable accelerators mapped into the virtual address space utilizing a dual stage System Memory Management Unit with coherent memory access. The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming model. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	7.2.5	ENABLING HPC FOR QOS-SENSITIVE APPLICATIONS: THE MANGO APPROACH Speaker: José Flich, Universitat Politècnica de València, ES Authors: José Flich1, Giovanni Agosta2, Philipp Ampletzer3, David Atienza4, Alessandro Cilardo5, William Fornaciari2, Ynse Hoornengorb6, Mario Kovac7, Bruno Maitre8, Giuseppe Massari2, Ermis Papastefanakis8, Fabrice Roudet9, Rafael Tornero1 and Davide Zoni2 1Universitat Politècnica de València, ES; 2Politecnico di Milano, IT; 3ProDesign, DE; 4École Polytechnique Fédérale de Lausanne (EPFL), CH; 5University of Naples Federico II, IT; 6Philips Medical, NL; 7Zagreb University, HR; 8Thales Communication, FR; 9EATON, FR Abstract In this paper, we provide an overview of the MANGO project and its goal. The MANGO project aims at addressing power, performance and predictability (the PPP space) in future High-Performance Computing systems. It starts from the fundamental intuition that effective techniques for all three goals ultimately rely on customization to adapt the computing resources to reach the desired Quality of Service (QoS). From this starting point, MANGO will explore different but interrelated mechanisms at various architectural levels, as well as at the level of the system software. In particular, to explore a new positioning across the PPP space, MANGO will investigate system-wide, holistic, proactive thermal and power management aimed at extreme-scale energy efficiency. Download Paper (PDF; Only available from the DATE venue WiFi)
15:45	7.2.6	AUTOTUNING AND ADAPTIVITY APPROACH FOR ENERGY EFFICIENT EXASCALE HPC SYSTEMS: THE ANTAREX APPROACH Speaker: Cristina Silvano, Politecnico di Milano, IT Authors: Cristina Silvano1, Giovanni Agosta1, Andrea Bartolini2, Andrea Beccari3, Luca Benini2, João Bispo4, João M. P. Cardoso5, Carlo Cavazzoni6, Jan Martinovic7, Gianluca Palermo1, Martin Palkovic7, Pedro Pinto8, Erven Rohou9, Nico Sanna6 and Katerina Slaninova7 1Politecnico di Milano, IT; 2Università di Bologna, IT; 3Dompe' Farmaceutici SpA, IT; 4Faculty of Engineering (FEUP), University of Porto, PT; 5University of Porto, PT; 6CINECA, IT; 7IT4Innovation National Supercomputing Center, CZ; 8Faculty of Engineering, University of Porto, PT; 9INRIA Rennes, FR Abstract The main goal of the ANTAREX project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, perfor- mance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00	IP3-7, 1023	TECHNOLOGY TRANSFER IN COMPUTING SYSTEMS: THE TETRACOM APPROACH Speaker and Author: Rainer Leupers, RWTH Aachen University, DE Abstract TETRACOM is an ongoing EU FP7 Coordination Action with the ambition to boost small to medium scale academia-to-industry technology transfer in all domains of computing systems. The project primarily operates via competitive open calls for individual Technology Transfer Projects (TTPs). Each TTP performs a well-defined bilateral transfer activity between one European academic partner and one industry partner. TETRACOM coordinates all TTPs and provides technology transfer advice and co-funding. This paper describes TETRACOM´s experimental concept and project structure. It summarizes preliminary lessons learned after more than two project years and successful management of 30+ individual TTPs. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00		End of session Coffee Break in Exhibition Area