Date: Wednesday 16 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 2

Chair:
Alberto Garcia Ortiz, University of Bremen, DE

Co-Chair:
Qi Zhu, UCR, US

Papers in this session address methods for power efficient design of digital systems. The first paper presents an FPGA emulation for design trade-offs. The second paper proposes a methodology to automatically generate power state machine models for SoCs. The third paper presents an automatic method to place isolation gates trading off precision and power dissipation. The IP paper investigates circuit verification of power grids.

Time	Label	Presentation Title Authors
11:00	6.4.1	A SYSTEMATIC APPROACH TO AUTOMATED CONSTRUCTION OF POWER EMULATION MODELS Speaker: Benjamin Andreassen Bjørnseth, Norwegian University of Science and Technology, NO Authors: Benjamin Andreassen Bjørnseth, Asbjørn Djupdal and Lasse Natvig, Norwegian University of Science and Technology, NO Abstract Efficient estimation of power consumption is vital when designing large digital systems. The technique called power emulation can speed up estimation by implementing power models alongside a design on an FPGA. Current state-of-the-art power emulation methods construct models using various custom techniques, but there is no study on how the existing methods relate to each other nor how their differences impact the final quality of the model. We propose a methodology which describes the breadth of current approaches to automated construction of power emulation models. We also evaluate the current methods, finding that there is significant variation in accuracy and complexity. In 32.8 % of all tests, the average accuracy of the least complex method is better than that of the most advanced method at less than 0.3 % the hardware overhead. This result fuels the hope that further innovation may yield models with high accuracy at low implementation cost. Our software frameworks and experimental data are made available to promote continued work on the field. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	6.4.2	AUTOMATIC GENERATION OF POWER STATE MACHINES THROUGH DYNAMIC MINING OF TEMPORAL ASSERTIONS Speaker: Graziano Pravadelli, University of Verona, IT Authors: Alessandro Danese, Ivan Zandonà and Graziano Pravadelli, University of Verona, IT Abstract Several papers propose approaches based on power state machines (PSMs) for modelling and simulating the power consumption of system-on-chips (SoCs). However, while they focus on the use of PSMs as the underlying formalism for imple- menting dynamic power management techniques, they generally do not deal with the basic problem of generating PSMs. In most of these papers, PSMs just exist, in some cases they are manually defined, and only a few approaches give a hint of semi-automatic generation, but no fully-automatic approach exists in the literature. Indeed, without an automatic procedure, an accurate power characterization of complex SoCs by using PSMs is almost impossible. Thus, in this paper, first a methodology for the automatic generation of PSMs is proposed, and then, a statistical approach based on a Hidden Markov Model is presented for their simulation. The core of the approach is based on a mining procedure whose role consists of extracting temporal assertions describing the functional behaviours of the IP, which are then automatically mapped on states of the PSMs and characterized from the energy consumption point of view. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	6.4.3	APPROXIMATION THROUGH LOGIC ISOLATION FOR THE DESIGN OF QUALITY CONFIGURABLE CIRCUITS Speaker: Shubham Jain, Purdue University, US Authors: Shubham Jain, Swagath Venkataramani and Anand Raghunathan, Purdue University, US Abstract Intrinsic application resilience, a property exhibited by many emerging application domains, allows designers to optimize computing platforms by approximating selected computations within an application without any perceivable loss in its output quality. At the circuit level, this is often achieved by designing circuits that are more efficient but realize slightly modified functionality. Most prior efforts on approximate circuit design hardwire the degree of approximation into the implementation. This severely limits their applicability, as intrinsic resilience significantly varies both across and within applications, and often the same computation needs to be executed at different levels of accuracy when the application processes a different input or used in a different context. To address this limitation, in this work, we propose a new approach to design quality configurable circuits that are equipped to modulate their output accuracy and energy at runtime. Our approach, approximation through logic isolation, identifies portions of logic in the circuit that consume significant power, but contribute only minimally to output accuracy. One or more approximate modes of circuit operation are then enabled by isolating the identified logic (using muxes, latches or power gating cells) to benefit power while satisfying the desired output accuracy. We propose a systematic methodology to transform a given circuit into a quality-configurable circuit by applying the proposed technique. Our methodology generates a favorable energy-quality trade-off by deliberately creating opportunities for error compensation between multiple logic islands that are simultaneously isolated. This enables more aggressive approximation for a given output quality, leading to a superior power benefits. We evaluate the proposed methodology using a wide range of arithmetic circuits, complex modules and datapaths. The synthesized quality configurable circuits support 3 quality modes viz. accurate, <0.1% average error, and <0.2% average error. Power improvements achieved in the approximate modes are 8.4%-34.5% and 17%-51.5%, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	IP3-2, 297	ACCURATE VERIFICATION OF RC POWER GRIDS Speaker: Mohammad Fawaz, University of Toronto, CA Authors: Mohammad Fawaz and Farid N. Najm, University of Toronto, CA Abstract The power distribution network (PDN) of an integrated circuit (IC) must undergo various checks throughout the design flow, in order to guarantee that the voltage fluctuations are within certain user-specified safety thresholds. Vectorless verification of the PDN is one approach for verification that requires little information about the on-die logic. This verification problem has been studied extensively over the past few years and has been generally solved by first discretizing time using a particular user-defined time-step. We investigate the effect of this time-step on the quality of the solutions produced (both exact and estimates). We also propose an efficient method to specify the time-step in a way to minimize the errors introduced by the voltage drop estimates. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 14:00 - 14:30