Date: Tuesday 15 March 2016
Time: 17:00 - 18:30
Location / Room: Konferenz 3

Chair:
Fabien Clermidy, CEA-Leti, FR

Co-Chair:
Walter Weber, Namlab, DE

This session explores the use of emerging memory devices for energy efficiency. The first paper proposes a compact SRAM design employing silicon-based tunnel FETs. A new type of tunneling device is also used in the second paper to build circuits designs of flip-flops and latches. Finally, an energy saving system integration of non-volatile ternary content addressable memory cells is presented in the third paper.

Time	Label	Presentation Title Authors
17:00	4.5.1	3T-TFET BITCELL BASED TFET-CMOS HYBRID SRAM DESIGN FOR ULTRA-LOW POWER APPLICATIONS Speaker: Costin Anghel, Institut Supérieur d'électronique de Paris (ISEP), FR Authors: Navneet Gupta1, Adam Makosiej2, Andrei Vladimirescu3, Amara Amara3 and Costin Anghel3 1Institut Supérieur d'Électronique de Paris (ISEP) and CEA-Leti, FR; 2CEA-Leti, FR; 3Institut Supérieur d'Électronique de Paris (ISEP), FR Abstract This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance from 4Kb SRAM designed in 28nm FDSOI CMOS process using MOSFETs & Tunnel FETs (TFETs). The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. A 0.35 fA/bit memory array leakage current was achieved showing a 14x to 10000x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells. Minimum read and write access pulse is evaluated at 1.27ns at sub-1V supply voltage. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	4.5.2	DESIGN OF LATCHES AND FLIP-FLOPS USING EMERGING TUNNELING DEVICES Speaker: Xunzhao Yin, University of Notre Dame, US Authors: Xunzhao Yin, Behnam Sedighi, Michael Niemier and Xiaobo Sharon Hu, University of Notre Dame, US Abstract Tunneling field-effect transistors (TFETs) stand out among novel device technologies for low-power circuits and systems. While some TFETs exhibits behavior similar to MOSFETs, a group of emerging tunneling devices including symmetric tunneling FETs (SymFETs) and interlayer tunnel FETs (IFETs) demonstrate a bell-shaped I-V characteristic dissimilar to that of MOSFETs. They have shown the potential for image processing and nontraditional computing in analog applications and the design of Boolean gates with SymFETs has also been explored. This paper uses a SymFET as a proxy to design sequential circuits comprised of devices with bell-shaped I-V characteristics. Said circuits are essential as practically any application requires the indefinite storage of data and control modules during computation. We show that the negative differential resistance (NDR) behavior of SymFET transistors can be employed to build compact and low power latches and flip-flops. The relationship of SymFET with another well-known tunneling device, namely resonant tunneling diode (RTD), is investigated. We illustrate how previous research on RTD-based circuits -- such as monostable-bistable (MOBILE) self-latching circuits and highly compact MOBILE-based D flip-flop circuits -- can be adopted to SymFETs. Our paper provides a novel path of circuit designs based on devices that have characteristics similar to SymFETs and shows that SymFETs are a promising option for image processing applications in terms of power and area. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	4.5.3	MASC: ULTRA-LOW ENERGY MULTIPLE-ACCESS SIGNLE-CHARGE TCAM FOR APPROXIMATE COMPUTING Speaker: Tajana Rosing, UC San Diego, US Authors: Mohsen Imani1, Shruti Patil1 and Tajana Rosing2 1UC San Diego, US; 2University of California, San Diego, US Abstract Memory-based computing using associative memory has emerged as a promising solution to reduce the energy consumption of important classes of streaming applications such as multimedia by avoiding redundant computations. In associative memory, a set of frequent patterns that represent basic functions are pre-stored in ternary content addressable memory (TCAM) and reused. The primary limitation to using associative memory in modern parallel processors is the large search energy required by TCAMs. In TCAMs, all match rows, except hit rows, precharge and discharge in every search operation, resulting in high and undesirable energy consumption. In this paper, we propose a new multiple-access single-charge (MASC) TCAM architecture which is capable of searching TCAM contents multiple times with a single precharging cycle. In contrast to previous designs, the MASC TCAM keeps the match-line voltage of all miss-rows high and uses their charge for the next search operation, while only the hit rows discharge. We use a periodic refresh scheme to guarantee the accuracy of the search. We also implement a new type of approximate associative memory by setting longer refresh times for MASC TCAMs, which yields search results within 1-2 bit Hamming distances of the exact result. Our evaluation on AMD Southern Island GPU shows that using MASC associative memory can improve the average GPGPU energy efficiency by 36.6%, 40.2% and 39.4% for exact matching, selective 1-HD and 2-HD approximations respectively, with acceptable quality of service (PSNR>30dB). These energy savings are 1.8X and 1.6X higher than GPGPU using exact matching TCAM and approximation TCAM that uses voltage overscaling, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session