4.2 Hot Topic: Nanoelectronic Design Tools Addressing Coupled Problems for 3D-IC Integration

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Date: Tuesday 15 March 2016
Time: 17:00 - 18:30
Location / Room: Konferenz 6

Organisers:
Caren Tischendorf, Humboldt University of Berlin, DE
Jan ter Maten, University of Wuppertal, DE

Chair:
Wim Schoenmaker, Magwel NV, Leuven, BE

Co-Chair:
Caren Tischendorf, Humboldt University of Berlin, DE

The 3D-IC integration involves strong feedback coupled problems caused by electrical proximity and heat dissipation as well as new design challenges due to immense variety and complexity. New sophisticated modeling and simulation techniques are required in order to facilitate robust designs and enable complex analyses. Within a special hot-topic session, speakers from industry (NXP, ACCO Semiconductor), CAD tool vendors (MAGWEL NV, ON Semiconductor Belgium) and research institutions (University of Wuppertal, TU Darmstadt, Humboldt University of Berlin, Max Planck Institute for Dynamics of Complex Technical Systems, University of Applied Sciences Upper Austria) shall present new jointly developed CAD tools enabling coupled electromagnetic field-circuit-heat simulations, coupled electro-thermal-stress analyses as well as aging effect predictions based on enhanced, parameterized model order reduction techniques, multirate methods, monolithic field-circuit modeling, holistic electro-thermal modeling and uncertainty quantification via adapted probability distributions.

TimeLabelPresentation Title
Authors
17:004.2.1FAST TIME DOMAIN SIMULATION FOR RELIABLE FAULT DETECTION
Speaker:
Jos J. Dohmen, NXP Semiconductors, NL
Authors:
Bratislav Tasic1, Jos J. Dohmen1, Rick Janssen1, E. Jan W. ter Maten2, Theo J.G. Beelen3 and Roland Pulch4
1NXP Semiconductors, NL; 2Bergische Universität Wuppertal, DE; 3Eindhoven University of Technology, NL; 4Ernst-Moritz-Arndt-Universität Greifswald, DE
Abstract
Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

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17:224.2.2HOLISTIC COUPLED FIELD AND CIRCUIT SIMULATION
Speaker:
Christian Strohm, Humboldt University of Berlin, DE
Authors:
Peter Meuris1, Wim Schoenmaker1, Christian Strohm2 and Caren Tischendorf2
1Magwel NV, Leuven, BE; 2Humboldt University of Berlin, DE
Abstract
Circuit simulators used in semiconductor industry are based on lumped element models described in form of net lists. In order to be able to incorporate the mutual electromagnetic influence of neighboring elements (e.g. cross talking), one needs refined models based on a sufficiently exact discretization of the full Maxwell equations. Here, we present a holistic simulation approach for lumped circuit models including 3D electromagnetic field models for specific devices.

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17:444.2.3MODEL ORDER REDUCTION FOR NANOELECTRONICS COUPLED PROBLEMS WITH MANY INPUTS
Speaker:
Nicodemus Banagaaya, Max Planck Institute for Dynamics of Complex Technical Systems, DE
Authors:
Nicodemus Banagaaya1, Lihong Feng1, Wim Schoenmaker2, Peter Meuris2, Aarnout Wieers3, Renaud Gillon3 and Peter Benner1
1Max Planck Institute for Dynamics of Complex Technical Systems, DE; 2Magwel NV, Leuven, BE; 3ON Semiconductor, BE
Abstract
This paper is concerned with Model Order Reduction (MOR) for nanoelectronics coupled problems with many inputs. Our main applications are electro-thermal coupled problems described by nonlinear quadratic differential-algebraic systems (DAEs). We present algorithms that combine the advantages of the splitting techniques for DAEs and the existing MOR methods for systems with many inputs such as sparse implicit projection (SIP) for RC/RLC networks and MOR based on the superposition principle.

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18:064.2.4SHAPE OPTIMIZATION OF A POWER MOS DEVICE TRANSISTOR UNDER UNCERTAINTIES
Speaker:
Piotr Putek, Bergische Universität Wuppertal, DE
Authors:
Piotr Putek1, Peter Meuris2, Roland Pulch3, E. Jan W. ter Maten1, Michael Günther1, Wim Schoenmaker2, Frederik Deleu4 and Aarnout Wieers4
1Bergische Universität Wuppertal, DE; 2Magwel NV, Leuven, BE; 3Ernst-Moritz-Arndt-Universität Greifswald, DE; 4ON Semiconductor, BE
Abstract
Abstract—In this paper we focus on a shape/topology optimization problem of a power MOS transistor under geometrical and material uncertainties to reduce the current density overshoot. This problem, occurring in the automotive industry, yields a stochastic electro-thermal coupled problem. Its solution enables to investigate the propagation of uncertainties through a 3-D model, which affect yield and performance of a power transistor. In our work, the Stochastic Collocation Method (SCM) has been used for this purpose. In particular, uncertainties, which result from imperfections of an industrial production, are modeled by random variables with known a priori probability density distributions, for example, a Gaussian or uniform type. Then, the Polynomial Chaos Expansion (PCE) with the basis associated to the assumed distribution can be used to construct numerical methods for a stochastic representation of the random-dependent solutions. Furthermore, this optimization is formulated in terms of statistical moments such as the mean and the variance. The gradient directions of a bi-objective cost functional is calculated using the Continuum Design Shape Sensitivity and the PCE in conjunction with the SCM. Finally, the optimization results for a relevant nanoelectronics problem demonstrate that the proposed method is robust and efficient.

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18:30End of session