Date: Tuesday 15 March 2016
Time: 14:30 - 16:00
Location / Room: Konferenz 3

Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Co-Chair:
Aida Todri-Sanial, LIRMM, FR

This session explores how new devices can be used to build energy efficient systems. The first paper presents a novel simultaneously bi-directional TSV technology, promising area and energy benefits. The second paper presents programmable logic circuit designs based on nanowire transistors. The last paper examines how inherent characteristics of reversible logic circuits can be exploited to check combinational equivalence in faster ways.

Time	Label	Presentation Title Authors
14:30	3.5.1	ENABLING SIMULTANEOUSLY BI-DIRECTIONAL TSV SIGNALING FOR ENERGY AND AREA EFFICIENT 3D-ICS Speaker: Sunghyun Park, Massachusetts Institute of Technology (MIT), US Authors: Sunghyun Park1, Alice Wang2, Uming Ko2, Li-Shiuan Peh1 and Anantha Chandrakasan1 1Massachusetts Institute of Technology (MIT), US; 2MediaTek Inc., US Abstract This paper presents an analytic and experimental study on a simultaneously bi-directional (SBD) TSV interconnect capable of energy and area efficient 3D-IC vertical signaling. We first explore TSV channel characteristics that differ from well-known off-chip channel properties, then analyze circuit design tradeoffs for SBD TSV signaling in terms of energy, bandwidth and noise margin. Based on this analysis, we propose a novel SBD TSV signaling circuit optimized for our system-level design goals and given TSV technology. Measurement results on a 28nm CMOS test chip show that the proposed SBD TSV interconnect enables 10.3-31.1% lower energy at 34.4% less area than equivalent two uni-directional TSVs. Although our single SBD TSV has 12.5% lower bandwidth than two uni-directional TSVs, the SBD TSV can support up to 9.1Gb/s/TSV bi-directional signaling (i.e. 4.55GHz maximum clock speed) at 1.05V. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	3.5.2	RECONFIGURABLE NANOWIRE TRANSISTORS WITH MULTIPLE INDEPENDENT GATES FOR EFFICIENT AND PROGRAMMABLE COMBINATIONAL CIRCUITS Speaker: Jens Trommer, Namlab gGmbH, DE Authors: Jens Trommer1, Michael Raitza2, André Heinzig2, Tim Baldauf2, Marcus Völp2, Thomas Mikolajick3 and Walter Weber4 1Namlab gGmbH, DE; 2Technische Universität Dresden, DE; 3NaMLab Gmbh / TU Dresden, DE; 4NaMLab gGmbH and CfAED, DE Abstract We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors in series. This leads to topological differences and increased flexibility in circuit design. We found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type. This can be exploited to directly map reconfigurable building blocks, e.g. dynamically switching NAND to NOR. Exemplary 6 functional logic circuits will be shown, which exhibit up to 80% reduction in transistor count, while maintaining the same functionality as compared to the CMOS reference design. Logical effort analysis indicates that 20% less circuit delay and 33% less normalized dynamic power consumption can be achieved. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	3.5.3	EXPLOITING INHERENT CHARACTERISTICS OF REVERSIBLE CIRCUITS FOR FASTER COMBINATIONAL EQUIVALENCE CHECKING Speaker: Luca Amaru, École Polytechnique Fédérale de Lausanne (EPFL), CH Authors: Luca Amaru1, Pierre-Emmanuel Gaillardon2, Robert Wille3 and Giovanni De Micheli1 1École Polytechnique Fédérale de Lausanne (EPFL), CH; 2University of Utah, US; 3Johannes Kepler University Linz, AT Abstract Reversible circuits implement invertible logic functions. They are of great interest to cryptography, coding theory, interconnect design, computer graphics, quantum computing, and many other fields. As for conventional circuits, checking the combinational equivalence of two reversible circuits is an important but difficult (coNP-complete) problem. In this work, we present a new approach for solving this problem significantly faster than the state-of-the-art. For this purpose, we exploit inherent characteristics of reversible computation, namely bi-directional (invertible) execution and the XOR-richness of reversible circuits. Bi-directional execution allows us to create an identity miter out of two reversible circuits to be verified, which naturally encodes the equiv- alence checking problem in the reversible domain. Then, the abundant presence of XOR operations in the identity miter enables an efficient problem mapping into XOR-CNF satisfiability. The resulting XOR-CNF formulas are eventually more compact than pure CNF formulas and potentially easier to solve. As previously anticipated, experimental results show that our equivalence checking methodology is more than one order of magnitude faster, on average, than the state-of-the-art solution based on established CNF-formulation and standard SAT solvers. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00	IP1-15, 515	LOSSLESS COMPRESSION ALGORITHM BASED ON DICTIONARY CODING FOR MULTIPLE E-BEAM DIRECT WRITE SYSTEM Speaker: Pei-Chun Lin, National Taiwan University, TW Authors: Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang and Charlie Chung-Ping Chen, National Taiwan University, TW Abstract Electron-beam direct-write (EBDW) lithography is an attractive candidate of next-generation lithography in advanced semiconductor processes. The huge data stream bandwidth required for the data delivery path in EBDW systems could seriously deteriorate throughput, which is one of the major deficiencies constraining EBDW lithography from mass production. A lossless electron-beam layout data compression and decompression algorithm is proposed in this paper for 5-bit gray level bitmaps. Compared with the state-of-the-art LineDiff Entropy algorithm, the proposed method averagely improves the compression rate by 18% and achieves more than 7.5 times speedup for decompression. Download Paper (PDF; Only available from the DATE venue WiFi)
16:01	IP1-16, 283	PHONOCMAP: AN APPLICATION MAPPING TOOL FOR PHOTONIC NETWORKS-ON-CHIP Speaker: Edoardo Fusella, University of Naples Federico II, IT Authors: Edoardo Fusella and Alessandro Cilardo, University of Naples Federico II, IT Abstract While providing a promising solution for high-performance on-chip communication, photonic networks-on-chip suffer from insertion loss and crosstalk noise, which may severely constrain their scalability. In this paper, we introduce a methodology and a related tool, PhoNoCMap, for the design space exploration of optical NoCs mapping solutions, which automatically assigns application tasks to the nodes of a generic photonic NoC architecture such that the worst-case either insertion loss or crosstalk noise are minimized. The experimental results show significant benefits in terms of insertion loss and crosstalk noise, allowing improved network scalability. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00		End of session Coffee Break in Exhibition Area