Date: Tuesday 15 March 2016
Time: 14:30 - 16:00
Location / Room: Konferenz 2

Chair:
Sheldon X.-D. Tan, University of California at Riverside, US

Co-Chair:
Masaaki Kondo, University of Tokyo, JP

This session introduces power and energy management technics that are tailed for application-specific characteristics. The first paper introduces how simplified neurons without a multiplier can perform in artificial neural networks. The second paper again demonstrates power saving of artificial neural networks with a novel hybrid SRAM cells. The third paper introduces network-aware energy management for mobile applications.

Time	Label	Presentation Title Authors
14:30	3.4.1	MULTIPLIER-LESS ARTIFICIAL NEURONS EXPLOITING ERROR RESILIENCY FOR ENERGY-EFFICIENT NEURAL COMPUTING Speaker: Syed Shakib Sarwar, Purdue University, US Authors: Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan and Kaushik Roy, Purdue University, US Abstract Large-scale artificial neural networks have shown significant promise in addressing a wide range of classification and recognition applications. However, their large computational requirements stretch the capabilities of computing platforms. The fundamental components of these neural networks are the neurons and its synapses. The core of a digital hardware neuron consists of multiplier, accumulator and activation function. Multipliers consume most of the processing energy in the digital neurons, and thereby in the hardware implementations of artificial neural networks. We propose an approximate multiplier that utilizes the notion of computation sharing and exploits error resilience of neural network applications to achieve improved energy consumption. We also propose Multiplier-less Artificial Neuron (MAN) for even larger improvement in energy consumption and adapt the training process to ensure minimal degradation in accuracy. We evaluated the proposed design on 5 recognition applications. The results show, 35% and 60% reduction in energy consumption, for neuron sizes of 8 bits and 12 bits, respectively, with a maximum of ~2.83% loss in network accuracy, compared to a conventional neuron implementation. We also achieve 37% and 62% reduction in area for a neuron size of 8 bits and 12 bits, respectively, under iso-speed conditions. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	3.4.2	SIGNIFICANCE DRIVEN HYBRID 8T-6T SRAM FOR ENERGY-EFFICIENT SYNAPTIC STORAGE IN ARTIFICIAL NEURAL NETWORKS Speaker: Syed Shakib Sarwar, Purdue University, US Authors: Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal and Kaushik Roy, Purdue University, US Abstract Multilayered artificial neural networks have found widespread utility in classification and recognition applications. The scale and complexity of such networks together with the inadequacies of general purpose computing platforms have led to a significant interest in the development of efficient hardware implementations. In this work, we focus on designing energy-efficient on-chip storage for the synaptic weights, motivated primarily by the observation that the number of synapses is orders of magnitude larger than the number of neurons. Typical digital CMOS implementations of such large-scale networks are power hungry. In order to minimize the power consumption, the digital neurons could be operated reliably at scaled voltages by reducing the clock frequency. On the contrary, the on-chip synaptic storage designed using a conventional 6T SRAM is susceptible to bitcell failures at reduced voltages. However, the intrinsic error resiliency of neural networks to small synaptic weight perturbations enables us to scale the operating voltage of the 6T SRAM. Our analysis on a widely used digit recognition dataset indicates that the voltage can be scaled by 200 mV from the nominal operating voltage (950 mV) for practically no loss (less than 0.5%) in accuracy (22 nm predictive technology). Scaling beyond that causes substantial performance degradation owing to increased probability of failures in the MSBs of the synaptic weights. We, therefore propose a significance driven hybrid 8T-6T SRAM, wherein the sensitive MSBs are stored in 8T bitcells that are robust at scaled voltages due to decoupled read and write paths. In an effort to further minimize the area penalty, we present a synaptic-sensitivity driven hybrid memory architecture consisting of multiple 8T-6T SRAM banks. Our circuit to system-level simulation framework shows that the proposed synaptic-sensitivity driven architecture provides a 30.91% reduction in the memory access power with a 10.41% area overhead, for less than 1% loss in the classification accuracy. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	3.4.3	NETWORK DELAY-AWARE ENERGY MANAGEMENT FOR MOBILE SYSTEMS Speaker: Soontae Kim, Korea Advanced Institute of Science and Technology, KR Authors: Minho Ju, Hyeonggyu Kim and Soontae Kim, Korea Advanced Institute of Science and Technology, KR Abstract Smartphones and tablets have occupied the every facet of our daily life in recent years. According to a recent survey, users spend over 3 hours a day on their mobile devices. In addition, 76% and 75% of smartphone users perform web browsing and social networking at least once a day, respectively. To fully enjoy their benefits, those mobile systems require a long battery life. However, network errors such as packet losses decrease the battery life more quickly. We analyzed the reason for this through measurements using real smartphones and mobile full system simulation. We found that the smartphones maintain high performance level on packet losses without doing useful work. To address this problem, we propose a method for reducing energy consumption by lowering down performance level with a Dynamic Voltage and Frequency Scaling mechanism when long network delay is expected due to packet losses. Experimental results show that the total energy consumption is reduced by 8.4% without performance loss. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00	IP1-14, 635	BEHAVIORAL MODELING OF TIMING SLACK VARIATION IN DIGITAL CIRCUITS DUE TO POWER SUPPLY NOISE Speaker: Taesik Na, Georgia Institute of Technology, US Authors: Taesik Na and Saibal Mukhopadhyay, Georgia Institute of Technology, US Abstract Timing error due to power supply noise (PSN) is a key challenge for design of digital systems. This paper presents an accurate time-domain behavioral model of timing slack variation due to the PSN while accounting for the clock-data compensation (CDC). The accuracy of the model is verified against SPICE for complex designs including AES engine and LEON3 processor. As a case study, the model is used for time-domain co-simulation of power distribution network (PDN) and LEON3 processor with circuit-based noise tolerance techniques. The analysis shows that the model helps reduce pessimism in estimated timing slack by considering effects of PSN and CDC. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00		End of session Coffee Break in Exhibition Area