2.4 Physical Design for Cutting-edge Lithography

Time	Label	Presentation Title Authors
11:30	2.4.1	OPTIMIZATION FOR MULTIPLE PATTERNING LITHOGRAPHY WITH CUTTING PROCESS AND BEYOND Speaker: Jian Kuang, The Chinese University of Hong Kong, HK Authors: Jian Kuang and Evangeline F. Y. Young, The Chinese University of Hong Kong, HK Abstract Multiple Patterning Lithography (MPL) is indispensable for producing sub-22nm devices. Recently, multiple patterning with cutting (MPC) was proposed. For example, in triple patterning with cutting (LELECUT), the first two masks are used to do double patterning, whereas the third mask is used to cut off the unwanted parts. In this paper, we will systematically study the problem of cut candidate generation, and propose a flow to optimally minimize the manufacturing cost for standard cell based design with MPC. We will further extend the optimization flow to handle multiple patterning with e-beam cuts. Experiments demonstrate the effectiveness of the proposed algorithms. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.4.2	A FAST MANUFACTURABILITY AWARE OPTICAL PROXIMITY CORRECTION (OPC) ALGORITHM WITH ADAPTIVE WAFER IMAGE ESTIMATION Speaker: Ahmed Awad, Tokyo Institute of Technology, JP Authors: Ahmed Awad¹, Atsushi Takahashi¹ and Chikaaki Kodama² ¹Tokyo Institute of Technology, JP; ²Toshiba Corporation, JP Abstract Aggressive Optical Proximity Correction (OPC) has been widely adopted in optical lithography to preserve circuit performance for sub-20nm technology nodes. However, complex mask patterns are outputted resulting in large mask manufacturability cost and large computational time. In this paper, we propose a fast OPC algorithm in which intensity estimation during OPC is improved for better pattern fidelity and in which post processing to effectively improve mask manufacturability with preserving acceptable pattern fidelity is executed. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.4.3	REDUNDANT VIA INSERTION IN DIRECTED SELF-ASSEMBLY LITHOGRAPHY Speaker: Woohyun Chung, Korea Advanced Institute of Science and Technology, KR Authors: Woohyun Chung, Seongbo Shim and Youngsoo Shin, Korea Advanced Institute of Science and Technology, KR Abstract In directed self-assembly lithography (DSAL), vias that are located close are clustered and patterned together. A large and complex cluster, however, is not allowed in this process due to its potential danger of pattern failure. We address redundant via insertion in DSAL. The goal is to insert maximum number of redundant vias while adjacent vias do not form a large and complex cluster. The problem is formulated as maximum independent set (MIS) of a conflict graph. Experiments demonstrate 13% more redundant vias inserted compared to simple-minded approach, basic insertion with no consideration of DSAL followed by removal of redundant vias in large and complex clusters. We also introduce DSA defect probability in order to quantitatively define which clusters should be allowed during insertion process. Download Paper (PDF; Only available from the DATE venue WiFi)
12:45	2.4.4	IMPROVED PERFORMANCE OF 3DIC IMPLEMENTATIONS THROUGH INHERENT AWARENESS OF MIX-AND-MATCH DIE STACKING Speaker: Andrew B. Kahng, UCSD, US Authors: Kwangsoo Han, Andrew B. Kahng and Jiajia Li, University of California, San Diego, US Abstract 3D logic-logic integration is an important future lever for continued cost and density scaling value propositions in the semiconductor industry. In the 3DIC context, several works have proposed "mix-and- match" of multiple stacked die, according to binning information, to improve overall product yield. However, each of the stacked die in these works is independently designed: there is no holistic "design for eventual stacking" of any of the die. Separately, many approaches have been proposed for design partitioning and implementation with multiple die, including 3D stacked-die implementation. However, the signoff criteria used to implement such a multi-die solution must necessarily validate timing correctness for all combinations of process conditions on the multiple die. To our knowledge, no previous work has examined the fundamental issue of design partitioning and signoff specifically for mix- and-match die stacking. In this work, we study performance improvements of 3DIC implementation that leverage knowledge of mix-and-match die stacking during manufacturing. We propose partitioning methodologies to partition timing-critical paths across tiers to explicitly optimize the signed-off timing across the reduced set of corner combinations that can be produced by the stacked-die manufacturing. These include both an ILP- based methodology and a heuristic with novel maximum-cut partitioning, solved by semidefinite programming, and a signoff timing-aware FM optimization. We also extend two existing 3DIC implementation flows to incorporate mix-and-match-aware partitioning and signoff, demonstrating the simplicity of adopting our techniques. Experimental results show that our optimization flow achieves up to 16% timing improvement as compared to the existing 3DIC implementation flow in the context of mix-and-match die stacking. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00	IP1-4, 544	GRID-BASED SELF-ALIGNED QUADRUPLE PATTERNING AWARE TWO DIMENSIONAL ROUTING PATTERN Speaker: Atsushi Takahashi, Tokyo Institute of Technology, JP Authors: Takeshi Ihara¹, Toshiyuki Hongo¹, Atsushi Takahashi¹ and Chikaaki Kodama² ¹Tokyo Institute of Technology, JP; ²Toshiba, JP Abstract Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node. Although various routing algorithms for SAQP have been proposed, it is not easy to find a dense SAQP compliant routing pattern efficiently. Even though a grid for SAQP compliant routing pattern was proposed, it is not easy to find a valid routing pattern on the grid. The routing pattern of SAQP on the grid consists of three types of routing. Among them, third type has turn prohibition constraint on the grid. Typical routing algorithms often fail to find a valid routing for third type. In this paper, SAQP compliant two dimensional routing patterns are found effectively on the grid by finding an optimal valid tertiary pattern. Experiments show that SAQP compliant routing patterns are found efficiently. Download Paper (PDF; Only available from the DATE venue WiFi)
13:01	IP1-5, 356	PRACTICAL ILP-BASED ROUTING OF STANDARD CELLS Speaker: Rung-Bin Lin, Yuan Ze University, TW Authors: Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin and Rung-Bin Lin, Yuan Ze University, TW Abstract This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing of many cells that cannot be routed by an industrial one. Download Paper (PDF; Only available from the DATE venue WiFi)
13:02	IP1-6, 732	A PROCEDURE FOR IMPROVING THE DISTRIBUTION OF CONGESTION IN GLOBAL ROUTING Speaker: Azadeh Davoodi, University of Wisconsin - Madison, US Authors: Daohang Shi, Azadeh Davoodi and Jeffrey Linderoth, University of Wisconsin - Madison, US Abstract This work introduces a procedure which takes as input a global routing solution that is already improved for routability based on the traditional total overﬂow (TOF) metric, and then improves the distribution of congestion without increasing the TOF. Our router is able to signiﬁcantly decrease the number of edges in undesirable ranges of congestion by optimizing a convex piece-wise linear penalty function. The penalties are ﬂexible and may be speciﬁed by the user. In our experiments, using the already-optimized global routing solutions of the ISPD'11 benchmarks—mostly have 0 units of TOF—we show the number of edges which are utilized very close to capacity can be signiﬁcantly reduced. This work is the ﬁrst to explicitly target improving the distribution of edge congestion corresponding to an already-optimized global routing solution without sacriﬁcing the TOF. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session Lunch Break in Großer Saal + Saal 1

Time

Label

Presentation Title
Authors

11:30

2.4.1

OPTIMIZATION FOR MULTIPLE PATTERNING LITHOGRAPHY WITH CUTTING PROCESS AND BEYOND
Speaker:
Jian Kuang, The Chinese University of Hong Kong, HK
Authors:
Jian Kuang and Evangeline F. Y. Young, The Chinese University of Hong Kong, HK
Abstract
Multiple Patterning Lithography (MPL) is indispensable for producing sub-22nm devices. Recently, multiple patterning with cutting (MPC) was proposed. For example, in triple patterning with cutting (LELECUT), the first two masks are used to do double patterning, whereas the third mask is used to cut off the unwanted parts. In this paper, we will systematically study the problem of cut candidate generation, and propose a flow to optimally minimize the manufacturing cost for standard cell based design with MPC. We will further extend the optimization flow to handle multiple patterning with e-beam cuts. Experiments demonstrate the effectiveness of the proposed algorithms.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

2.4.2

A FAST MANUFACTURABILITY AWARE OPTICAL PROXIMITY CORRECTION (OPC) ALGORITHM WITH ADAPTIVE WAFER IMAGE ESTIMATION
Speaker:
Ahmed Awad, Tokyo Institute of Technology, JP
Authors:
Ahmed Awad¹, Atsushi Takahashi¹ and Chikaaki Kodama²
¹Tokyo Institute of Technology, JP; ²Toshiba Corporation, JP
Abstract
Aggressive Optical Proximity Correction (OPC) has been widely adopted in optical lithography to preserve circuit performance for sub-20nm technology nodes. However, complex mask patterns are outputted resulting in large mask manufacturability cost and large computational time. In this paper, we propose a fast OPC algorithm in which intensity estimation during OPC is improved for better pattern fidelity and in which post processing to effectively improve mask manufacturability with preserving acceptable pattern fidelity is executed.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

2.4.3

REDUNDANT VIA INSERTION IN DIRECTED SELF-ASSEMBLY LITHOGRAPHY
Speaker:
Woohyun Chung, Korea Advanced Institute of Science and Technology, KR
Authors:
Woohyun Chung, Seongbo Shim and Youngsoo Shin, Korea Advanced Institute of Science and Technology, KR
Abstract
In directed self-assembly lithography (DSAL), vias that are located close are clustered and patterned together. A large and complex cluster, however, is not allowed in this process due to its potential danger of pattern failure. We address redundant via insertion in DSAL. The goal is to insert maximum number of redundant vias while adjacent vias do not form a large and complex cluster. The problem is formulated as maximum independent set (MIS) of a conflict graph. Experiments demonstrate 13% more redundant vias inserted compared to simple-minded approach, basic insertion with no consideration of DSAL followed by removal of redundant vias in large and complex clusters. We also introduce DSA defect probability in order to quantitatively define which clusters should be allowed during insertion process.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:45

2.4.4

IMPROVED PERFORMANCE OF 3DIC IMPLEMENTATIONS THROUGH INHERENT AWARENESS OF MIX-AND-MATCH DIE STACKING
Speaker:
Andrew B. Kahng, UCSD, US
Authors:
Kwangsoo Han, Andrew B. Kahng and Jiajia Li, University of California, San Diego, US
Abstract
3D logic-logic integration is an important future lever for continued cost and density scaling value propositions in the semiconductor industry. In the 3DIC context, several works have proposed "mix-and- match" of multiple stacked die, according to binning information, to improve overall product yield. However, each of the stacked die in these works is independently designed: there is no holistic "design for eventual stacking" of any of the die. Separately, many approaches have been proposed for design partitioning and implementation with multiple die, including 3D stacked-die implementation. However, the signoff criteria used to implement such a multi-die solution must necessarily validate timing correctness for all combinations of process conditions on the multiple die. To our knowledge, no previous work has examined the fundamental issue of design partitioning and signoff specifically for mix- and-match die stacking. In this work, we study performance improvements of 3DIC implementation that leverage knowledge of mix-and-match die stacking during manufacturing. We propose partitioning methodologies to partition timing-critical paths across tiers to explicitly optimize the signed-off timing across the reduced set of corner combinations that can be produced by the stacked-die manufacturing. These include both an ILP- based methodology and a heuristic with novel maximum-cut partitioning, solved by semidefinite programming, and a signoff timing-aware FM optimization. We also extend two existing 3DIC implementation flows to incorporate mix-and-match-aware partitioning and signoff, demonstrating the simplicity of adopting our techniques. Experimental results show that our optimization flow achieves up to 16% timing improvement as compared to the existing 3DIC implementation flow in the context of mix-and-match die stacking.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

IP1-4, 544

GRID-BASED SELF-ALIGNED QUADRUPLE PATTERNING AWARE TWO DIMENSIONAL ROUTING PATTERN
Speaker:
Atsushi Takahashi, Tokyo Institute of Technology, JP
Authors:
Takeshi Ihara¹, Toshiyuki Hongo¹, Atsushi Takahashi¹ and Chikaaki Kodama²
¹Tokyo Institute of Technology, JP; ²Toshiba, JP
Abstract
Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node. Although various routing algorithms for SAQP have been proposed, it is not easy to find a dense SAQP compliant routing pattern efficiently. Even though a grid for SAQP compliant routing pattern was proposed, it is not easy to find a valid routing pattern on the grid. The routing pattern of SAQP on the grid consists of three types of routing. Among them, third type has turn prohibition constraint on the grid. Typical routing algorithms often fail to find a valid routing for third type. In this paper, SAQP compliant two dimensional routing patterns are found effectively on the grid by finding an optimal valid tertiary pattern. Experiments show that SAQP compliant routing patterns are found efficiently.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:01

IP1-5, 356

PRACTICAL ILP-BASED ROUTING OF STANDARD CELLS
Speaker:
Rung-Bin Lin, Yuan Ze University, TW
Authors:
Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin and Rung-Bin Lin, Yuan Ze University, TW
Abstract
This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing of many cells that cannot be routed by an industrial one.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:02

IP1-6, 732

A PROCEDURE FOR IMPROVING THE DISTRIBUTION OF CONGESTION IN GLOBAL ROUTING
Speaker:
Azadeh Davoodi, University of Wisconsin - Madison, US
Authors:
Daohang Shi, Azadeh Davoodi and Jeffrey Linderoth, University of Wisconsin - Madison, US
Abstract
This work introduces a procedure which takes as input a global routing solution that is already improved for routability based on the traditional total overﬂow (TOF) metric, and then improves the distribution of congestion without increasing the TOF. Our router is able to signiﬁcantly decrease the number of edges in undesirable ranges of congestion by optimizing a convex piece-wise linear penalty function. The penalties are ﬂexible and may be speciﬁed by the user. In our experiments, using the already-optimized global routing solutions of the ISPD'11 benchmarks—mostly have 0 units of TOF—we show the number of edges which are utilized very close to capacity can be signiﬁcantly reduced. This work is the ﬁrst to explicitly target improving the distribution of edge congestion corresponding to an already-optimized global routing solution without sacriﬁcing the TOF.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

End of session
Lunch Break in Großer Saal + Saal 1

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