Date: Tuesday 15 March 2016
Time: 11:30 - 13:00
Location / Room: Konferenz 6

Organisers:
Siddharth Garg, New York University, US
Michael Niemier, University of Notre Dame, South Bend, US

Chair:
Muhammad Shafique, Karlsruhe Institute of Technology (KIT), DE

Co-Chair:
Umit Ogras, Arizona State University, US

In 2014, Jörg Henkel organized a "hot topic" special session that provided the DATE community with a snapshot of current research activities related to the grand challenge of dark silicon (DS). A primary purpose of that session was to introduce and engage the design automation community on this important problem. The lead presentation in the 2014 session was by Prof. Michael Taylor who spoke about the "landscape of the new dark silicon design regime." He defined a taxonomy termed "the four horsemen" for addressing the DS challenge. These are:- The shrinking horseman - i.e., addressing power density and thermal challenges caused by transistor scaling- The dim horseman - i.e., mitigating the DS challenge using near-threshold voltage scaling- The "deux ex machine" horseman - i.e., leveraging emerging and/or disruptive device technologies with more appealing power, performance and power density trade-offs- The specialization horseman - i.e., provisioning chips with a large number of application-specific acceleratorsTaylor notes: "Future chips are likely to employ not just one horseman, but all of them, in interesting and unique combinations.". In this embedded tutorial, we consider how researchers are leveraging new technologies - especially 3D integration and new transistor technologies - to address the DS problem. For continuity, we frame technology-based solutions in the context of the four-horsemen identified by Taylor in 2014.

Time	Label	Presentation Title Authors
11:30	2.2.1	TOWARDS PERFORMANCE AND RELIABILITY-EFFICIENT COMPUTING IN THE DARK SILICON ERA Speaker: Jörg Henkel, Karlsruhe Institute of Technology (KIT), DE Authors: Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman and Muhammad Shafique, Karlsruhe Institute of Technology (KIT), DE Abstract This paper discusses the power density and temperature induced issues in modern on-chip systems due to the high integration density and roadblock on the voltage scaling. First, the emerging dark silicon problem is discussed, and the corresponding critical research challenges in future chips are enumerated. Afterwards, we present an overview of some key research efforts and concepts that leverage dark silicon for performance and reliability optimization of on-chip systems under power or temperature constraints. The summarized works account for heat transfer inside a chip, as well as the varying performance and power trade-offs of gray silicon, that is, the potential benefits of operating at lower-than-nominal voltage and frequency levels. Besides realizing reliability-heterogeneous architectures, reliability of an on-chip system is enhanced by exploiting dark silicon for aging deceleration and resilience-driven resource management to mitigate soft-errors. Several of the tools discussed in this paper are available for download at http://ces.itec.kit.edu/download. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.2.2	TOWARDS NEAR-THRESHOLD SERVER PROCESSORS Speaker: David Atienza, École Polytechnique Fédérale de Lausanne (EPFL), CH Authors: Ali Pahlevan1, Javier Picorel1, Arash Pourhabibi Zarandi1, Davide Rossi2, Marina Zapater3, Andrea Bartolini4, Pablo G. del Valle1, David Atienza1, Luca Benini4 and Babak Falsafi1 1École Polytechnique Fédérale de Lausanne (EPFL), CH; 2ETH Zurich, CH; 3CEI Campus Moncloa, UCM-UPM, ES; 4Università di Bologna, IT Abstract The popularity of cloud computing has led to a dramatic increase in the number of data centers in the world. The ever-increasing computational demands along with the slowdown in technology scaling has ushered an era of power-limited servers. Techniques such as near-threshold computing (NTC) can be used to improve energy efficiency in the post-Dennard scaling era. This paper describes an architecture based on the FD-SOI process technology for near-threshold operation in servers. Our work explores the trade-offs in energy and performance when running a wide range of applications found in private and public clouds, ranging from traditional scale-out application, such as web search or media streaming, to virtualized banking applications. Our study demonstrates the benefits of near-threshold operation and proposes several directions to synergistically increase the energy proportionality of a near-threshold server. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.2.3	CAN BEYOND-CMOS DEVICES ILLUMINATE DARK SILICON? Speaker: Michael Niemier, University of Notre Dame, US Authors: Robert Perricone, X. Sharon Hu, Joseph Nahas and Michael Niemier, University of Notre Dame, US Abstract Throughout the last decade, the microprocessor industry has been struggling to preserve the benefits of Moore's Law scaling. The persistent scaling of CMOS technology no longer yields exponential performance gains due in part to the growth of dark silicon. With each subsequent technology node generation, power constraints resulting from factors such as sub-threshold leakage currents are projected to further limit the number of transistors that can be simultaneously pow- ered. To overcome the limits of CMOS devices, researchers are working to develop "beyond-CMOS" device technologies. To determine the most promising beyond-CMOS devices, it is necessary to benchmark them against CMOS. In this paper, we present the design and validation of an analytical bench- marking model that evaluates CMOS and beyond-CMOS devices at the architectural-level. Our model is built from the device to the architectural/application-level. Our target architecture is a symmetric multi-core processor executing highly parallel applications (i.e., PARSEC). As a case study, we select one class of promising beyond-CMOS devices, tunneling field-effect transistors, to evaluate against CMOS. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session Lunch Break in Großer Saal + Saal 1